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Linux 3.17-rc2
[linux/fpc-iii.git] / arch / powerpc / kernel / sysfs.c
blob67fd2fd2620ae64a2f44cced5a25b68d49877c50
1 #include <linux/device.h>
2 #include <linux/cpu.h>
3 #include <linux/smp.h>
4 #include <linux/percpu.h>
5 #include <linux/init.h>
6 #include <linux/sched.h>
7 #include <linux/export.h>
8 #include <linux/nodemask.h>
9 #include <linux/cpumask.h>
10 #include <linux/notifier.h>
11
12 #include <asm/current.h>
13 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/hvcall.h>
16 #include <asm/prom.h>
17 #include <asm/machdep.h>
18 #include <asm/smp.h>
19 #include <asm/pmc.h>
20 #include <asm/firmware.h>
21
22 #include "cacheinfo.h"
23
24 #ifdef CONFIG_PPC64
25 #include <asm/paca.h>
26 #include <asm/lppaca.h>
27 #endif
28
29 static DEFINE_PER_CPU(struct cpu, cpu_devices);
30
31 /*
32 * SMT snooze delay stuff, 64-bit only for now
33 */
34
35 #ifdef CONFIG_PPC64
36
37 /* Time in microseconds we delay before sleeping in the idle loop */
38 DEFINE_PER_CPU(long, smt_snooze_delay) = { 100 };
39
40 static ssize_t store_smt_snooze_delay(struct device *dev,
41 struct device_attribute *attr,
42 const char *buf,
43 size_t count)
44 {
45 struct cpu *cpu = container_of(dev, struct cpu, dev);
46 ssize_t ret;
47 long snooze;
48
49 ret = sscanf(buf, "%ld", &snooze);
50 if (ret != 1)
51 return -EINVAL;
52
53 per_cpu(smt_snooze_delay, cpu->dev.id) = snooze;
54 return count;
55 }
56
57 static ssize_t show_smt_snooze_delay(struct device *dev,
58 struct device_attribute *attr,
59 char *buf)
60 {
61 struct cpu *cpu = container_of(dev, struct cpu, dev);
62
63 return sprintf(buf, "%ld\n", per_cpu(smt_snooze_delay, cpu->dev.id));
64 }
65
66 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
67 store_smt_snooze_delay);
68
69 static int __init setup_smt_snooze_delay(char *str)
70 {
71 unsigned int cpu;
72 long snooze;
73
74 if (!cpu_has_feature(CPU_FTR_SMT))
75 return 1;
76
77 snooze = simple_strtol(str, NULL, 10);
78 for_each_possible_cpu(cpu)
79 per_cpu(smt_snooze_delay, cpu) = snooze;
80
81 return 1;
82 }
83 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
84
85 #endif /* CONFIG_PPC64 */
86
87 #ifdef CONFIG_PPC_FSL_BOOK3E
88 #define MAX_BIT 63
89
90 static u64 pw20_wt;
91 static u64 altivec_idle_wt;
92
93 static unsigned int get_idle_ticks_bit(u64 ns)
94 {
95 u64 cycle;
96
97 if (ns >= 10000)
98 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
99 else
100 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
101
102 if (!cycle)
103 return 0;
104
105 return ilog2(cycle);
106 }
107
108 static void do_show_pwrmgtcr0(void *val)
109 {
110 u32 *value = val;
111
112 *value = mfspr(SPRN_PWRMGTCR0);
113 }
114
115 static ssize_t show_pw20_state(struct device *dev,
116 struct device_attribute *attr, char *buf)
117 {
118 u32 value;
119 unsigned int cpu = dev->id;
120
121 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
122
123 value &= PWRMGTCR0_PW20_WAIT;
124
125 return sprintf(buf, "%u\n", value ? 1 : 0);
126 }
127
128 static void do_store_pw20_state(void *val)
129 {
130 u32 *value = val;
131 u32 pw20_state;
132
133 pw20_state = mfspr(SPRN_PWRMGTCR0);
134
135 if (*value)
136 pw20_state |= PWRMGTCR0_PW20_WAIT;
137 else
138 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
139
140 mtspr(SPRN_PWRMGTCR0, pw20_state);
141 }
142
143 static ssize_t store_pw20_state(struct device *dev,
144 struct device_attribute *attr,
145 const char *buf, size_t count)
146 {
147 u32 value;
148 unsigned int cpu = dev->id;
149
150 if (kstrtou32(buf, 0, &value))
151 return -EINVAL;
152
153 if (value > 1)
154 return -EINVAL;
155
156 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
157
158 return count;
159 }
160
161 static ssize_t show_pw20_wait_time(struct device *dev,
162 struct device_attribute *attr, char *buf)
163 {
164 u32 value;
165 u64 tb_cycle = 1;
166 u64 time;
167
168 unsigned int cpu = dev->id;
169
170 if (!pw20_wt) {
171 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
172 value = (value & PWRMGTCR0_PW20_ENT) >>
173 PWRMGTCR0_PW20_ENT_SHIFT;
174
175 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
176 /* convert ms to ns */
177 if (tb_ticks_per_usec > 1000) {
178 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
179 } else {
180 u32 rem_us;
181
182 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
183 &rem_us);
184 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
185 }
186 } else {
187 time = pw20_wt;
188 }
189
190 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
191 }
192
193 static void set_pw20_wait_entry_bit(void *val)
194 {
195 u32 *value = val;
196 u32 pw20_idle;
197
198 pw20_idle = mfspr(SPRN_PWRMGTCR0);
199
200 /* Set Automatic PW20 Core Idle Count */
201 /* clear count */
202 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
203
204 /* set count */
205 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
206
207 mtspr(SPRN_PWRMGTCR0, pw20_idle);
208 }
209
210 static ssize_t store_pw20_wait_time(struct device *dev,
211 struct device_attribute *attr,
212 const char *buf, size_t count)
213 {
214 u32 entry_bit;
215 u64 value;
216
217 unsigned int cpu = dev->id;
218
219 if (kstrtou64(buf, 0, &value))
220 return -EINVAL;
221
222 if (!value)
223 return -EINVAL;
224
225 entry_bit = get_idle_ticks_bit(value);
226 if (entry_bit > MAX_BIT)
227 return -EINVAL;
228
229 pw20_wt = value;
230
231 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
232 &entry_bit, 1);
233
234 return count;
235 }
236
237 static ssize_t show_altivec_idle(struct device *dev,
238 struct device_attribute *attr, char *buf)
239 {
240 u32 value;
241 unsigned int cpu = dev->id;
242
243 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
244
245 value &= PWRMGTCR0_AV_IDLE_PD_EN;
246
247 return sprintf(buf, "%u\n", value ? 1 : 0);
248 }
249
250 static void do_store_altivec_idle(void *val)
251 {
252 u32 *value = val;
253 u32 altivec_idle;
254
255 altivec_idle = mfspr(SPRN_PWRMGTCR0);
256
257 if (*value)
258 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
259 else
260 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
261
262 mtspr(SPRN_PWRMGTCR0, altivec_idle);
263 }
264
265 static ssize_t store_altivec_idle(struct device *dev,
266 struct device_attribute *attr,
267 const char *buf, size_t count)
268 {
269 u32 value;
270 unsigned int cpu = dev->id;
271
272 if (kstrtou32(buf, 0, &value))
273 return -EINVAL;
274
275 if (value > 1)
276 return -EINVAL;
277
278 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
279
280 return count;
281 }
282
283 static ssize_t show_altivec_idle_wait_time(struct device *dev,
284 struct device_attribute *attr, char *buf)
285 {
286 u32 value;
287 u64 tb_cycle = 1;
288 u64 time;
289
290 unsigned int cpu = dev->id;
291
292 if (!altivec_idle_wt) {
293 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
294 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
295 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
296
297 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
298 /* convert ms to ns */
299 if (tb_ticks_per_usec > 1000) {
300 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
301 } else {
302 u32 rem_us;
303
304 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
305 &rem_us);
306 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
307 }
308 } else {
309 time = altivec_idle_wt;
310 }
311
312 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
313 }
314
315 static void set_altivec_idle_wait_entry_bit(void *val)
316 {
317 u32 *value = val;
318 u32 altivec_idle;
319
320 altivec_idle = mfspr(SPRN_PWRMGTCR0);
321
322 /* Set Automatic AltiVec Idle Count */
323 /* clear count */
324 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
325
326 /* set count */
327 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
328
329 mtspr(SPRN_PWRMGTCR0, altivec_idle);
330 }
331
332 static ssize_t store_altivec_idle_wait_time(struct device *dev,
333 struct device_attribute *attr,
334 const char *buf, size_t count)
335 {
336 u32 entry_bit;
337 u64 value;
338
339 unsigned int cpu = dev->id;
340
341 if (kstrtou64(buf, 0, &value))
342 return -EINVAL;
343
344 if (!value)
345 return -EINVAL;
346
347 entry_bit = get_idle_ticks_bit(value);
348 if (entry_bit > MAX_BIT)
349 return -EINVAL;
350
351 altivec_idle_wt = value;
352
353 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
354 &entry_bit, 1);
355
356 return count;
357 }
358
359 /*
360 * Enable/Disable interface:
361 * 0, disable. 1, enable.
362 */
363 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
364 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
365
366 /*
367 * Set wait time interface:(Nanosecond)
368 * Example: Base on TBfreq is 41MHZ.
369 * 1~48(ns): TB[63]
370 * 49~97(ns): TB[62]
371 * 98~195(ns): TB[61]
372 * 196~390(ns): TB[60]
373 * 391~780(ns): TB[59]
374 * 781~1560(ns): TB[58]
375 * ...
376 */
377 static DEVICE_ATTR(pw20_wait_time, 0600,
378 show_pw20_wait_time,
379 store_pw20_wait_time);
380 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
381 show_altivec_idle_wait_time,
382 store_altivec_idle_wait_time);
383 #endif
384
385 /*
386 * Enabling PMCs will slow partition context switch times so we only do
387 * it the first time we write to the PMCs.
388 */
389
390 static DEFINE_PER_CPU(char, pmcs_enabled);
391
392 void ppc_enable_pmcs(void)
393 {
394 ppc_set_pmu_inuse(1);
395
396 /* Only need to enable them once */
397 if (__get_cpu_var(pmcs_enabled))
398 return;
399
400 __get_cpu_var(pmcs_enabled) = 1;
401
402 if (ppc_md.enable_pmcs)
403 ppc_md.enable_pmcs();
404 }
405 EXPORT_SYMBOL(ppc_enable_pmcs);
406
407 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
408 static void read_##NAME(void *val) \
409 { \
410 *(unsigned long *)val = mfspr(ADDRESS); \
411 } \
412 static void write_##NAME(void *val) \
413 { \
414 EXTRA; \
415 mtspr(ADDRESS, *(unsigned long *)val); \
416 }
417
418 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
419 static ssize_t show_##NAME(struct device *dev, \
420 struct device_attribute *attr, \
421 char *buf) \
422 { \
423 struct cpu *cpu = container_of(dev, struct cpu, dev); \
424 unsigned long val; \
425 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
426 return sprintf(buf, "%lx\n", val); \
427 } \
428 static ssize_t __used \
429 store_##NAME(struct device *dev, struct device_attribute *attr, \
430 const char *buf, size_t count) \
431 { \
432 struct cpu *cpu = container_of(dev, struct cpu, dev); \
433 unsigned long val; \
434 int ret = sscanf(buf, "%lx", &val); \
435 if (ret != 1) \
436 return -EINVAL; \
437 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
438 return count; \
439 }
440
441 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
442 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
443 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
444 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
445 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
446 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
447
448 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
449 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
450
451 /* Let's define all possible registers, we'll only hook up the ones
452 * that are implemented on the current processor
453 */
454
455 #if defined(CONFIG_PPC64)
456 #define HAS_PPC_PMC_CLASSIC 1
457 #define HAS_PPC_PMC_IBM 1
458 #define HAS_PPC_PMC_PA6T 1
459 #elif defined(CONFIG_6xx)
460 #define HAS_PPC_PMC_CLASSIC 1
461 #define HAS_PPC_PMC_IBM 1
462 #define HAS_PPC_PMC_G4 1
463 #endif
464
465
466 #ifdef HAS_PPC_PMC_CLASSIC
467 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
468 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
469 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
470 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
471 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
472 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
473 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
474 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
475
476 #ifdef HAS_PPC_PMC_G4
477 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
478 #endif
479
480 #ifdef CONFIG_PPC64
481 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
482 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
483
484 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
485 SYSFS_SPRSETUP(purr, SPRN_PURR);
486 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
487 SYSFS_SPRSETUP(pir, SPRN_PIR);
488
489 /*
490 Lets only enable read for phyp resources and
491 enable write when needed with a separate function.
492 Lets be conservative and default to pseries.
493 */
494 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
495 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
496 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
497 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
498
499 static unsigned long dscr_default;
500
501 static void read_dscr(void *val)
502 {
503 *(unsigned long *)val = get_paca()->dscr_default;
504 }
505
506 static void write_dscr(void *val)
507 {
508 get_paca()->dscr_default = *(unsigned long *)val;
509 if (!current->thread.dscr_inherit) {
510 current->thread.dscr = *(unsigned long *)val;
511 mtspr(SPRN_DSCR, *(unsigned long *)val);
512 }
513 }
514
515 SYSFS_SPRSETUP_SHOW_STORE(dscr);
516 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
517
518 static void add_write_permission_dev_attr(struct device_attribute *attr)
519 {
520 attr->attr.mode |= 0200;
521 }
522
523 static ssize_t show_dscr_default(struct device *dev,
524 struct device_attribute *attr, char *buf)
525 {
526 return sprintf(buf, "%lx\n", dscr_default);
527 }
528
529 static ssize_t __used store_dscr_default(struct device *dev,
530 struct device_attribute *attr, const char *buf,
531 size_t count)
532 {
533 unsigned long val;
534 int ret = 0;
535
536 ret = sscanf(buf, "%lx", &val);
537 if (ret != 1)
538 return -EINVAL;
539 dscr_default = val;
540
541 on_each_cpu(write_dscr, &val, 1);
542
543 return count;
544 }
545
546 static DEVICE_ATTR(dscr_default, 0600,
547 show_dscr_default, store_dscr_default);
548
549 static void sysfs_create_dscr_default(void)
550 {
551 int err = 0;
552 if (cpu_has_feature(CPU_FTR_DSCR))
553 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
554 }
555 #endif /* CONFIG_PPC64 */
556
557 #ifdef HAS_PPC_PMC_PA6T
558 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
559 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
560 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
561 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
562 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
563 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
564 #ifdef CONFIG_DEBUG_KERNEL
565 SYSFS_SPRSETUP(hid0, SPRN_HID0);
566 SYSFS_SPRSETUP(hid1, SPRN_HID1);
567 SYSFS_SPRSETUP(hid4, SPRN_HID4);
568 SYSFS_SPRSETUP(hid5, SPRN_HID5);
569 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
570 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
571 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
572 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
573 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
574 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
575 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
576 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
577 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
578 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
579 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
580 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
581 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
582 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
583 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
584 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
585 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
586 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
587 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
588 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
589 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
590 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
591 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
592 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
593 #endif /* CONFIG_DEBUG_KERNEL */
594 #endif /* HAS_PPC_PMC_PA6T */
595
596 #ifdef HAS_PPC_PMC_IBM
597 static struct device_attribute ibm_common_attrs[] = {
598 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
599 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
600 };
601 #endif /* HAS_PPC_PMC_G4 */
602
603 #ifdef HAS_PPC_PMC_G4
604 static struct device_attribute g4_common_attrs[] = {
605 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
606 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
607 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
608 };
609 #endif /* HAS_PPC_PMC_G4 */
610
611 static struct device_attribute classic_pmc_attrs[] = {
612 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
613 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
614 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
615 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
616 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
617 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
618 #ifdef CONFIG_PPC64
619 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
620 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
621 #endif
622 };
623
624 #ifdef HAS_PPC_PMC_PA6T
625 static struct device_attribute pa6t_attrs[] = {
626 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
627 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
628 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
629 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
630 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
631 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
632 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
633 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
634 #ifdef CONFIG_DEBUG_KERNEL
635 __ATTR(hid0, 0600, show_hid0, store_hid0),
636 __ATTR(hid1, 0600, show_hid1, store_hid1),
637 __ATTR(hid4, 0600, show_hid4, store_hid4),
638 __ATTR(hid5, 0600, show_hid5, store_hid5),
639 __ATTR(ima0, 0600, show_ima0, store_ima0),
640 __ATTR(ima1, 0600, show_ima1, store_ima1),
641 __ATTR(ima2, 0600, show_ima2, store_ima2),
642 __ATTR(ima3, 0600, show_ima3, store_ima3),
643 __ATTR(ima4, 0600, show_ima4, store_ima4),
644 __ATTR(ima5, 0600, show_ima5, store_ima5),
645 __ATTR(ima6, 0600, show_ima6, store_ima6),
646 __ATTR(ima7, 0600, show_ima7, store_ima7),
647 __ATTR(ima8, 0600, show_ima8, store_ima8),
648 __ATTR(ima9, 0600, show_ima9, store_ima9),
649 __ATTR(imaat, 0600, show_imaat, store_imaat),
650 __ATTR(btcr, 0600, show_btcr, store_btcr),
651 __ATTR(pccr, 0600, show_pccr, store_pccr),
652 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
653 __ATTR(der, 0600, show_der, store_der),
654 __ATTR(mer, 0600, show_mer, store_mer),
655 __ATTR(ber, 0600, show_ber, store_ber),
656 __ATTR(ier, 0600, show_ier, store_ier),
657 __ATTR(sier, 0600, show_sier, store_sier),
658 __ATTR(siar, 0600, show_siar, store_siar),
659 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
660 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
661 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
662 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
663 #endif /* CONFIG_DEBUG_KERNEL */
664 };
665 #endif /* HAS_PPC_PMC_PA6T */
666 #endif /* HAS_PPC_PMC_CLASSIC */
667
668 static void register_cpu_online(unsigned int cpu)
669 {
670 struct cpu *c = &per_cpu(cpu_devices, cpu);
671 struct device *s = &c->dev;
672 struct device_attribute *attrs, *pmc_attrs;
673 int i, nattrs;
674
675 #ifdef CONFIG_PPC64
676 if (cpu_has_feature(CPU_FTR_SMT))
677 device_create_file(s, &dev_attr_smt_snooze_delay);
678 #endif
679
680 /* PMC stuff */
681 switch (cur_cpu_spec->pmc_type) {
682 #ifdef HAS_PPC_PMC_IBM
683 case PPC_PMC_IBM:
684 attrs = ibm_common_attrs;
685 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
686 pmc_attrs = classic_pmc_attrs;
687 break;
688 #endif /* HAS_PPC_PMC_IBM */
689 #ifdef HAS_PPC_PMC_G4
690 case PPC_PMC_G4:
691 attrs = g4_common_attrs;
692 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
693 pmc_attrs = classic_pmc_attrs;
694 break;
695 #endif /* HAS_PPC_PMC_G4 */
696 #ifdef HAS_PPC_PMC_PA6T
697 case PPC_PMC_PA6T:
698 /* PA Semi starts counting at PMC0 */
699 attrs = pa6t_attrs;
700 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
701 pmc_attrs = NULL;
702 break;
703 #endif /* HAS_PPC_PMC_PA6T */
704 default:
705 attrs = NULL;
706 nattrs = 0;
707 pmc_attrs = NULL;
708 }
709
710 for (i = 0; i < nattrs; i++)
711 device_create_file(s, &attrs[i]);
712
713 if (pmc_attrs)
714 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
715 device_create_file(s, &pmc_attrs[i]);
716
717 #ifdef CONFIG_PPC64
718 if (cpu_has_feature(CPU_FTR_MMCRA))
719 device_create_file(s, &dev_attr_mmcra);
720
721 if (cpu_has_feature(CPU_FTR_PURR)) {
722 if (!firmware_has_feature(FW_FEATURE_LPAR))
723 add_write_permission_dev_attr(&dev_attr_purr);
724 device_create_file(s, &dev_attr_purr);
725 }
726
727 if (cpu_has_feature(CPU_FTR_SPURR))
728 device_create_file(s, &dev_attr_spurr);
729
730 if (cpu_has_feature(CPU_FTR_DSCR))
731 device_create_file(s, &dev_attr_dscr);
732
733 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
734 device_create_file(s, &dev_attr_pir);
735 #endif /* CONFIG_PPC64 */
736
737 #ifdef CONFIG_PPC_FSL_BOOK3E
738 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
739 device_create_file(s, &dev_attr_pw20_state);
740 device_create_file(s, &dev_attr_pw20_wait_time);
741
742 device_create_file(s, &dev_attr_altivec_idle);
743 device_create_file(s, &dev_attr_altivec_idle_wait_time);
744 }
745 #endif
746 cacheinfo_cpu_online(cpu);
747 }
748
749 #ifdef CONFIG_HOTPLUG_CPU
750 static void unregister_cpu_online(unsigned int cpu)
751 {
752 struct cpu *c = &per_cpu(cpu_devices, cpu);
753 struct device *s = &c->dev;
754 struct device_attribute *attrs, *pmc_attrs;
755 int i, nattrs;
756
757 BUG_ON(!c->hotpluggable);
758
759 #ifdef CONFIG_PPC64
760 if (cpu_has_feature(CPU_FTR_SMT))
761 device_remove_file(s, &dev_attr_smt_snooze_delay);
762 #endif
763
764 /* PMC stuff */
765 switch (cur_cpu_spec->pmc_type) {
766 #ifdef HAS_PPC_PMC_IBM
767 case PPC_PMC_IBM:
768 attrs = ibm_common_attrs;
769 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
770 pmc_attrs = classic_pmc_attrs;
771 break;
772 #endif /* HAS_PPC_PMC_IBM */
773 #ifdef HAS_PPC_PMC_G4
774 case PPC_PMC_G4:
775 attrs = g4_common_attrs;
776 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
777 pmc_attrs = classic_pmc_attrs;
778 break;
779 #endif /* HAS_PPC_PMC_G4 */
780 #ifdef HAS_PPC_PMC_PA6T
781 case PPC_PMC_PA6T:
782 /* PA Semi starts counting at PMC0 */
783 attrs = pa6t_attrs;
784 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
785 pmc_attrs = NULL;
786 break;
787 #endif /* HAS_PPC_PMC_PA6T */
788 default:
789 attrs = NULL;
790 nattrs = 0;
791 pmc_attrs = NULL;
792 }
793
794 for (i = 0; i < nattrs; i++)
795 device_remove_file(s, &attrs[i]);
796
797 if (pmc_attrs)
798 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
799 device_remove_file(s, &pmc_attrs[i]);
800
801 #ifdef CONFIG_PPC64
802 if (cpu_has_feature(CPU_FTR_MMCRA))
803 device_remove_file(s, &dev_attr_mmcra);
804
805 if (cpu_has_feature(CPU_FTR_PURR))
806 device_remove_file(s, &dev_attr_purr);
807
808 if (cpu_has_feature(CPU_FTR_SPURR))
809 device_remove_file(s, &dev_attr_spurr);
810
811 if (cpu_has_feature(CPU_FTR_DSCR))
812 device_remove_file(s, &dev_attr_dscr);
813
814 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
815 device_remove_file(s, &dev_attr_pir);
816 #endif /* CONFIG_PPC64 */
817
818 #ifdef CONFIG_PPC_FSL_BOOK3E
819 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
820 device_remove_file(s, &dev_attr_pw20_state);
821 device_remove_file(s, &dev_attr_pw20_wait_time);
822
823 device_remove_file(s, &dev_attr_altivec_idle);
824 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
825 }
826 #endif
827 cacheinfo_cpu_offline(cpu);
828 }
829
830 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
831 ssize_t arch_cpu_probe(const char *buf, size_t count)
832 {
833 if (ppc_md.cpu_probe)
834 return ppc_md.cpu_probe(buf, count);
835
836 return -EINVAL;
837 }
838
839 ssize_t arch_cpu_release(const char *buf, size_t count)
840 {
841 if (ppc_md.cpu_release)
842 return ppc_md.cpu_release(buf, count);
843
844 return -EINVAL;
845 }
846 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
847
848 #endif /* CONFIG_HOTPLUG_CPU */
849
850 static int sysfs_cpu_notify(struct notifier_block *self,
851 unsigned long action, void *hcpu)
852 {
853 unsigned int cpu = (unsigned int)(long)hcpu;
854
855 switch (action) {
856 case CPU_ONLINE:
857 case CPU_ONLINE_FROZEN:
858 register_cpu_online(cpu);
859 break;
860 #ifdef CONFIG_HOTPLUG_CPU
861 case CPU_DEAD:
862 case CPU_DEAD_FROZEN:
863 unregister_cpu_online(cpu);
864 break;
865 #endif
866 }
867 return NOTIFY_OK;
868 }
869
870 static struct notifier_block sysfs_cpu_nb = {
871 .notifier_call = sysfs_cpu_notify,
872 };
873
874 static DEFINE_MUTEX(cpu_mutex);
875
876 int cpu_add_dev_attr(struct device_attribute *attr)
877 {
878 int cpu;
879
880 mutex_lock(&cpu_mutex);
881
882 for_each_possible_cpu(cpu) {
883 device_create_file(get_cpu_device(cpu), attr);
884 }
885
886 mutex_unlock(&cpu_mutex);
887 return 0;
888 }
889 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
890
891 int cpu_add_dev_attr_group(struct attribute_group *attrs)
892 {
893 int cpu;
894 struct device *dev;
895 int ret;
896
897 mutex_lock(&cpu_mutex);
898
899 for_each_possible_cpu(cpu) {
900 dev = get_cpu_device(cpu);
901 ret = sysfs_create_group(&dev->kobj, attrs);
902 WARN_ON(ret != 0);
903 }
904
905 mutex_unlock(&cpu_mutex);
906 return 0;
907 }
908 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
909
910
911 void cpu_remove_dev_attr(struct device_attribute *attr)
912 {
913 int cpu;
914
915 mutex_lock(&cpu_mutex);
916
917 for_each_possible_cpu(cpu) {
918 device_remove_file(get_cpu_device(cpu), attr);
919 }
920
921 mutex_unlock(&cpu_mutex);
922 }
923 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
924
925 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
926 {
927 int cpu;
928 struct device *dev;
929
930 mutex_lock(&cpu_mutex);
931
932 for_each_possible_cpu(cpu) {
933 dev = get_cpu_device(cpu);
934 sysfs_remove_group(&dev->kobj, attrs);
935 }
936
937 mutex_unlock(&cpu_mutex);
938 }
939 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
940
941
942 /* NUMA stuff */
943
944 #ifdef CONFIG_NUMA
945 static void register_nodes(void)
946 {
947 int i;
948
949 for (i = 0; i < MAX_NUMNODES; i++)
950 register_one_node(i);
951 }
952
953 int sysfs_add_device_to_node(struct device *dev, int nid)
954 {
955 struct node *node = node_devices[nid];
956 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
957 kobject_name(&dev->kobj));
958 }
959 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
960
961 void sysfs_remove_device_from_node(struct device *dev, int nid)
962 {
963 struct node *node = node_devices[nid];
964 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
965 }
966 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
967
968 #else
969 static void register_nodes(void)
970 {
971 return;
972 }
973
974 #endif
975
976 /* Only valid if CPU is present. */
977 static ssize_t show_physical_id(struct device *dev,
978 struct device_attribute *attr, char *buf)
979 {
980 struct cpu *cpu = container_of(dev, struct cpu, dev);
981
982 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
983 }
984 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
985
986 static int __init topology_init(void)
987 {
988 int cpu;
989
990 register_nodes();
991
992 cpu_notifier_register_begin();
993
994 for_each_possible_cpu(cpu) {
995 struct cpu *c = &per_cpu(cpu_devices, cpu);
996
997 /*
998 * For now, we just see if the system supports making
999 * the RTAS calls for CPU hotplug. But, there may be a
1000 * more comprehensive way to do this for an individual
1001 * CPU. For instance, the boot cpu might never be valid
1002 * for hotplugging.
1003 */
1004 if (ppc_md.cpu_die)
1005 c->hotpluggable = 1;
1006
1007 if (cpu_online(cpu) || c->hotpluggable) {
1008 register_cpu(c, cpu);
1009
1010 device_create_file(&c->dev, &dev_attr_physical_id);
1011 }
1012
1013 if (cpu_online(cpu))
1014 register_cpu_online(cpu);
1015 }
1016
1017 __register_cpu_notifier(&sysfs_cpu_nb);
1018
1019 cpu_notifier_register_done();
1020
1021 #ifdef CONFIG_PPC64
1022 sysfs_create_dscr_default();
1023 #endif /* CONFIG_PPC64 */
1024
1025 return 0;
1026 }
1027 subsys_initcall(topology_init);
Linux with added FPC-III support