2 * MPC8610 HPCD board specific routines
4 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
5 * Recode: Jason Jin <jason.jin@freescale.com>
6 * York Sun <yorksun@freescale.com>
8 * Rewrite the interrupt routing. remove the 8259PIC support,
9 * All the integrated device in ULI use sideband interrupt.
11 * Copyright 2008 Freescale Semiconductor Inc.
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
19 #include <linux/stddef.h>
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/interrupt.h>
23 #include <linux/kdev_t.h>
24 #include <linux/delay.h>
25 #include <linux/seq_file.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
32 #include <mm/mmu_decl.h>
37 #include <linux/of_platform.h>
38 #include <sysdev/fsl_pci.h>
39 #include <sysdev/fsl_soc.h>
40 #include <sysdev/simple_gpio.h>
41 #include <asm/fsl_guts.h>
45 static struct device_node
*pixis_node
;
46 static unsigned char *pixis_bdcfg0
, *pixis_arch
;
48 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
49 #define CLKDVDR_PXCKEN 0x80000000
50 #define CLKDVDR_PXCKINV 0x10000000
51 #define CLKDVDR_PXCKDLY 0x06000000
52 #define CLKDVDR_PXCLK_MASK 0x001F0000
55 static irqreturn_t
mpc8610_sw9_irq(int irq
, void *data
)
57 pr_debug("%s: PIXIS' event (sw9/wakeup) IRQ handled\n", __func__
);
61 static void __init
mpc8610_suspend_init(void)
69 irq
= irq_of_parse_and_map(pixis_node
, 0);
71 pr_err("%s: can't map pixis event IRQ.\n", __func__
);
75 ret
= request_irq(irq
, mpc8610_sw9_irq
, 0, "sw9:wakeup", NULL
);
77 pr_err("%s: can't request pixis event IRQ: %d\n",
79 irq_dispose_mapping(irq
);
85 static inline void mpc8610_suspend_init(void) { }
86 #endif /* CONFIG_SUSPEND */
88 static struct of_device_id __initdata mpc8610_ids
[] = {
89 { .compatible
= "fsl,mpc8610-immr", },
90 { .compatible
= "fsl,mpc8610-guts", },
91 { .compatible
= "simple-bus", },
92 /* So that the DMA channel nodes can be probed individually: */
93 { .compatible
= "fsl,eloplus-dma", },
95 { .compatible
= "fsl,mpc8610-pci", },
96 { .compatible
= "fsl,mpc8641-pcie", },
100 static int __init
mpc8610_declare_of_platform_devices(void)
102 /* Firstly, register PIXIS GPIOs. */
103 simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
105 /* Enable wakeup on PIXIS' event IRQ. */
106 mpc8610_suspend_init();
108 /* Without this call, the SSI device driver won't get probed. */
109 of_platform_bus_probe(NULL
, mpc8610_ids
, NULL
);
113 machine_arch_initcall(mpc86xx_hpcd
, mpc8610_declare_of_platform_devices
);
115 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
118 * DIU Area Descriptor
120 * The MPC8610 reference manual shows the bits of the AD register in
121 * little-endian order, which causes the BLUE_C field to be split into two
122 * parts. To simplify the definition of the MAKE_AD() macro, we define the
123 * fields in big-endian order and byte-swap the result.
125 * So even though the registers don't look like they're in the
126 * same bit positions as they are on the P1022, the same value is written to
127 * the AD register on the MPC8610 and on the P1022.
129 #define AD_BYTE_F 0x10000000
130 #define AD_ALPHA_C_MASK 0x0E000000
131 #define AD_ALPHA_C_SHIFT 25
132 #define AD_BLUE_C_MASK 0x01800000
133 #define AD_BLUE_C_SHIFT 23
134 #define AD_GREEN_C_MASK 0x00600000
135 #define AD_GREEN_C_SHIFT 21
136 #define AD_RED_C_MASK 0x00180000
137 #define AD_RED_C_SHIFT 19
138 #define AD_PALETTE 0x00040000
139 #define AD_PIXEL_S_MASK 0x00030000
140 #define AD_PIXEL_S_SHIFT 16
141 #define AD_COMP_3_MASK 0x0000F000
142 #define AD_COMP_3_SHIFT 12
143 #define AD_COMP_2_MASK 0x00000F00
144 #define AD_COMP_2_SHIFT 8
145 #define AD_COMP_1_MASK 0x000000F0
146 #define AD_COMP_1_SHIFT 4
147 #define AD_COMP_0_MASK 0x0000000F
148 #define AD_COMP_0_SHIFT 0
150 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
151 cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
152 (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
153 (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
154 (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
155 (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
157 u32
mpc8610hpcd_get_pixel_format(enum fsl_diu_monitor_port port
,
158 unsigned int bits_per_pixel
)
160 static const u32 pixelformat
[][3] = {
162 MAKE_AD(3, 0, 2, 1, 3, 8, 8, 8, 8),
163 MAKE_AD(4, 2, 0, 1, 2, 8, 8, 8, 0),
164 MAKE_AD(4, 0, 2, 1, 1, 5, 6, 5, 0)
167 MAKE_AD(3, 2, 0, 1, 3, 8, 8, 8, 8),
168 MAKE_AD(4, 0, 2, 1, 2, 8, 8, 8, 0),
169 MAKE_AD(4, 2, 0, 1, 1, 5, 6, 5, 0)
172 unsigned int arch_monitor
;
174 /* The DVI port is mis-wired on revision 1 of this board. */
176 ((*pixis_arch
== 0x01) && (port
== FSL_DIU_PORT_DVI
)) ? 0 : 1;
178 switch (bits_per_pixel
) {
180 return pixelformat
[arch_monitor
][0];
182 return pixelformat
[arch_monitor
][1];
184 return pixelformat
[arch_monitor
][2];
186 pr_err("fsl-diu: unsupported pixel depth %u\n", bits_per_pixel
);
191 void mpc8610hpcd_set_gamma_table(enum fsl_diu_monitor_port port
,
192 char *gamma_table_base
)
195 if (port
== FSL_DIU_PORT_DLVDS
) {
196 for (i
= 0; i
< 256*3; i
++)
197 gamma_table_base
[i
] = (gamma_table_base
[i
] << 2) |
198 ((gamma_table_base
[i
] >> 6) & 0x03);
202 #define PX_BRDCFG0_DVISEL (1 << 3)
203 #define PX_BRDCFG0_DLINK (1 << 4)
204 #define PX_BRDCFG0_DIU_MASK (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
206 void mpc8610hpcd_set_monitor_port(enum fsl_diu_monitor_port port
)
209 case FSL_DIU_PORT_DVI
:
210 clrsetbits_8(pixis_bdcfg0
, PX_BRDCFG0_DIU_MASK
,
211 PX_BRDCFG0_DVISEL
| PX_BRDCFG0_DLINK
);
213 case FSL_DIU_PORT_LVDS
:
214 clrsetbits_8(pixis_bdcfg0
, PX_BRDCFG0_DIU_MASK
,
217 case FSL_DIU_PORT_DLVDS
:
218 clrbits8(pixis_bdcfg0
, PX_BRDCFG0_DIU_MASK
);
224 * mpc8610hpcd_set_pixel_clock: program the DIU's clock
226 * @pixclock: the wavelength, in picoseconds, of the clock
228 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock
)
230 struct device_node
*guts_np
= NULL
;
231 struct ccsr_guts __iomem
*guts
;
236 /* Map the global utilities registers. */
237 guts_np
= of_find_compatible_node(NULL
, NULL
, "fsl,mpc8610-guts");
239 pr_err("mpc8610hpcd: missing global utilities device node\n");
243 guts
= of_iomap(guts_np
, 0);
244 of_node_put(guts_np
);
246 pr_err("mpc8610hpcd: could not map global utilities device\n");
250 /* Convert pixclock from a wavelength to a frequency */
251 temp
= 1000000000000ULL;
252 do_div(temp
, pixclock
);
256 * 'pxclk' is the ratio of the platform clock to the pixel clock.
257 * On the MPC8610, the value programmed into CLKDVDR is the ratio
258 * minus one. The valid range of values is 2-31.
260 pxclk
= DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq
) - 1;
261 pxclk
= clamp_t(u32
, pxclk
, 2, 31);
263 /* Disable the pixel clock, and set it to non-inverted and no delay */
264 clrbits32(&guts
->clkdvdr
,
265 CLKDVDR_PXCKEN
| CLKDVDR_PXCKDLY
| CLKDVDR_PXCLK_MASK
);
267 /* Enable the clock and set the pxclk */
268 setbits32(&guts
->clkdvdr
, CLKDVDR_PXCKEN
| (pxclk
<< 16));
273 enum fsl_diu_monitor_port
274 mpc8610hpcd_valid_monitor_port(enum fsl_diu_monitor_port port
)
281 static void __init
mpc86xx_hpcd_setup_arch(void)
284 unsigned char *pixis
;
287 ppc_md
.progress("mpc86xx_hpcd_setup_arch()", 0);
289 fsl_pci_assign_primary();
291 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
292 diu_ops
.get_pixel_format
= mpc8610hpcd_get_pixel_format
;
293 diu_ops
.set_gamma_table
= mpc8610hpcd_set_gamma_table
;
294 diu_ops
.set_monitor_port
= mpc8610hpcd_set_monitor_port
;
295 diu_ops
.set_pixel_clock
= mpc8610hpcd_set_pixel_clock
;
296 diu_ops
.valid_monitor_port
= mpc8610hpcd_valid_monitor_port
;
299 pixis_node
= of_find_compatible_node(NULL
, NULL
, "fsl,fpga-pixis");
301 of_address_to_resource(pixis_node
, 0, &r
);
302 of_node_put(pixis_node
);
303 pixis
= ioremap(r
.start
, 32);
305 printk(KERN_ERR
"Err: can't map FPGA cfg register!\n");
308 pixis_bdcfg0
= pixis
+ 8;
309 pixis_arch
= pixis
+ 1;
311 printk(KERN_ERR
"Err: "
312 "can't find device node 'fsl,fpga-pixis'\n");
314 printk("MPC86xx HPCD board from Freescale Semiconductor\n");
318 * Called very early, device-tree isn't unflattened
320 static int __init
mpc86xx_hpcd_probe(void)
322 unsigned long root
= of_get_flat_dt_root();
324 if (of_flat_dt_is_compatible(root
, "fsl,MPC8610HPCD"))
325 return 1; /* Looks good */
330 static long __init
mpc86xx_time_init(void)
334 /* Set the time base to zero */
338 temp
= mfspr(SPRN_HID0
);
340 mtspr(SPRN_HID0
, temp
);
341 asm volatile("isync");
346 define_machine(mpc86xx_hpcd
) {
347 .name
= "MPC86xx HPCD",
348 .probe
= mpc86xx_hpcd_probe
,
349 .setup_arch
= mpc86xx_hpcd_setup_arch
,
350 .init_IRQ
= mpc86xx_init_irq
,
351 .get_irq
= mpic_get_irq
,
352 .restart
= fsl_rstcr_restart
,
353 .time_init
= mpc86xx_time_init
,
354 .calibrate_decr
= generic_calibrate_decr
,
355 .progress
= udbg_progress
,
357 .pcibios_fixup_bus
= fsl_pcibios_fixup_bus
,