arch/powerpc/sysdev/ehv_pic.c

   1 /*
   2  *  Driver for ePAPR Embedded Hypervisor PIC
   3  *
   4  *  Copyright 2008-2011 Freescale Semiconductor, Inc.
   5  *
   6  *  Author: Ashish Kalra <ashish.kalra@freescale.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public License
   9  * version 2.  This program is licensed "as is" without any warranty of any
  10  * kind, whether express or implied.
  11  */
  12
  13 #include <linux/types.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/smp.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/slab.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/smp.h>
  27 #include <asm/machdep.h>
  28 #include <asm/ehv_pic.h>
  29 #include <asm/fsl_hcalls.h>
  30
  31 static struct ehv_pic *global_ehv_pic;
  32 static DEFINE_SPINLOCK(ehv_pic_lock);
  33
  34 static u32 hwirq_intspec[NR_EHV_PIC_INTS];
  35 static u32 __iomem *mpic_percpu_base_vaddr;
  36
  37 #define IRQ_TYPE_MPIC_DIRECT 4
  38 #define MPIC_EOI  0x00B0
  39
  40 /*
  41  * Linux descriptor level callbacks
  42  */
  43
  44 void ehv_pic_unmask_irq(struct irq_data *d)
  45 {
  46         unsigned int src = virq_to_hw(d->irq);
  47
  48         ev_int_set_mask(src, 0);
  49 }
  50
  51 void ehv_pic_mask_irq(struct irq_data *d)
  52 {
  53         unsigned int src = virq_to_hw(d->irq);
  54
  55         ev_int_set_mask(src, 1);
  56 }
  57
  58 void ehv_pic_end_irq(struct irq_data *d)
  59 {
  60         unsigned int src = virq_to_hw(d->irq);
  61
  62         ev_int_eoi(src);
  63 }
  64
  65 void ehv_pic_direct_end_irq(struct irq_data *d)
  66 {
  67         out_be32(mpic_percpu_base_vaddr + MPIC_EOI / 4, 0);
  68 }
  69
  70 int ehv_pic_set_affinity(struct irq_data *d, const struct cpumask *dest,
  71                          bool force)
  72 {
  73         unsigned int src = virq_to_hw(d->irq);
  74         unsigned int config, prio, cpu_dest;
  75         int cpuid = irq_choose_cpu(dest);
  76         unsigned long flags;
  77
  78         spin_lock_irqsave(&ehv_pic_lock, flags);
  79         ev_int_get_config(src, &config, &prio, &cpu_dest);
  80         ev_int_set_config(src, config, prio, cpuid);
  81         spin_unlock_irqrestore(&ehv_pic_lock, flags);
  82
  83         return IRQ_SET_MASK_OK;
  84 }
  85
  86 static unsigned int ehv_pic_type_to_vecpri(unsigned int type)
  87 {
  88         /* Now convert sense value */
  89
  90         switch (type & IRQ_TYPE_SENSE_MASK) {
  91         case IRQ_TYPE_EDGE_RISING:
  92                 return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
  93                        EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
  94
  95         case IRQ_TYPE_EDGE_FALLING:
  96         case IRQ_TYPE_EDGE_BOTH:
  97                 return EHV_PIC_INFO(VECPRI_SENSE_EDGE) |
  98                        EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
  99
 100         case IRQ_TYPE_LEVEL_HIGH:
 101                 return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
 102                        EHV_PIC_INFO(VECPRI_POLARITY_POSITIVE);
 103
 104         case IRQ_TYPE_LEVEL_LOW:
 105         default:
 106                 return EHV_PIC_INFO(VECPRI_SENSE_LEVEL) |
 107                        EHV_PIC_INFO(VECPRI_POLARITY_NEGATIVE);
 108         }
 109 }
 110
 111 int ehv_pic_set_irq_type(struct irq_data *d, unsigned int flow_type)
 112 {
 113         unsigned int src = virq_to_hw(d->irq);
 114         unsigned int vecpri, vold, vnew, prio, cpu_dest;
 115         unsigned long flags;
 116
 117         if (flow_type == IRQ_TYPE_NONE)
 118                 flow_type = IRQ_TYPE_LEVEL_LOW;
 119
 120         irqd_set_trigger_type(d, flow_type);
 121
 122         vecpri = ehv_pic_type_to_vecpri(flow_type);
 123
 124         spin_lock_irqsave(&ehv_pic_lock, flags);
 125         ev_int_get_config(src, &vold, &prio, &cpu_dest);
 126         vnew = vold & ~(EHV_PIC_INFO(VECPRI_POLARITY_MASK) |
 127                         EHV_PIC_INFO(VECPRI_SENSE_MASK));
 128         vnew |= vecpri;
 129
 130         /*
 131          * TODO : Add specific interface call for platform to set
 132          * individual interrupt priorities.
 133          * platform currently using static/default priority for all ints
 134          */
 135
 136         prio = 8;
 137
 138         ev_int_set_config(src, vecpri, prio, cpu_dest);
 139
 140         spin_unlock_irqrestore(&ehv_pic_lock, flags);
 141         return IRQ_SET_MASK_OK_NOCOPY;
 142 }
 143
 144 static struct irq_chip ehv_pic_irq_chip = {
 145         .irq_mask       = ehv_pic_mask_irq,
 146         .irq_unmask     = ehv_pic_unmask_irq,
 147         .irq_eoi        = ehv_pic_end_irq,
 148         .irq_set_type   = ehv_pic_set_irq_type,
 149 };
 150
 151 static struct irq_chip ehv_pic_direct_eoi_irq_chip = {
 152         .irq_mask       = ehv_pic_mask_irq,
 153         .irq_unmask     = ehv_pic_unmask_irq,
 154         .irq_eoi        = ehv_pic_direct_end_irq,
 155         .irq_set_type   = ehv_pic_set_irq_type,
 156 };
 157
 158 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
 159 unsigned int ehv_pic_get_irq(void)
 160 {
 161         int irq;
 162
 163         BUG_ON(global_ehv_pic == NULL);
 164
 165         if (global_ehv_pic->coreint_flag)
 166                 irq = mfspr(SPRN_EPR); /* if core int mode */
 167         else
 168                 ev_int_iack(0, &irq); /* legacy mode */
 169
 170         if (irq == 0xFFFF)    /* 0xFFFF --> no irq is pending */
 171                 return NO_IRQ;
 172
 173         /*
 174          * this will also setup revmap[] in the slow path for the first
 175          * time, next calls will always use fast path by indexing revmap
 176          */
 177         return irq_linear_revmap(global_ehv_pic->irqhost, irq);
 178 }
 179
 180 static int ehv_pic_host_match(struct irq_domain *h, struct device_node *node)
 181 {
 182         /* Exact match, unless ehv_pic node is NULL */
 183         return h->of_node == NULL || h->of_node == node;
 184 }
 185
 186 static int ehv_pic_host_map(struct irq_domain *h, unsigned int virq,
 187                          irq_hw_number_t hw)
 188 {
 189         struct ehv_pic *ehv_pic = h->host_data;
 190         struct irq_chip *chip;
 191
 192         /* Default chip */
 193         chip = &ehv_pic->hc_irq;
 194
 195         if (mpic_percpu_base_vaddr)
 196                 if (hwirq_intspec[hw] & IRQ_TYPE_MPIC_DIRECT)
 197                         chip = &ehv_pic_direct_eoi_irq_chip;
 198
 199         irq_set_chip_data(virq, chip);
 200         /*
 201          * using handle_fasteoi_irq as our irq handler, this will
 202          * only call the eoi callback and suitable for the MPIC
 203          * controller which set ISR/IPR automatically and clear the
 204          * highest priority active interrupt in ISR/IPR when we do
 205          * a specific eoi
 206          */
 207         irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
 208
 209         /* Set default irq type */
 210         irq_set_irq_type(virq, IRQ_TYPE_NONE);
 211
 212         return 0;
 213 }
 214
 215 static int ehv_pic_host_xlate(struct irq_domain *h, struct device_node *ct,
 216                            const u32 *intspec, unsigned int intsize,
 217                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 218
 219 {
 220         /*
 221          * interrupt sense values coming from the guest device tree
 222          * interrupt specifiers can have four possible sense and
 223          * level encoding information and they need to
 224          * be translated between firmware type & linux type.
 225          */
 226
 227         static unsigned char map_of_senses_to_linux_irqtype[4] = {
 228                 IRQ_TYPE_EDGE_FALLING,
 229                 IRQ_TYPE_EDGE_RISING,
 230                 IRQ_TYPE_LEVEL_LOW,
 231                 IRQ_TYPE_LEVEL_HIGH,
 232         };
 233
 234         *out_hwirq = intspec[0];
 235         if (intsize > 1) {
 236                 hwirq_intspec[intspec[0]] = intspec[1];
 237                 *out_flags = map_of_senses_to_linux_irqtype[intspec[1] &
 238                                                         ~IRQ_TYPE_MPIC_DIRECT];
 239         } else {
 240                 *out_flags = IRQ_TYPE_NONE;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static const struct irq_domain_ops ehv_pic_host_ops = {
 247         .match = ehv_pic_host_match,
 248         .map = ehv_pic_host_map,
 249         .xlate = ehv_pic_host_xlate,
 250 };
 251
 252 void __init ehv_pic_init(void)
 253 {
 254         struct device_node *np, *np2;
 255         struct ehv_pic *ehv_pic;
 256         int coreint_flag = 1;
 257
 258         np = of_find_compatible_node(NULL, NULL, "epapr,hv-pic");
 259         if (!np) {
 260                 pr_err("ehv_pic_init: could not find epapr,hv-pic node\n");
 261                 return;
 262         }
 263
 264         if (!of_find_property(np, "has-external-proxy", NULL))
 265                 coreint_flag = 0;
 266
 267         ehv_pic = kzalloc(sizeof(struct ehv_pic), GFP_KERNEL);
 268         if (!ehv_pic) {
 269                 of_node_put(np);
 270                 return;
 271         }
 272
 273         ehv_pic->irqhost = irq_domain_add_linear(np, NR_EHV_PIC_INTS,
 274                                                  &ehv_pic_host_ops, ehv_pic);
 275         if (!ehv_pic->irqhost) {
 276                 of_node_put(np);
 277                 kfree(ehv_pic);
 278                 return;
 279         }
 280
 281         np2 = of_find_compatible_node(NULL, NULL, "fsl,hv-mpic-per-cpu");
 282         if (np2) {
 283                 mpic_percpu_base_vaddr = of_iomap(np2, 0);
 284                 if (!mpic_percpu_base_vaddr)
 285                         pr_err("ehv_pic_init: of_iomap failed\n");
 286
 287                 of_node_put(np2);
 288         }
 289
 290         ehv_pic->hc_irq = ehv_pic_irq_chip;
 291         ehv_pic->hc_irq.irq_set_affinity = ehv_pic_set_affinity;
 292         ehv_pic->coreint_flag = coreint_flag;
 293
 294         global_ehv_pic = ehv_pic;
 295         irq_set_default_host(global_ehv_pic->irqhost);
 296 }