arch/tile/include/asm/io.h

   1 /*
   2  * Copyright 2010 Tilera Corporation. All Rights Reserved.
   3  *
   4  *   This program is free software; you can redistribute it and/or
   5  *   modify it under the terms of the GNU General Public License
   6  *   as published by the Free Software Foundation, version 2.
   7  *
   8  *   This program is distributed in the hope that it will be useful, but
   9  *   WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *   MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  11  *   NON INFRINGEMENT.  See the GNU General Public License for
  12  *   more details.
  13  */
  14
  15 #ifndef _ASM_TILE_IO_H
  16 #define _ASM_TILE_IO_H
  17
  18 #include <linux/kernel.h>
  19 #include <linux/bug.h>
  20 #include <asm/page.h>
  21
  22 /* Maximum PCI I/O space address supported. */
  23 #define IO_SPACE_LIMIT 0xffffffff
  24
  25 /*
  26  * Convert a physical pointer to a virtual kernel pointer for /dev/mem
  27  * access.
  28  */
  29 #define xlate_dev_mem_ptr(p)    __va(p)
  30
  31 /*
  32  * Convert a virtual cached pointer to an uncached pointer.
  33  */
  34 #define xlate_dev_kmem_ptr(p)   p
  35
  36 /*
  37  * Change "struct page" to physical address.
  38  */
  39 #define page_to_phys(page)    ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
  40
  41 /*
  42  * Some places try to pass in an loff_t for PHYSADDR (?!), so we cast it to
  43  * long before casting it to a pointer to avoid compiler warnings.
  44  */
  45 #if CHIP_HAS_MMIO()
  46 extern void __iomem *ioremap(resource_size_t offset, unsigned long size);
  47 extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size,
  48         pgprot_t pgprot);
  49 extern void iounmap(volatile void __iomem *addr);
  50 #else
  51 #define ioremap(physaddr, size) ((void __iomem *)(unsigned long)(physaddr))
  52 #define iounmap(addr)           ((void)0)
  53 #endif
  54
  55 #define ioremap_nocache(physaddr, size)         ioremap(physaddr, size)
  56 #define ioremap_wc(physaddr, size)              ioremap(physaddr, size)
  57 #define ioremap_writethrough(physaddr, size)    ioremap(physaddr, size)
  58 #define ioremap_fullcache(physaddr, size)       ioremap(physaddr, size)
  59
  60 #define mmiowb()
  61
  62 /* Conversion between virtual and physical mappings.  */
  63 #define mm_ptov(addr)           ((void *)phys_to_virt(addr))
  64 #define mm_vtop(addr)           ((unsigned long)virt_to_phys(addr))
  65
  66 #if CHIP_HAS_MMIO()
  67
  68 /*
  69  * We use inline assembly to guarantee that the compiler does not
  70  * split an access into multiple byte-sized accesses as it might
  71  * sometimes do if a register data structure is marked "packed".
  72  * Obviously on tile we can't tolerate such an access being
  73  * actually unaligned, but we want to avoid the case where the
  74  * compiler conservatively would generate multiple accesses even
  75  * for an aligned read or write.
  76  */
  77
  78 static inline u8 __raw_readb(const volatile void __iomem *addr)
  79 {
  80         return *(const volatile u8 __force *)addr;
  81 }
  82
  83 static inline u16 __raw_readw(const volatile void __iomem *addr)
  84 {
  85         u16 ret;
  86         asm volatile("ld2u %0, %1" : "=r" (ret) : "r" (addr));
  87         barrier();
  88         return le16_to_cpu(ret);
  89 }
  90
  91 static inline u32 __raw_readl(const volatile void __iomem *addr)
  92 {
  93         u32 ret;
  94         /* Sign-extend to conform to u32 ABI sign-extension convention. */
  95         asm volatile("ld4s %0, %1" : "=r" (ret) : "r" (addr));
  96         barrier();
  97         return le32_to_cpu(ret);
  98 }
  99
 100 static inline u64 __raw_readq(const volatile void __iomem *addr)
 101 {
 102         u64 ret;
 103         asm volatile("ld %0, %1" : "=r" (ret) : "r" (addr));
 104         barrier();
 105         return le64_to_cpu(ret);
 106 }
 107
 108 static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
 109 {
 110         *(volatile u8 __force *)addr = val;
 111 }
 112
 113 static inline void __raw_writew(u16 val, volatile void __iomem *addr)
 114 {
 115         asm volatile("st2 %0, %1" :: "r" (addr), "r" (cpu_to_le16(val)));
 116 }
 117
 118 static inline void __raw_writel(u32 val, volatile void __iomem *addr)
 119 {
 120         asm volatile("st4 %0, %1" :: "r" (addr), "r" (cpu_to_le32(val)));
 121 }
 122
 123 static inline void __raw_writeq(u64 val, volatile void __iomem *addr)
 124 {
 125         asm volatile("st %0, %1" :: "r" (addr), "r" (cpu_to_le64(val)));
 126 }
 127
 128 /*
 129  * The on-chip I/O hardware on tilegx is configured with VA=PA for the
 130  * kernel's PA range.  The low-level APIs and field names use "va" and
 131  * "void *" nomenclature, to be consistent with the general notion
 132  * that the addresses in question are virtualizable, but in the kernel
 133  * context we are actually manipulating PA values.  (In other contexts,
 134  * e.g. access from user space, we do in fact use real virtual addresses
 135  * in the va fields.)  To allow readers of the code to understand what's
 136  * happening, we direct their attention to this comment by using the
 137  * following two functions that just duplicate __va() and __pa().
 138  */
 139 typedef unsigned long tile_io_addr_t;
 140 static inline tile_io_addr_t va_to_tile_io_addr(void *va)
 141 {
 142         BUILD_BUG_ON(sizeof(phys_addr_t) != sizeof(tile_io_addr_t));
 143         return __pa(va);
 144 }
 145 static inline void *tile_io_addr_to_va(tile_io_addr_t tile_io_addr)
 146 {
 147         return __va(tile_io_addr);
 148 }
 149
 150 #else /* CHIP_HAS_MMIO() */
 151
 152 #ifdef CONFIG_PCI
 153
 154 extern u8 _tile_readb(unsigned long addr);
 155 extern u16 _tile_readw(unsigned long addr);
 156 extern u32 _tile_readl(unsigned long addr);
 157 extern u64 _tile_readq(unsigned long addr);
 158 extern void _tile_writeb(u8  val, unsigned long addr);
 159 extern void _tile_writew(u16 val, unsigned long addr);
 160 extern void _tile_writel(u32 val, unsigned long addr);
 161 extern void _tile_writeq(u64 val, unsigned long addr);
 162
 163 #define __raw_readb(addr) _tile_readb((unsigned long)addr)
 164 #define __raw_readw(addr) _tile_readw((unsigned long)addr)
 165 #define __raw_readl(addr) _tile_readl((unsigned long)addr)
 166 #define __raw_readq(addr) _tile_readq((unsigned long)addr)
 167 #define __raw_writeb(val, addr) _tile_writeb(val, (unsigned long)addr)
 168 #define __raw_writew(val, addr) _tile_writew(val, (unsigned long)addr)
 169 #define __raw_writel(val, addr) _tile_writel(val, (unsigned long)addr)
 170 #define __raw_writeq(val, addr) _tile_writeq(val, (unsigned long)addr)
 171
 172 #else /* CONFIG_PCI */
 173
 174 /*
 175  * The tilepro architecture does not support IOMEM unless PCI is enabled.
 176  * Unfortunately we can't yet simply not declare these methods,
 177  * since some generic code that compiles into the kernel, but
 178  * we never run, uses them unconditionally.
 179  */
 180
 181 static inline int iomem_panic(void)
 182 {
 183         panic("readb/writeb and friends do not exist on tile without PCI");
 184         return 0;
 185 }
 186
 187 static inline u8 readb(unsigned long addr)
 188 {
 189         return iomem_panic();
 190 }
 191
 192 static inline u16 _readw(unsigned long addr)
 193 {
 194         return iomem_panic();
 195 }
 196
 197 static inline u32 readl(unsigned long addr)
 198 {
 199         return iomem_panic();
 200 }
 201
 202 static inline u64 readq(unsigned long addr)
 203 {
 204         return iomem_panic();
 205 }
 206
 207 static inline void writeb(u8  val, unsigned long addr)
 208 {
 209         iomem_panic();
 210 }
 211
 212 static inline void writew(u16 val, unsigned long addr)
 213 {
 214         iomem_panic();
 215 }
 216
 217 static inline void writel(u32 val, unsigned long addr)
 218 {
 219         iomem_panic();
 220 }
 221
 222 static inline void writeq(u64 val, unsigned long addr)
 223 {
 224         iomem_panic();
 225 }
 226
 227 #endif /* CONFIG_PCI */
 228
 229 #endif /* CHIP_HAS_MMIO() */
 230
 231 #define readb __raw_readb
 232 #define readw __raw_readw
 233 #define readl __raw_readl
 234 #define readq __raw_readq
 235 #define writeb __raw_writeb
 236 #define writew __raw_writew
 237 #define writel __raw_writel
 238 #define writeq __raw_writeq
 239
 240 #define readb_relaxed readb
 241 #define readw_relaxed readw
 242 #define readl_relaxed readl
 243 #define readq_relaxed readq
 244
 245 #define ioread8 readb
 246 #define ioread16 readw
 247 #define ioread32 readl
 248 #define ioread64 readq
 249 #define iowrite8 writeb
 250 #define iowrite16 writew
 251 #define iowrite32 writel
 252 #define iowrite64 writeq
 253
 254 #if CHIP_HAS_MMIO() || defined(CONFIG_PCI)
 255
 256 static inline void memset_io(volatile void *dst, int val, size_t len)
 257 {
 258         size_t x;
 259         BUG_ON((unsigned long)dst & 0x3);
 260         val = (val & 0xff) * 0x01010101;
 261         for (x = 0; x < len; x += 4)
 262                 writel(val, dst + x);
 263 }
 264
 265 static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
 266                                  size_t len)
 267 {
 268         size_t x;
 269         BUG_ON((unsigned long)src & 0x3);
 270         for (x = 0; x < len; x += 4)
 271                 *(u32 *)(dst + x) = readl(src + x);
 272 }
 273
 274 static inline void memcpy_toio(volatile void __iomem *dst, const void *src,
 275                                 size_t len)
 276 {
 277         size_t x;
 278         BUG_ON((unsigned long)dst & 0x3);
 279         for (x = 0; x < len; x += 4)
 280                 writel(*(u32 *)(src + x), dst + x);
 281 }
 282
 283 #endif
 284
 285 #if CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO)
 286
 287 static inline u8 inb(unsigned long addr)
 288 {
 289         return readb((volatile void __iomem *) addr);
 290 }
 291
 292 static inline u16 inw(unsigned long addr)
 293 {
 294         return readw((volatile void __iomem *) addr);
 295 }
 296
 297 static inline u32 inl(unsigned long addr)
 298 {
 299         return readl((volatile void __iomem *) addr);
 300 }
 301
 302 static inline void outb(u8 b, unsigned long addr)
 303 {
 304         writeb(b, (volatile void __iomem *) addr);
 305 }
 306
 307 static inline void outw(u16 b, unsigned long addr)
 308 {
 309         writew(b, (volatile void __iomem *) addr);
 310 }
 311
 312 static inline void outl(u32 b, unsigned long addr)
 313 {
 314         writel(b, (volatile void __iomem *) addr);
 315 }
 316
 317 static inline void insb(unsigned long addr, void *buffer, int count)
 318 {
 319         if (count) {
 320                 u8 *buf = buffer;
 321                 do {
 322                         u8 x = inb(addr);
 323                         *buf++ = x;
 324                 } while (--count);
 325         }
 326 }
 327
 328 static inline void insw(unsigned long addr, void *buffer, int count)
 329 {
 330         if (count) {
 331                 u16 *buf = buffer;
 332                 do {
 333                         u16 x = inw(addr);
 334                         *buf++ = x;
 335                 } while (--count);
 336         }
 337 }
 338
 339 static inline void insl(unsigned long addr, void *buffer, int count)
 340 {
 341         if (count) {
 342                 u32 *buf = buffer;
 343                 do {
 344                         u32 x = inl(addr);
 345                         *buf++ = x;
 346                 } while (--count);
 347         }
 348 }
 349
 350 static inline void outsb(unsigned long addr, const void *buffer, int count)
 351 {
 352         if (count) {
 353                 const u8 *buf = buffer;
 354                 do {
 355                         outb(*buf++, addr);
 356                 } while (--count);
 357         }
 358 }
 359
 360 static inline void outsw(unsigned long addr, const void *buffer, int count)
 361 {
 362         if (count) {
 363                 const u16 *buf = buffer;
 364                 do {
 365                         outw(*buf++, addr);
 366                 } while (--count);
 367         }
 368 }
 369
 370 static inline void outsl(unsigned long addr, const void *buffer, int count)
 371 {
 372         if (count) {
 373                 const u32 *buf = buffer;
 374                 do {
 375                         outl(*buf++, addr);
 376                 } while (--count);
 377         }
 378 }
 379
 380 extern void __iomem *ioport_map(unsigned long port, unsigned int len);
 381 extern void ioport_unmap(void __iomem *addr);
 382
 383 #else
 384
 385 /*
 386  * The TilePro architecture does not support IOPORT, even with PCI.
 387  * Unfortunately we can't yet simply not declare these methods,
 388  * since some generic code that compiles into the kernel, but
 389  * we never run, uses them unconditionally.
 390  */
 391
 392 static inline long ioport_panic(void)
 393 {
 394 #ifdef __tilegx__
 395         panic("PCI IO space support is disabled. Configure the kernel with"
 396               " CONFIG_TILE_PCI_IO to enable it");
 397 #else
 398         panic("inb/outb and friends do not exist on tile");
 399 #endif
 400         return 0;
 401 }
 402
 403 static inline void __iomem *ioport_map(unsigned long port, unsigned int len)
 404 {
 405         pr_info("ioport_map: mapping IO resources is unsupported on tile.\n");
 406         return NULL;
 407 }
 408
 409 static inline void ioport_unmap(void __iomem *addr)
 410 {
 411         ioport_panic();
 412 }
 413
 414 static inline u8 inb(unsigned long addr)
 415 {
 416         return ioport_panic();
 417 }
 418
 419 static inline u16 inw(unsigned long addr)
 420 {
 421         return ioport_panic();
 422 }
 423
 424 static inline u32 inl(unsigned long addr)
 425 {
 426         return ioport_panic();
 427 }
 428
 429 static inline void outb(u8 b, unsigned long addr)
 430 {
 431         ioport_panic();
 432 }
 433
 434 static inline void outw(u16 b, unsigned long addr)
 435 {
 436         ioport_panic();
 437 }
 438
 439 static inline void outl(u32 b, unsigned long addr)
 440 {
 441         ioport_panic();
 442 }
 443
 444 static inline void insb(unsigned long addr, void *buffer, int count)
 445 {
 446         ioport_panic();
 447 }
 448
 449 static inline void insw(unsigned long addr, void *buffer, int count)
 450 {
 451         ioport_panic();
 452 }
 453
 454 static inline void insl(unsigned long addr, void *buffer, int count)
 455 {
 456         ioport_panic();
 457 }
 458
 459 static inline void outsb(unsigned long addr, const void *buffer, int count)
 460 {
 461         ioport_panic();
 462 }
 463
 464 static inline void outsw(unsigned long addr, const void *buffer, int count)
 465 {
 466         ioport_panic();
 467 }
 468
 469 static inline void outsl(unsigned long addr, const void *buffer, int count)
 470 {
 471         ioport_panic();
 472 }
 473
 474 #endif /* CHIP_HAS_MMIO() && defined(CONFIG_TILE_PCI_IO) */
 475
 476 #define inb_p(addr)     inb(addr)
 477 #define inw_p(addr)     inw(addr)
 478 #define inl_p(addr)     inl(addr)
 479 #define outb_p(x, addr) outb((x), (addr))
 480 #define outw_p(x, addr) outw((x), (addr))
 481 #define outl_p(x, addr) outl((x), (addr))
 482
 483 #define ioread16be(addr)        be16_to_cpu(ioread16(addr))
 484 #define ioread32be(addr)        be32_to_cpu(ioread32(addr))
 485 #define iowrite16be(v, addr)    iowrite16(be16_to_cpu(v), (addr))
 486 #define iowrite32be(v, addr)    iowrite32(be32_to_cpu(v), (addr))
 487
 488 #define ioread8_rep(p, dst, count) \
 489         insb((unsigned long) (p), (dst), (count))
 490 #define ioread16_rep(p, dst, count) \
 491         insw((unsigned long) (p), (dst), (count))
 492 #define ioread32_rep(p, dst, count) \
 493         insl((unsigned long) (p), (dst), (count))
 494
 495 #define iowrite8_rep(p, src, count) \
 496         outsb((unsigned long) (p), (src), (count))
 497 #define iowrite16_rep(p, src, count) \
 498         outsw((unsigned long) (p), (src), (count))
 499 #define iowrite32_rep(p, src, count) \
 500         outsl((unsigned long) (p), (src), (count))
 501
 502 #define virt_to_bus     virt_to_phys
 503 #define bus_to_virt     phys_to_virt
 504
 505 #endif /* _ASM_TILE_IO_H */