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media: v4l: rcar_fdp1: Change platform dependency to ARCH_RENESAS
[linux/fpc-iii.git] / sound / soc / codecs / tlv320aic31xx.c
blobbf92d36b8f8ab06ee1f3559981c1c9d510cb8129
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * ALSA SoC TLV320AIC31xx CODEC Driver
4 *
5 * Copyright (C) 2014-2017 Texas Instruments Incorporated - http://www.ti.com/
6 * Jyri Sarha <jsarha@ti.com>
7 *
8 * Based on ground work by: Ajit Kulkarni <x0175765@ti.com>
9 *
10 * The TLV320AIC31xx series of audio codecs are low-power, highly integrated
11 * high performance codecs which provides a stereo DAC, a mono ADC,
12 * and mono/stereo Class-D speaker driver.
13 */
14
15 #include <linux/module.h>
16 #include <linux/moduleparam.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/pm.h>
20 #include <linux/i2c.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/acpi.h>
24 #include <linux/of.h>
25 #include <linux/of_gpio.h>
26 #include <linux/slab.h>
27 #include <sound/core.h>
28 #include <sound/pcm.h>
29 #include <sound/pcm_params.h>
30 #include <sound/soc.h>
31 #include <sound/initval.h>
32 #include <sound/tlv.h>
33 #include <dt-bindings/sound/tlv320aic31xx-micbias.h>
34
35 #include "tlv320aic31xx.h"
36
37 static const struct reg_default aic31xx_reg_defaults[] = {
38 { AIC31XX_CLKMUX, 0x00 },
39 { AIC31XX_PLLPR, 0x11 },
40 { AIC31XX_PLLJ, 0x04 },
41 { AIC31XX_PLLDMSB, 0x00 },
42 { AIC31XX_PLLDLSB, 0x00 },
43 { AIC31XX_NDAC, 0x01 },
44 { AIC31XX_MDAC, 0x01 },
45 { AIC31XX_DOSRMSB, 0x00 },
46 { AIC31XX_DOSRLSB, 0x80 },
47 { AIC31XX_NADC, 0x01 },
48 { AIC31XX_MADC, 0x01 },
49 { AIC31XX_AOSR, 0x80 },
50 { AIC31XX_IFACE1, 0x00 },
51 { AIC31XX_DATA_OFFSET, 0x00 },
52 { AIC31XX_IFACE2, 0x00 },
53 { AIC31XX_BCLKN, 0x01 },
54 { AIC31XX_DACSETUP, 0x14 },
55 { AIC31XX_DACMUTE, 0x0c },
56 { AIC31XX_LDACVOL, 0x00 },
57 { AIC31XX_RDACVOL, 0x00 },
58 { AIC31XX_ADCSETUP, 0x00 },
59 { AIC31XX_ADCFGA, 0x80 },
60 { AIC31XX_ADCVOL, 0x00 },
61 { AIC31XX_HPDRIVER, 0x04 },
62 { AIC31XX_SPKAMP, 0x06 },
63 { AIC31XX_DACMIXERROUTE, 0x00 },
64 { AIC31XX_LANALOGHPL, 0x7f },
65 { AIC31XX_RANALOGHPR, 0x7f },
66 { AIC31XX_LANALOGSPL, 0x7f },
67 { AIC31XX_RANALOGSPR, 0x7f },
68 { AIC31XX_HPLGAIN, 0x02 },
69 { AIC31XX_HPRGAIN, 0x02 },
70 { AIC31XX_SPLGAIN, 0x00 },
71 { AIC31XX_SPRGAIN, 0x00 },
72 { AIC31XX_MICBIAS, 0x00 },
73 { AIC31XX_MICPGA, 0x80 },
74 { AIC31XX_MICPGAPI, 0x00 },
75 { AIC31XX_MICPGAMI, 0x00 },
76 };
77
78 static bool aic31xx_volatile(struct device *dev, unsigned int reg)
79 {
80 switch (reg) {
81 case AIC31XX_PAGECTL: /* regmap implementation requires this */
82 case AIC31XX_RESET: /* always clears after write */
83 case AIC31XX_OT_FLAG:
84 case AIC31XX_ADCFLAG:
85 case AIC31XX_DACFLAG1:
86 case AIC31XX_DACFLAG2:
87 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
88 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
89 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
90 case AIC31XX_INTRDACFLAG2:
91 case AIC31XX_INTRADCFLAG2:
92 return true;
93 }
94 return false;
95 }
96
97 static bool aic31xx_writeable(struct device *dev, unsigned int reg)
98 {
99 switch (reg) {
100 case AIC31XX_OT_FLAG:
101 case AIC31XX_ADCFLAG:
102 case AIC31XX_DACFLAG1:
103 case AIC31XX_DACFLAG2:
104 case AIC31XX_OFFLAG: /* Sticky interrupt flags */
105 case AIC31XX_INTRDACFLAG: /* Sticky interrupt flags */
106 case AIC31XX_INTRADCFLAG: /* Sticky interrupt flags */
107 case AIC31XX_INTRDACFLAG2:
108 case AIC31XX_INTRADCFLAG2:
109 return false;
110 }
111 return true;
112 }
113
114 static const struct regmap_range_cfg aic31xx_ranges[] = {
115 {
116 .range_min = 0,
117 .range_max = 12 * 128,
118 .selector_reg = AIC31XX_PAGECTL,
119 .selector_mask = 0xff,
120 .selector_shift = 0,
121 .window_start = 0,
122 .window_len = 128,
123 },
124 };
125
126 static const struct regmap_config aic31xx_i2c_regmap = {
127 .reg_bits = 8,
128 .val_bits = 8,
129 .writeable_reg = aic31xx_writeable,
130 .volatile_reg = aic31xx_volatile,
131 .reg_defaults = aic31xx_reg_defaults,
132 .num_reg_defaults = ARRAY_SIZE(aic31xx_reg_defaults),
133 .cache_type = REGCACHE_RBTREE,
134 .ranges = aic31xx_ranges,
135 .num_ranges = ARRAY_SIZE(aic31xx_ranges),
136 .max_register = 12 * 128,
137 };
138
139 static const char * const aic31xx_supply_names[] = {
140 "HPVDD",
141 "SPRVDD",
142 "SPLVDD",
143 "AVDD",
144 "IOVDD",
145 "DVDD",
146 };
147
148 #define AIC31XX_NUM_SUPPLIES ARRAY_SIZE(aic31xx_supply_names)
149
150 struct aic31xx_disable_nb {
151 struct notifier_block nb;
152 struct aic31xx_priv *aic31xx;
153 };
154
155 struct aic31xx_priv {
156 struct snd_soc_component *component;
157 u8 i2c_regs_status;
158 struct device *dev;
159 struct regmap *regmap;
160 enum aic31xx_type codec_type;
161 struct gpio_desc *gpio_reset;
162 int micbias_vg;
163 struct aic31xx_pdata pdata;
164 struct regulator_bulk_data supplies[AIC31XX_NUM_SUPPLIES];
165 struct aic31xx_disable_nb disable_nb[AIC31XX_NUM_SUPPLIES];
166 unsigned int sysclk;
167 u8 p_div;
168 int rate_div_line;
169 bool master_dapm_route_applied;
170 };
171
172 struct aic31xx_rate_divs {
173 u32 mclk_p;
174 u32 rate;
175 u8 pll_j;
176 u16 pll_d;
177 u16 dosr;
178 u8 ndac;
179 u8 mdac;
180 u8 aosr;
181 u8 nadc;
182 u8 madc;
183 };
184
185 /* ADC dividers can be disabled by configuring them to 0 */
186 static const struct aic31xx_rate_divs aic31xx_divs[] = {
187 /* mclk/p rate pll: j d dosr ndac mdac aors nadc madc */
188 /* 8k rate */
189 {12000000, 8000, 8, 1920, 128, 48, 2, 128, 48, 2},
190 {12000000, 8000, 8, 1920, 128, 32, 3, 128, 32, 3},
191 {12500000, 8000, 7, 8643, 128, 48, 2, 128, 48, 2},
192 /* 11.025k rate */
193 {12000000, 11025, 7, 5264, 128, 32, 2, 128, 32, 2},
194 {12000000, 11025, 8, 4672, 128, 24, 3, 128, 24, 3},
195 {12500000, 11025, 7, 2253, 128, 32, 2, 128, 32, 2},
196 /* 16k rate */
197 {12000000, 16000, 8, 1920, 128, 24, 2, 128, 24, 2},
198 {12000000, 16000, 8, 1920, 128, 16, 3, 128, 16, 3},
199 {12500000, 16000, 7, 8643, 128, 24, 2, 128, 24, 2},
200 /* 22.05k rate */
201 {12000000, 22050, 7, 5264, 128, 16, 2, 128, 16, 2},
202 {12000000, 22050, 8, 4672, 128, 12, 3, 128, 12, 3},
203 {12500000, 22050, 7, 2253, 128, 16, 2, 128, 16, 2},
204 /* 32k rate */
205 {12000000, 32000, 8, 1920, 128, 12, 2, 128, 12, 2},
206 {12000000, 32000, 8, 1920, 128, 8, 3, 128, 8, 3},
207 {12500000, 32000, 7, 8643, 128, 12, 2, 128, 12, 2},
208 /* 44.1k rate */
209 {12000000, 44100, 7, 5264, 128, 8, 2, 128, 8, 2},
210 {12000000, 44100, 8, 4672, 128, 6, 3, 128, 6, 3},
211 {12500000, 44100, 7, 2253, 128, 8, 2, 128, 8, 2},
212 /* 48k rate */
213 {12000000, 48000, 8, 1920, 128, 8, 2, 128, 8, 2},
214 {12000000, 48000, 7, 6800, 96, 5, 4, 96, 5, 4},
215 {12500000, 48000, 7, 8643, 128, 8, 2, 128, 8, 2},
216 /* 88.2k rate */
217 {12000000, 88200, 7, 5264, 64, 8, 2, 64, 8, 2},
218 {12000000, 88200, 8, 4672, 64, 6, 3, 64, 6, 3},
219 {12500000, 88200, 7, 2253, 64, 8, 2, 64, 8, 2},
220 /* 96k rate */
221 {12000000, 96000, 8, 1920, 64, 8, 2, 64, 8, 2},
222 {12000000, 96000, 7, 6800, 48, 5, 4, 48, 5, 4},
223 {12500000, 96000, 7, 8643, 64, 8, 2, 64, 8, 2},
224 /* 176.4k rate */
225 {12000000, 176400, 7, 5264, 32, 8, 2, 32, 8, 2},
226 {12000000, 176400, 8, 4672, 32, 6, 3, 32, 6, 3},
227 {12500000, 176400, 7, 2253, 32, 8, 2, 32, 8, 2},
228 /* 192k rate */
229 {12000000, 192000, 8, 1920, 32, 8, 2, 32, 8, 2},
230 {12000000, 192000, 7, 6800, 24, 5, 4, 24, 5, 4},
231 {12500000, 192000, 7, 8643, 32, 8, 2, 32, 8, 2},
232 };
233
234 static const char * const ldac_in_text[] = {
235 "Off", "Left Data", "Right Data", "Mono"
236 };
237
238 static const char * const rdac_in_text[] = {
239 "Off", "Right Data", "Left Data", "Mono"
240 };
241
242 static SOC_ENUM_SINGLE_DECL(ldac_in_enum, AIC31XX_DACSETUP, 4, ldac_in_text);
243
244 static SOC_ENUM_SINGLE_DECL(rdac_in_enum, AIC31XX_DACSETUP, 2, rdac_in_text);
245
246 static const char * const mic_select_text[] = {
247 "Off", "FFR 10 Ohm", "FFR 20 Ohm", "FFR 40 Ohm"
248 };
249
250 static SOC_ENUM_SINGLE_DECL(mic1lp_p_enum, AIC31XX_MICPGAPI, 6,
251 mic_select_text);
252 static SOC_ENUM_SINGLE_DECL(mic1rp_p_enum, AIC31XX_MICPGAPI, 4,
253 mic_select_text);
254 static SOC_ENUM_SINGLE_DECL(mic1lm_p_enum, AIC31XX_MICPGAPI, 2,
255 mic_select_text);
256
257 static SOC_ENUM_SINGLE_DECL(cm_m_enum, AIC31XX_MICPGAMI, 6, mic_select_text);
258 static SOC_ENUM_SINGLE_DECL(mic1lm_m_enum, AIC31XX_MICPGAMI, 4,
259 mic_select_text);
260
261 static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6350, 50, 0);
262 static const DECLARE_TLV_DB_SCALE(adc_fgain_tlv, 0, 10, 0);
263 static const DECLARE_TLV_DB_SCALE(adc_cgain_tlv, -2000, 50, 0);
264 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv, 0, 50, 0);
265 static const DECLARE_TLV_DB_SCALE(hp_drv_tlv, 0, 100, 0);
266 static const DECLARE_TLV_DB_SCALE(class_D_drv_tlv, 600, 600, 0);
267 static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -6350, 50, 0);
268 static const DECLARE_TLV_DB_SCALE(sp_vol_tlv, -6350, 50, 0);
269
270 /*
271 * controls to be exported to the user space
272 */
273 static const struct snd_kcontrol_new common31xx_snd_controls[] = {
274 SOC_DOUBLE_R_S_TLV("DAC Playback Volume", AIC31XX_LDACVOL,
275 AIC31XX_RDACVOL, 0, -127, 48, 7, 0, dac_vol_tlv),
276
277 SOC_DOUBLE_R("HP Driver Playback Switch", AIC31XX_HPLGAIN,
278 AIC31XX_HPRGAIN, 2, 1, 0),
279 SOC_DOUBLE_R_TLV("HP Driver Playback Volume", AIC31XX_HPLGAIN,
280 AIC31XX_HPRGAIN, 3, 0x09, 0, hp_drv_tlv),
281
282 SOC_DOUBLE_R_TLV("HP Analog Playback Volume", AIC31XX_LANALOGHPL,
283 AIC31XX_RANALOGHPR, 0, 0x7F, 1, hp_vol_tlv),
284 };
285
286 static const struct snd_kcontrol_new aic31xx_snd_controls[] = {
287 SOC_SINGLE_TLV("ADC Fine Capture Volume", AIC31XX_ADCFGA, 4, 4, 1,
288 adc_fgain_tlv),
289
290 SOC_SINGLE("ADC Capture Switch", AIC31XX_ADCFGA, 7, 1, 1),
291 SOC_DOUBLE_R_S_TLV("ADC Capture Volume", AIC31XX_ADCVOL, AIC31XX_ADCVOL,
292 0, -24, 40, 6, 0, adc_cgain_tlv),
293
294 SOC_SINGLE_TLV("Mic PGA Capture Volume", AIC31XX_MICPGA, 0,
295 119, 0, mic_pga_tlv),
296 };
297
298 static const struct snd_kcontrol_new aic311x_snd_controls[] = {
299 SOC_DOUBLE_R("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
300 AIC31XX_SPRGAIN, 2, 1, 0),
301 SOC_DOUBLE_R_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
302 AIC31XX_SPRGAIN, 3, 3, 0, class_D_drv_tlv),
303
304 SOC_DOUBLE_R_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
305 AIC31XX_RANALOGSPR, 0, 0x7F, 1, sp_vol_tlv),
306 };
307
308 static const struct snd_kcontrol_new aic310x_snd_controls[] = {
309 SOC_SINGLE("Speaker Driver Playback Switch", AIC31XX_SPLGAIN,
310 2, 1, 0),
311 SOC_SINGLE_TLV("Speaker Driver Playback Volume", AIC31XX_SPLGAIN,
312 3, 3, 0, class_D_drv_tlv),
313
314 SOC_SINGLE_TLV("Speaker Analog Playback Volume", AIC31XX_LANALOGSPL,
315 0, 0x7F, 1, sp_vol_tlv),
316 };
317
318 static const struct snd_kcontrol_new ldac_in_control =
319 SOC_DAPM_ENUM("DAC Left Input", ldac_in_enum);
320
321 static const struct snd_kcontrol_new rdac_in_control =
322 SOC_DAPM_ENUM("DAC Right Input", rdac_in_enum);
323
324 static int aic31xx_wait_bits(struct aic31xx_priv *aic31xx, unsigned int reg,
325 unsigned int mask, unsigned int wbits, int sleep,
326 int count)
327 {
328 unsigned int bits;
329 int counter = count;
330 int ret = regmap_read(aic31xx->regmap, reg, &bits);
331
332 while ((bits & mask) != wbits && counter && !ret) {
333 usleep_range(sleep, sleep * 2);
334 ret = regmap_read(aic31xx->regmap, reg, &bits);
335 counter--;
336 }
337 if ((bits & mask) != wbits) {
338 dev_err(aic31xx->dev,
339 "%s: Failed! 0x%x was 0x%x expected 0x%x (%d, 0x%x, %d us)\n",
340 __func__, reg, bits, wbits, ret, mask,
341 (count - counter) * sleep);
342 ret = -1;
343 }
344 return ret;
345 }
346
347 #define WIDGET_BIT(reg, shift) (((shift) << 8) | (reg))
348
349 static int aic31xx_dapm_power_event(struct snd_soc_dapm_widget *w,
350 struct snd_kcontrol *kcontrol, int event)
351 {
352 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
353 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
354 unsigned int reg = AIC31XX_DACFLAG1;
355 unsigned int mask;
356
357 switch (WIDGET_BIT(w->reg, w->shift)) {
358 case WIDGET_BIT(AIC31XX_DACSETUP, 7):
359 mask = AIC31XX_LDACPWRSTATUS_MASK;
360 break;
361 case WIDGET_BIT(AIC31XX_DACSETUP, 6):
362 mask = AIC31XX_RDACPWRSTATUS_MASK;
363 break;
364 case WIDGET_BIT(AIC31XX_HPDRIVER, 7):
365 mask = AIC31XX_HPLDRVPWRSTATUS_MASK;
366 break;
367 case WIDGET_BIT(AIC31XX_HPDRIVER, 6):
368 mask = AIC31XX_HPRDRVPWRSTATUS_MASK;
369 break;
370 case WIDGET_BIT(AIC31XX_SPKAMP, 7):
371 mask = AIC31XX_SPLDRVPWRSTATUS_MASK;
372 break;
373 case WIDGET_BIT(AIC31XX_SPKAMP, 6):
374 mask = AIC31XX_SPRDRVPWRSTATUS_MASK;
375 break;
376 case WIDGET_BIT(AIC31XX_ADCSETUP, 7):
377 mask = AIC31XX_ADCPWRSTATUS_MASK;
378 reg = AIC31XX_ADCFLAG;
379 break;
380 default:
381 dev_err(component->dev, "Unknown widget '%s' calling %s\n",
382 w->name, __func__);
383 return -EINVAL;
384 }
385
386 switch (event) {
387 case SND_SOC_DAPM_POST_PMU:
388 return aic31xx_wait_bits(aic31xx, reg, mask, mask, 5000, 100);
389 case SND_SOC_DAPM_POST_PMD:
390 return aic31xx_wait_bits(aic31xx, reg, mask, 0, 5000, 100);
391 default:
392 dev_dbg(component->dev,
393 "Unhandled dapm widget event %d from %s\n",
394 event, w->name);
395 }
396 return 0;
397 }
398
399 static const struct snd_kcontrol_new aic31xx_left_output_switches[] = {
400 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
401 SOC_DAPM_SINGLE("From MIC1LP", AIC31XX_DACMIXERROUTE, 5, 1, 0),
402 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 4, 1, 0),
403 };
404
405 static const struct snd_kcontrol_new aic31xx_right_output_switches[] = {
406 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
407 SOC_DAPM_SINGLE("From MIC1RP", AIC31XX_DACMIXERROUTE, 1, 1, 0),
408 };
409
410 static const struct snd_kcontrol_new dac31xx_left_output_switches[] = {
411 SOC_DAPM_SINGLE("From Left DAC", AIC31XX_DACMIXERROUTE, 6, 1, 0),
412 SOC_DAPM_SINGLE("From AIN1", AIC31XX_DACMIXERROUTE, 5, 1, 0),
413 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 4, 1, 0),
414 };
415
416 static const struct snd_kcontrol_new dac31xx_right_output_switches[] = {
417 SOC_DAPM_SINGLE("From Right DAC", AIC31XX_DACMIXERROUTE, 2, 1, 0),
418 SOC_DAPM_SINGLE("From AIN2", AIC31XX_DACMIXERROUTE, 1, 1, 0),
419 };
420
421 static const struct snd_kcontrol_new p_term_mic1lp =
422 SOC_DAPM_ENUM("MIC1LP P-Terminal", mic1lp_p_enum);
423
424 static const struct snd_kcontrol_new p_term_mic1rp =
425 SOC_DAPM_ENUM("MIC1RP P-Terminal", mic1rp_p_enum);
426
427 static const struct snd_kcontrol_new p_term_mic1lm =
428 SOC_DAPM_ENUM("MIC1LM P-Terminal", mic1lm_p_enum);
429
430 static const struct snd_kcontrol_new m_term_mic1lm =
431 SOC_DAPM_ENUM("MIC1LM M-Terminal", mic1lm_m_enum);
432
433 static const struct snd_kcontrol_new aic31xx_dapm_hpl_switch =
434 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGHPL, 7, 1, 0);
435
436 static const struct snd_kcontrol_new aic31xx_dapm_hpr_switch =
437 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGHPR, 7, 1, 0);
438
439 static const struct snd_kcontrol_new aic31xx_dapm_spl_switch =
440 SOC_DAPM_SINGLE("Switch", AIC31XX_LANALOGSPL, 7, 1, 0);
441
442 static const struct snd_kcontrol_new aic31xx_dapm_spr_switch =
443 SOC_DAPM_SINGLE("Switch", AIC31XX_RANALOGSPR, 7, 1, 0);
444
445 static int mic_bias_event(struct snd_soc_dapm_widget *w,
446 struct snd_kcontrol *kcontrol, int event)
447 {
448 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
449 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
450
451 switch (event) {
452 case SND_SOC_DAPM_POST_PMU:
453 /* change mic bias voltage to user defined */
454 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
455 AIC31XX_MICBIAS_MASK,
456 aic31xx->micbias_vg <<
457 AIC31XX_MICBIAS_SHIFT);
458 dev_dbg(component->dev, "%s: turned on\n", __func__);
459 break;
460 case SND_SOC_DAPM_PRE_PMD:
461 /* turn mic bias off */
462 snd_soc_component_update_bits(component, AIC31XX_MICBIAS,
463 AIC31XX_MICBIAS_MASK, 0);
464 dev_dbg(component->dev, "%s: turned off\n", __func__);
465 break;
466 }
467 return 0;
468 }
469
470 static const struct snd_soc_dapm_widget common31xx_dapm_widgets[] = {
471 SND_SOC_DAPM_AIF_IN("AIF IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
472
473 SND_SOC_DAPM_MUX("DAC Left Input",
474 SND_SOC_NOPM, 0, 0, &ldac_in_control),
475 SND_SOC_DAPM_MUX("DAC Right Input",
476 SND_SOC_NOPM, 0, 0, &rdac_in_control),
477 /* DACs */
478 SND_SOC_DAPM_DAC_E("DAC Left", "Left Playback",
479 AIC31XX_DACSETUP, 7, 0, aic31xx_dapm_power_event,
480 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
481
482 SND_SOC_DAPM_DAC_E("DAC Right", "Right Playback",
483 AIC31XX_DACSETUP, 6, 0, aic31xx_dapm_power_event,
484 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
485
486 /* HP */
487 SND_SOC_DAPM_SWITCH("HP Left", SND_SOC_NOPM, 0, 0,
488 &aic31xx_dapm_hpl_switch),
489 SND_SOC_DAPM_SWITCH("HP Right", SND_SOC_NOPM, 0, 0,
490 &aic31xx_dapm_hpr_switch),
491
492 /* Output drivers */
493 SND_SOC_DAPM_OUT_DRV_E("HPL Driver", AIC31XX_HPDRIVER, 7, 0,
494 NULL, 0, aic31xx_dapm_power_event,
495 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
496 SND_SOC_DAPM_OUT_DRV_E("HPR Driver", AIC31XX_HPDRIVER, 6, 0,
497 NULL, 0, aic31xx_dapm_power_event,
498 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_POST_PMU),
499
500 /* Mic Bias */
501 SND_SOC_DAPM_SUPPLY("MICBIAS", SND_SOC_NOPM, 0, 0, mic_bias_event,
502 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
503
504 /* Keep BCLK/WCLK enabled even if DAC/ADC is powered down */
505 SND_SOC_DAPM_SUPPLY("Activate I2S clocks", AIC31XX_IFACE2, 2, 0,
506 NULL, 0),
507
508 /* Outputs */
509 SND_SOC_DAPM_OUTPUT("HPL"),
510 SND_SOC_DAPM_OUTPUT("HPR"),
511 };
512
513 static const struct snd_soc_dapm_widget dac31xx_dapm_widgets[] = {
514 /* Inputs */
515 SND_SOC_DAPM_INPUT("AIN1"),
516 SND_SOC_DAPM_INPUT("AIN2"),
517
518 /* Output Mixers */
519 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
520 dac31xx_left_output_switches,
521 ARRAY_SIZE(dac31xx_left_output_switches)),
522 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
523 dac31xx_right_output_switches,
524 ARRAY_SIZE(dac31xx_right_output_switches)),
525 };
526
527 static const struct snd_soc_dapm_widget aic31xx_dapm_widgets[] = {
528 /* Inputs */
529 SND_SOC_DAPM_INPUT("MIC1LP"),
530 SND_SOC_DAPM_INPUT("MIC1RP"),
531 SND_SOC_DAPM_INPUT("MIC1LM"),
532
533 /* Input Selection to MIC_PGA */
534 SND_SOC_DAPM_MUX("MIC1LP P-Terminal", SND_SOC_NOPM, 0, 0,
535 &p_term_mic1lp),
536 SND_SOC_DAPM_MUX("MIC1RP P-Terminal", SND_SOC_NOPM, 0, 0,
537 &p_term_mic1rp),
538 SND_SOC_DAPM_MUX("MIC1LM P-Terminal", SND_SOC_NOPM, 0, 0,
539 &p_term_mic1lm),
540
541 /* ADC */
542 SND_SOC_DAPM_ADC_E("ADC", "Capture", AIC31XX_ADCSETUP, 7, 0,
543 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
544 SND_SOC_DAPM_POST_PMD),
545
546 SND_SOC_DAPM_MUX("MIC1LM M-Terminal", SND_SOC_NOPM, 0, 0,
547 &m_term_mic1lm),
548
549 /* Enabling & Disabling MIC Gain Ctl */
550 SND_SOC_DAPM_PGA("MIC_GAIN_CTL", AIC31XX_MICPGA,
551 7, 1, NULL, 0),
552
553 /* Output Mixers */
554 SND_SOC_DAPM_MIXER("Output Left", SND_SOC_NOPM, 0, 0,
555 aic31xx_left_output_switches,
556 ARRAY_SIZE(aic31xx_left_output_switches)),
557 SND_SOC_DAPM_MIXER("Output Right", SND_SOC_NOPM, 0, 0,
558 aic31xx_right_output_switches,
559 ARRAY_SIZE(aic31xx_right_output_switches)),
560
561 SND_SOC_DAPM_AIF_OUT("AIF OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
562 };
563
564 static const struct snd_soc_dapm_widget aic311x_dapm_widgets[] = {
565 /* AIC3111 and AIC3110 have stereo class-D amplifier */
566 SND_SOC_DAPM_OUT_DRV_E("SPL ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
567 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
568 SND_SOC_DAPM_POST_PMD),
569 SND_SOC_DAPM_OUT_DRV_E("SPR ClassD", AIC31XX_SPKAMP, 6, 0, NULL, 0,
570 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
571 SND_SOC_DAPM_POST_PMD),
572 SND_SOC_DAPM_SWITCH("Speaker Left", SND_SOC_NOPM, 0, 0,
573 &aic31xx_dapm_spl_switch),
574 SND_SOC_DAPM_SWITCH("Speaker Right", SND_SOC_NOPM, 0, 0,
575 &aic31xx_dapm_spr_switch),
576 SND_SOC_DAPM_OUTPUT("SPL"),
577 SND_SOC_DAPM_OUTPUT("SPR"),
578 };
579
580 /* AIC3100 and AIC3120 have only mono class-D amplifier */
581 static const struct snd_soc_dapm_widget aic310x_dapm_widgets[] = {
582 SND_SOC_DAPM_OUT_DRV_E("SPK ClassD", AIC31XX_SPKAMP, 7, 0, NULL, 0,
583 aic31xx_dapm_power_event, SND_SOC_DAPM_POST_PMU |
584 SND_SOC_DAPM_POST_PMD),
585 SND_SOC_DAPM_SWITCH("Speaker", SND_SOC_NOPM, 0, 0,
586 &aic31xx_dapm_spl_switch),
587 SND_SOC_DAPM_OUTPUT("SPK"),
588 };
589
590 static const struct snd_soc_dapm_route
591 common31xx_audio_map[] = {
592 /* DAC Input Routing */
593 {"DAC Left Input", "Left Data", "AIF IN"},
594 {"DAC Left Input", "Right Data", "AIF IN"},
595 {"DAC Left Input", "Mono", "AIF IN"},
596 {"DAC Right Input", "Left Data", "AIF IN"},
597 {"DAC Right Input", "Right Data", "AIF IN"},
598 {"DAC Right Input", "Mono", "AIF IN"},
599 {"DAC Left", NULL, "DAC Left Input"},
600 {"DAC Right", NULL, "DAC Right Input"},
601
602 /* HPL path */
603 {"HP Left", "Switch", "Output Left"},
604 {"HPL Driver", NULL, "HP Left"},
605 {"HPL", NULL, "HPL Driver"},
606
607 /* HPR path */
608 {"HP Right", "Switch", "Output Right"},
609 {"HPR Driver", NULL, "HP Right"},
610 {"HPR", NULL, "HPR Driver"},
611 };
612
613 static const struct snd_soc_dapm_route
614 dac31xx_audio_map[] = {
615 /* Left Output */
616 {"Output Left", "From Left DAC", "DAC Left"},
617 {"Output Left", "From AIN1", "AIN1"},
618 {"Output Left", "From AIN2", "AIN2"},
619
620 /* Right Output */
621 {"Output Right", "From Right DAC", "DAC Right"},
622 {"Output Right", "From AIN2", "AIN2"},
623 };
624
625 static const struct snd_soc_dapm_route
626 aic31xx_audio_map[] = {
627 /* Mic input */
628 {"MIC1LP P-Terminal", "FFR 10 Ohm", "MIC1LP"},
629 {"MIC1LP P-Terminal", "FFR 20 Ohm", "MIC1LP"},
630 {"MIC1LP P-Terminal", "FFR 40 Ohm", "MIC1LP"},
631 {"MIC1RP P-Terminal", "FFR 10 Ohm", "MIC1RP"},
632 {"MIC1RP P-Terminal", "FFR 20 Ohm", "MIC1RP"},
633 {"MIC1RP P-Terminal", "FFR 40 Ohm", "MIC1RP"},
634 {"MIC1LM P-Terminal", "FFR 10 Ohm", "MIC1LM"},
635 {"MIC1LM P-Terminal", "FFR 20 Ohm", "MIC1LM"},
636 {"MIC1LM P-Terminal", "FFR 40 Ohm", "MIC1LM"},
637
638 {"MIC1LM M-Terminal", "FFR 10 Ohm", "MIC1LM"},
639 {"MIC1LM M-Terminal", "FFR 20 Ohm", "MIC1LM"},
640 {"MIC1LM M-Terminal", "FFR 40 Ohm", "MIC1LM"},
641
642 {"MIC_GAIN_CTL", NULL, "MIC1LP P-Terminal"},
643 {"MIC_GAIN_CTL", NULL, "MIC1RP P-Terminal"},
644 {"MIC_GAIN_CTL", NULL, "MIC1LM P-Terminal"},
645 {"MIC_GAIN_CTL", NULL, "MIC1LM M-Terminal"},
646
647 {"ADC", NULL, "MIC_GAIN_CTL"},
648
649 {"AIF OUT", NULL, "ADC"},
650
651 /* Left Output */
652 {"Output Left", "From Left DAC", "DAC Left"},
653 {"Output Left", "From MIC1LP", "MIC1LP"},
654 {"Output Left", "From MIC1RP", "MIC1RP"},
655
656 /* Right Output */
657 {"Output Right", "From Right DAC", "DAC Right"},
658 {"Output Right", "From MIC1RP", "MIC1RP"},
659 };
660
661 static const struct snd_soc_dapm_route
662 aic311x_audio_map[] = {
663 /* SP L path */
664 {"Speaker Left", "Switch", "Output Left"},
665 {"SPL ClassD", NULL, "Speaker Left"},
666 {"SPL", NULL, "SPL ClassD"},
667
668 /* SP R path */
669 {"Speaker Right", "Switch", "Output Right"},
670 {"SPR ClassD", NULL, "Speaker Right"},
671 {"SPR", NULL, "SPR ClassD"},
672 };
673
674 static const struct snd_soc_dapm_route
675 aic310x_audio_map[] = {
676 /* SP L path */
677 {"Speaker", "Switch", "Output Left"},
678 {"SPK ClassD", NULL, "Speaker"},
679 {"SPK", NULL, "SPK ClassD"},
680 };
681
682 /*
683 * Always connected DAPM routes for codec clock master modes.
684 * If the codec is the master on the I2S bus, we need to power up components
685 * to have valid DAC_CLK.
686 *
687 * In order to have the I2S clocks on the bus either the DACs/ADC need to be
688 * enabled, or the P0/R29/D2 (Keep bclk/wclk in power down) need to be set.
689 *
690 * Otherwise the codec will not generate clocks on the bus.
691 */
692 static const struct snd_soc_dapm_route
693 common31xx_cm_audio_map[] = {
694 {"HPL", NULL, "AIF IN"},
695 {"HPR", NULL, "AIF IN"},
696
697 {"AIF IN", NULL, "Activate I2S clocks"},
698 };
699
700 static const struct snd_soc_dapm_route
701 aic31xx_cm_audio_map[] = {
702 {"AIF OUT", NULL, "MIC1LP"},
703 {"AIF OUT", NULL, "MIC1RP"},
704 {"AIF OUT", NULL, "MIC1LM"},
705
706 {"AIF OUT", NULL, "Activate I2S clocks"},
707 };
708
709 static int aic31xx_add_controls(struct snd_soc_component *component)
710 {
711 int ret = 0;
712 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
713
714 if (!(aic31xx->codec_type & DAC31XX_BIT))
715 ret = snd_soc_add_component_controls(
716 component, aic31xx_snd_controls,
717 ARRAY_SIZE(aic31xx_snd_controls));
718 if (ret)
719 return ret;
720
721 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT)
722 ret = snd_soc_add_component_controls(
723 component, aic311x_snd_controls,
724 ARRAY_SIZE(aic311x_snd_controls));
725 else
726 ret = snd_soc_add_component_controls(
727 component, aic310x_snd_controls,
728 ARRAY_SIZE(aic310x_snd_controls));
729
730 return ret;
731 }
732
733 static int aic31xx_add_widgets(struct snd_soc_component *component)
734 {
735 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
736 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
737 int ret = 0;
738
739 if (aic31xx->codec_type & DAC31XX_BIT) {
740 ret = snd_soc_dapm_new_controls(
741 dapm, dac31xx_dapm_widgets,
742 ARRAY_SIZE(dac31xx_dapm_widgets));
743 if (ret)
744 return ret;
745
746 ret = snd_soc_dapm_add_routes(dapm, dac31xx_audio_map,
747 ARRAY_SIZE(dac31xx_audio_map));
748 if (ret)
749 return ret;
750 } else {
751 ret = snd_soc_dapm_new_controls(
752 dapm, aic31xx_dapm_widgets,
753 ARRAY_SIZE(aic31xx_dapm_widgets));
754 if (ret)
755 return ret;
756
757 ret = snd_soc_dapm_add_routes(dapm, aic31xx_audio_map,
758 ARRAY_SIZE(aic31xx_audio_map));
759 if (ret)
760 return ret;
761 }
762
763 if (aic31xx->codec_type & AIC31XX_STEREO_CLASS_D_BIT) {
764 ret = snd_soc_dapm_new_controls(
765 dapm, aic311x_dapm_widgets,
766 ARRAY_SIZE(aic311x_dapm_widgets));
767 if (ret)
768 return ret;
769
770 ret = snd_soc_dapm_add_routes(dapm, aic311x_audio_map,
771 ARRAY_SIZE(aic311x_audio_map));
772 if (ret)
773 return ret;
774 } else {
775 ret = snd_soc_dapm_new_controls(
776 dapm, aic310x_dapm_widgets,
777 ARRAY_SIZE(aic310x_dapm_widgets));
778 if (ret)
779 return ret;
780
781 ret = snd_soc_dapm_add_routes(dapm, aic310x_audio_map,
782 ARRAY_SIZE(aic310x_audio_map));
783 if (ret)
784 return ret;
785 }
786
787 return 0;
788 }
789
790 static int aic31xx_setup_pll(struct snd_soc_component *component,
791 struct snd_pcm_hw_params *params)
792 {
793 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
794 int bclk_score = snd_soc_params_to_frame_size(params);
795 int mclk_p;
796 int bclk_n = 0;
797 int match = -1;
798 int i;
799
800 if (!aic31xx->sysclk || !aic31xx->p_div) {
801 dev_err(component->dev, "Master clock not supplied\n");
802 return -EINVAL;
803 }
804 mclk_p = aic31xx->sysclk / aic31xx->p_div;
805
806 /* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
807 snd_soc_component_update_bits(component, AIC31XX_CLKMUX,
808 AIC31XX_CODEC_CLKIN_MASK, AIC31XX_CODEC_CLKIN_PLL);
809 snd_soc_component_update_bits(component, AIC31XX_IFACE2,
810 AIC31XX_BDIVCLK_MASK, AIC31XX_DAC2BCLK);
811
812 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
813 if (aic31xx_divs[i].rate == params_rate(params) &&
814 aic31xx_divs[i].mclk_p == mclk_p) {
815 int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
816 snd_soc_params_to_frame_size(params);
817 int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
818 snd_soc_params_to_frame_size(params);
819 if (s < bclk_score && bn > 0) {
820 match = i;
821 bclk_n = bn;
822 bclk_score = s;
823 }
824 }
825 }
826
827 if (match == -1) {
828 dev_err(component->dev,
829 "%s: Sample rate (%u) and format not supported\n",
830 __func__, params_rate(params));
831 /* See bellow for details how fix this. */
832 return -EINVAL;
833 }
834 if (bclk_score != 0) {
835 dev_warn(component->dev, "Can not produce exact bitclock");
836 /* This is fine if using dsp format, but if using i2s
837 there may be trouble. To fix the issue edit the
838 aic31xx_divs table for your mclk and sample
839 rate. Details can be found from:
840 http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
841 Section: 5.6 CLOCK Generation and PLL
842 */
843 }
844 i = match;
845
846 /* PLL configuration */
847 snd_soc_component_update_bits(component, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
848 (aic31xx->p_div << 4) | 0x01);
849 snd_soc_component_write(component, AIC31XX_PLLJ, aic31xx_divs[i].pll_j);
850
851 snd_soc_component_write(component, AIC31XX_PLLDMSB,
852 aic31xx_divs[i].pll_d >> 8);
853 snd_soc_component_write(component, AIC31XX_PLLDLSB,
854 aic31xx_divs[i].pll_d & 0xff);
855
856 /* DAC dividers configuration */
857 snd_soc_component_update_bits(component, AIC31XX_NDAC, AIC31XX_PLL_MASK,
858 aic31xx_divs[i].ndac);
859 snd_soc_component_update_bits(component, AIC31XX_MDAC, AIC31XX_PLL_MASK,
860 aic31xx_divs[i].mdac);
861
862 snd_soc_component_write(component, AIC31XX_DOSRMSB, aic31xx_divs[i].dosr >> 8);
863 snd_soc_component_write(component, AIC31XX_DOSRLSB, aic31xx_divs[i].dosr & 0xff);
864
865 /* ADC dividers configuration. Write reset value 1 if not used. */
866 snd_soc_component_update_bits(component, AIC31XX_NADC, AIC31XX_PLL_MASK,
867 aic31xx_divs[i].nadc ? aic31xx_divs[i].nadc : 1);
868 snd_soc_component_update_bits(component, AIC31XX_MADC, AIC31XX_PLL_MASK,
869 aic31xx_divs[i].madc ? aic31xx_divs[i].madc : 1);
870
871 snd_soc_component_write(component, AIC31XX_AOSR, aic31xx_divs[i].aosr);
872
873 /* Bit clock divider configuration. */
874 snd_soc_component_update_bits(component, AIC31XX_BCLKN,
875 AIC31XX_PLL_MASK, bclk_n);
876
877 aic31xx->rate_div_line = i;
878
879 dev_dbg(component->dev,
880 "pll %d.%04d/%d dosr %d n %d m %d aosr %d n %d m %d bclk_n %d\n",
881 aic31xx_divs[i].pll_j,
882 aic31xx_divs[i].pll_d,
883 aic31xx->p_div,
884 aic31xx_divs[i].dosr,
885 aic31xx_divs[i].ndac,
886 aic31xx_divs[i].mdac,
887 aic31xx_divs[i].aosr,
888 aic31xx_divs[i].nadc,
889 aic31xx_divs[i].madc,
890 bclk_n
891 );
892
893 return 0;
894 }
895
896 static int aic31xx_hw_params(struct snd_pcm_substream *substream,
897 struct snd_pcm_hw_params *params,
898 struct snd_soc_dai *dai)
899 {
900 struct snd_soc_component *component = dai->component;
901 u8 data = 0;
902
903 dev_dbg(component->dev, "## %s: width %d rate %d\n",
904 __func__, params_width(params),
905 params_rate(params));
906
907 switch (params_width(params)) {
908 case 16:
909 break;
910 case 20:
911 data = (AIC31XX_WORD_LEN_20BITS <<
912 AIC31XX_IFACE1_DATALEN_SHIFT);
913 break;
914 case 24:
915 data = (AIC31XX_WORD_LEN_24BITS <<
916 AIC31XX_IFACE1_DATALEN_SHIFT);
917 break;
918 case 32:
919 data = (AIC31XX_WORD_LEN_32BITS <<
920 AIC31XX_IFACE1_DATALEN_SHIFT);
921 break;
922 default:
923 dev_err(component->dev, "%s: Unsupported width %d\n",
924 __func__, params_width(params));
925 return -EINVAL;
926 }
927
928 snd_soc_component_update_bits(component, AIC31XX_IFACE1,
929 AIC31XX_IFACE1_DATALEN_MASK,
930 data);
931
932 return aic31xx_setup_pll(component, params);
933 }
934
935 static int aic31xx_dac_mute(struct snd_soc_dai *codec_dai, int mute)
936 {
937 struct snd_soc_component *component = codec_dai->component;
938
939 if (mute) {
940 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
941 AIC31XX_DACMUTE_MASK,
942 AIC31XX_DACMUTE_MASK);
943 } else {
944 snd_soc_component_update_bits(component, AIC31XX_DACMUTE,
945 AIC31XX_DACMUTE_MASK, 0x0);
946 }
947
948 return 0;
949 }
950
951 static int aic31xx_clock_master_routes(struct snd_soc_component *component,
952 unsigned int fmt)
953 {
954 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
955 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
956 int ret;
957
958 fmt &= SND_SOC_DAIFMT_MASTER_MASK;
959 if (fmt == SND_SOC_DAIFMT_CBS_CFS &&
960 aic31xx->master_dapm_route_applied) {
961 /*
962 * Remove the DAPM route(s) for codec clock master modes,
963 * if applied
964 */
965 ret = snd_soc_dapm_del_routes(dapm, common31xx_cm_audio_map,
966 ARRAY_SIZE(common31xx_cm_audio_map));
967 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
968 ret = snd_soc_dapm_del_routes(dapm,
969 aic31xx_cm_audio_map,
970 ARRAY_SIZE(aic31xx_cm_audio_map));
971
972 if (ret)
973 return ret;
974
975 aic31xx->master_dapm_route_applied = false;
976 } else if (fmt != SND_SOC_DAIFMT_CBS_CFS &&
977 !aic31xx->master_dapm_route_applied) {
978 /*
979 * Add the needed DAPM route(s) for codec clock master modes,
980 * if it is not done already
981 */
982 ret = snd_soc_dapm_add_routes(dapm, common31xx_cm_audio_map,
983 ARRAY_SIZE(common31xx_cm_audio_map));
984 if (!ret && !(aic31xx->codec_type & DAC31XX_BIT))
985 ret = snd_soc_dapm_add_routes(dapm,
986 aic31xx_cm_audio_map,
987 ARRAY_SIZE(aic31xx_cm_audio_map));
988
989 if (ret)
990 return ret;
991
992 aic31xx->master_dapm_route_applied = true;
993 }
994
995 return 0;
996 }
997
998 static int aic31xx_set_dai_fmt(struct snd_soc_dai *codec_dai,
999 unsigned int fmt)
1000 {
1001 struct snd_soc_component *component = codec_dai->component;
1002 u8 iface_reg1 = 0;
1003 u8 iface_reg2 = 0;
1004 u8 dsp_a_val = 0;
1005
1006 dev_dbg(component->dev, "## %s: fmt = 0x%x\n", __func__, fmt);
1007
1008 /* set master/slave audio interface */
1009 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1010 case SND_SOC_DAIFMT_CBM_CFM:
1011 iface_reg1 |= AIC31XX_BCLK_MASTER | AIC31XX_WCLK_MASTER;
1012 break;
1013 case SND_SOC_DAIFMT_CBS_CFM:
1014 iface_reg1 |= AIC31XX_WCLK_MASTER;
1015 break;
1016 case SND_SOC_DAIFMT_CBM_CFS:
1017 iface_reg1 |= AIC31XX_BCLK_MASTER;
1018 break;
1019 case SND_SOC_DAIFMT_CBS_CFS:
1020 break;
1021 default:
1022 dev_err(component->dev, "Invalid DAI master/slave interface\n");
1023 return -EINVAL;
1024 }
1025
1026 /* signal polarity */
1027 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
1028 case SND_SOC_DAIFMT_NB_NF:
1029 break;
1030 case SND_SOC_DAIFMT_IB_NF:
1031 iface_reg2 |= AIC31XX_BCLKINV_MASK;
1032 break;
1033 default:
1034 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
1035 return -EINVAL;
1036 }
1037
1038 /* interface format */
1039 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
1040 case SND_SOC_DAIFMT_I2S:
1041 break;
1042 case SND_SOC_DAIFMT_DSP_A:
1043 dsp_a_val = 0x1; /* fall through */
1044 case SND_SOC_DAIFMT_DSP_B:
1045 /*
1046 * NOTE: This CODEC samples on the falling edge of BCLK in
1047 * DSP mode, this is inverted compared to what most DAIs
1048 * expect, so we invert for this mode
1049 */
1050 iface_reg2 ^= AIC31XX_BCLKINV_MASK;
1051 iface_reg1 |= (AIC31XX_DSP_MODE <<
1052 AIC31XX_IFACE1_DATATYPE_SHIFT);
1053 break;
1054 case SND_SOC_DAIFMT_RIGHT_J:
1055 iface_reg1 |= (AIC31XX_RIGHT_JUSTIFIED_MODE <<
1056 AIC31XX_IFACE1_DATATYPE_SHIFT);
1057 break;
1058 case SND_SOC_DAIFMT_LEFT_J:
1059 iface_reg1 |= (AIC31XX_LEFT_JUSTIFIED_MODE <<
1060 AIC31XX_IFACE1_DATATYPE_SHIFT);
1061 break;
1062 default:
1063 dev_err(component->dev, "Invalid DAI interface format\n");
1064 return -EINVAL;
1065 }
1066
1067 snd_soc_component_update_bits(component, AIC31XX_IFACE1,
1068 AIC31XX_IFACE1_DATATYPE_MASK |
1069 AIC31XX_IFACE1_MASTER_MASK,
1070 iface_reg1);
1071 snd_soc_component_update_bits(component, AIC31XX_DATA_OFFSET,
1072 AIC31XX_DATA_OFFSET_MASK,
1073 dsp_a_val);
1074 snd_soc_component_update_bits(component, AIC31XX_IFACE2,
1075 AIC31XX_BCLKINV_MASK,
1076 iface_reg2);
1077
1078 return aic31xx_clock_master_routes(component, fmt);
1079 }
1080
1081 static int aic31xx_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1082 int clk_id, unsigned int freq, int dir)
1083 {
1084 struct snd_soc_component *component = codec_dai->component;
1085 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1086 int i;
1087
1088 dev_dbg(component->dev, "## %s: clk_id = %d, freq = %d, dir = %d\n",
1089 __func__, clk_id, freq, dir);
1090
1091 for (i = 1; i < 8; i++)
1092 if (freq / i <= 20000000)
1093 break;
1094 if (freq/i > 20000000) {
1095 dev_err(aic31xx->dev, "%s: Too high mclk frequency %u\n",
1096 __func__, freq);
1097 return -EINVAL;
1098 }
1099 aic31xx->p_div = i;
1100
1101 for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++)
1102 if (aic31xx_divs[i].mclk_p == freq / aic31xx->p_div)
1103 break;
1104 if (i == ARRAY_SIZE(aic31xx_divs)) {
1105 dev_err(aic31xx->dev, "%s: Unsupported frequency %d\n",
1106 __func__, freq);
1107 return -EINVAL;
1108 }
1109
1110 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */
1111 snd_soc_component_update_bits(component, AIC31XX_CLKMUX, AIC31XX_PLL_CLKIN_MASK,
1112 clk_id << AIC31XX_PLL_CLKIN_SHIFT);
1113
1114 aic31xx->sysclk = freq;
1115
1116 return 0;
1117 }
1118
1119 static int aic31xx_regulator_event(struct notifier_block *nb,
1120 unsigned long event, void *data)
1121 {
1122 struct aic31xx_disable_nb *disable_nb =
1123 container_of(nb, struct aic31xx_disable_nb, nb);
1124 struct aic31xx_priv *aic31xx = disable_nb->aic31xx;
1125
1126 if (event & REGULATOR_EVENT_DISABLE) {
1127 /*
1128 * Put codec to reset and as at least one of the
1129 * supplies was disabled.
1130 */
1131 if (aic31xx->gpio_reset)
1132 gpiod_set_value(aic31xx->gpio_reset, 1);
1133
1134 regcache_mark_dirty(aic31xx->regmap);
1135 dev_dbg(aic31xx->dev, "## %s: DISABLE received\n", __func__);
1136 }
1137
1138 return 0;
1139 }
1140
1141 static int aic31xx_reset(struct aic31xx_priv *aic31xx)
1142 {
1143 int ret = 0;
1144
1145 if (aic31xx->gpio_reset) {
1146 gpiod_set_value(aic31xx->gpio_reset, 1);
1147 ndelay(10); /* At least 10ns */
1148 gpiod_set_value(aic31xx->gpio_reset, 0);
1149 } else {
1150 ret = regmap_write(aic31xx->regmap, AIC31XX_RESET, 1);
1151 }
1152 mdelay(1); /* At least 1ms */
1153
1154 return ret;
1155 }
1156
1157 static void aic31xx_clk_on(struct snd_soc_component *component)
1158 {
1159 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1160 u8 mask = AIC31XX_PM_MASK;
1161 u8 on = AIC31XX_PM_MASK;
1162
1163 dev_dbg(component->dev, "codec clock -> on (rate %d)\n",
1164 aic31xx_divs[aic31xx->rate_div_line].rate);
1165 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, on);
1166 mdelay(10);
1167 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, on);
1168 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, on);
1169 if (aic31xx_divs[aic31xx->rate_div_line].nadc)
1170 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, on);
1171 if (aic31xx_divs[aic31xx->rate_div_line].madc)
1172 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, on);
1173 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, on);
1174 }
1175
1176 static void aic31xx_clk_off(struct snd_soc_component *component)
1177 {
1178 u8 mask = AIC31XX_PM_MASK;
1179 u8 off = 0;
1180
1181 dev_dbg(component->dev, "codec clock -> off\n");
1182 snd_soc_component_update_bits(component, AIC31XX_BCLKN, mask, off);
1183 snd_soc_component_update_bits(component, AIC31XX_MADC, mask, off);
1184 snd_soc_component_update_bits(component, AIC31XX_NADC, mask, off);
1185 snd_soc_component_update_bits(component, AIC31XX_MDAC, mask, off);
1186 snd_soc_component_update_bits(component, AIC31XX_NDAC, mask, off);
1187 snd_soc_component_update_bits(component, AIC31XX_PLLPR, mask, off);
1188 }
1189
1190 static int aic31xx_power_on(struct snd_soc_component *component)
1191 {
1192 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1193 int ret;
1194
1195 ret = regulator_bulk_enable(ARRAY_SIZE(aic31xx->supplies),
1196 aic31xx->supplies);
1197 if (ret)
1198 return ret;
1199
1200 regcache_cache_only(aic31xx->regmap, false);
1201
1202 /* Reset device registers for a consistent power-on like state */
1203 ret = aic31xx_reset(aic31xx);
1204 if (ret < 0)
1205 dev_err(aic31xx->dev, "Could not reset device: %d\n", ret);
1206
1207 ret = regcache_sync(aic31xx->regmap);
1208 if (ret) {
1209 dev_err(component->dev,
1210 "Failed to restore cache: %d\n", ret);
1211 regcache_cache_only(aic31xx->regmap, true);
1212 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1213 aic31xx->supplies);
1214 return ret;
1215 }
1216
1217 return 0;
1218 }
1219
1220 static void aic31xx_power_off(struct snd_soc_component *component)
1221 {
1222 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1223
1224 regcache_cache_only(aic31xx->regmap, true);
1225 regulator_bulk_disable(ARRAY_SIZE(aic31xx->supplies),
1226 aic31xx->supplies);
1227 }
1228
1229 static int aic31xx_set_bias_level(struct snd_soc_component *component,
1230 enum snd_soc_bias_level level)
1231 {
1232 dev_dbg(component->dev, "## %s: %d -> %d\n", __func__,
1233 snd_soc_component_get_bias_level(component), level);
1234
1235 switch (level) {
1236 case SND_SOC_BIAS_ON:
1237 break;
1238 case SND_SOC_BIAS_PREPARE:
1239 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1240 aic31xx_clk_on(component);
1241 break;
1242 case SND_SOC_BIAS_STANDBY:
1243 switch (snd_soc_component_get_bias_level(component)) {
1244 case SND_SOC_BIAS_OFF:
1245 aic31xx_power_on(component);
1246 break;
1247 case SND_SOC_BIAS_PREPARE:
1248 aic31xx_clk_off(component);
1249 break;
1250 default:
1251 BUG();
1252 }
1253 break;
1254 case SND_SOC_BIAS_OFF:
1255 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_STANDBY)
1256 aic31xx_power_off(component);
1257 break;
1258 }
1259
1260 return 0;
1261 }
1262
1263 static int aic31xx_codec_probe(struct snd_soc_component *component)
1264 {
1265 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1266 int i, ret;
1267
1268 dev_dbg(aic31xx->dev, "## %s\n", __func__);
1269
1270 aic31xx->component = component;
1271
1272 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++) {
1273 aic31xx->disable_nb[i].nb.notifier_call =
1274 aic31xx_regulator_event;
1275 aic31xx->disable_nb[i].aic31xx = aic31xx;
1276 ret = regulator_register_notifier(aic31xx->supplies[i].consumer,
1277 &aic31xx->disable_nb[i].nb);
1278 if (ret) {
1279 dev_err(component->dev,
1280 "Failed to request regulator notifier: %d\n",
1281 ret);
1282 return ret;
1283 }
1284 }
1285
1286 regcache_cache_only(aic31xx->regmap, true);
1287 regcache_mark_dirty(aic31xx->regmap);
1288
1289 ret = aic31xx_add_controls(component);
1290 if (ret)
1291 return ret;
1292
1293 ret = aic31xx_add_widgets(component);
1294 if (ret)
1295 return ret;
1296
1297 return 0;
1298 }
1299
1300 static void aic31xx_codec_remove(struct snd_soc_component *component)
1301 {
1302 struct aic31xx_priv *aic31xx = snd_soc_component_get_drvdata(component);
1303 int i;
1304
1305 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1306 regulator_unregister_notifier(aic31xx->supplies[i].consumer,
1307 &aic31xx->disable_nb[i].nb);
1308 }
1309
1310 static const struct snd_soc_component_driver soc_codec_driver_aic31xx = {
1311 .probe = aic31xx_codec_probe,
1312 .remove = aic31xx_codec_remove,
1313 .set_bias_level = aic31xx_set_bias_level,
1314 .controls = common31xx_snd_controls,
1315 .num_controls = ARRAY_SIZE(common31xx_snd_controls),
1316 .dapm_widgets = common31xx_dapm_widgets,
1317 .num_dapm_widgets = ARRAY_SIZE(common31xx_dapm_widgets),
1318 .dapm_routes = common31xx_audio_map,
1319 .num_dapm_routes = ARRAY_SIZE(common31xx_audio_map),
1320 .suspend_bias_off = 1,
1321 .idle_bias_on = 1,
1322 .use_pmdown_time = 1,
1323 .endianness = 1,
1324 .non_legacy_dai_naming = 1,
1325 };
1326
1327 static const struct snd_soc_dai_ops aic31xx_dai_ops = {
1328 .hw_params = aic31xx_hw_params,
1329 .set_sysclk = aic31xx_set_dai_sysclk,
1330 .set_fmt = aic31xx_set_dai_fmt,
1331 .digital_mute = aic31xx_dac_mute,
1332 };
1333
1334 static struct snd_soc_dai_driver dac31xx_dai_driver[] = {
1335 {
1336 .name = "tlv320dac31xx-hifi",
1337 .playback = {
1338 .stream_name = "Playback",
1339 .channels_min = 2,
1340 .channels_max = 2,
1341 .rates = AIC31XX_RATES,
1342 .formats = AIC31XX_FORMATS,
1343 },
1344 .ops = &aic31xx_dai_ops,
1345 .symmetric_rates = 1,
1346 }
1347 };
1348
1349 static struct snd_soc_dai_driver aic31xx_dai_driver[] = {
1350 {
1351 .name = "tlv320aic31xx-hifi",
1352 .playback = {
1353 .stream_name = "Playback",
1354 .channels_min = 2,
1355 .channels_max = 2,
1356 .rates = AIC31XX_RATES,
1357 .formats = AIC31XX_FORMATS,
1358 },
1359 .capture = {
1360 .stream_name = "Capture",
1361 .channels_min = 2,
1362 .channels_max = 2,
1363 .rates = AIC31XX_RATES,
1364 .formats = AIC31XX_FORMATS,
1365 },
1366 .ops = &aic31xx_dai_ops,
1367 .symmetric_rates = 1,
1368 }
1369 };
1370
1371 #if defined(CONFIG_OF)
1372 static const struct of_device_id tlv320aic31xx_of_match[] = {
1373 { .compatible = "ti,tlv320aic310x" },
1374 { .compatible = "ti,tlv320aic311x" },
1375 { .compatible = "ti,tlv320aic3100" },
1376 { .compatible = "ti,tlv320aic3110" },
1377 { .compatible = "ti,tlv320aic3120" },
1378 { .compatible = "ti,tlv320aic3111" },
1379 { .compatible = "ti,tlv320dac3100" },
1380 { .compatible = "ti,tlv320dac3101" },
1381 {},
1382 };
1383 MODULE_DEVICE_TABLE(of, tlv320aic31xx_of_match);
1384 #endif /* CONFIG_OF */
1385
1386 #ifdef CONFIG_ACPI
1387 static const struct acpi_device_id aic31xx_acpi_match[] = {
1388 { "10TI3100", 0 },
1389 { }
1390 };
1391 MODULE_DEVICE_TABLE(acpi, aic31xx_acpi_match);
1392 #endif
1393
1394 static int aic31xx_i2c_probe(struct i2c_client *i2c,
1395 const struct i2c_device_id *id)
1396 {
1397 struct aic31xx_priv *aic31xx;
1398 unsigned int micbias_value = MICBIAS_2_0V;
1399 int i, ret;
1400
1401 dev_dbg(&i2c->dev, "## %s: %s codec_type = %d\n", __func__,
1402 id->name, (int)id->driver_data);
1403
1404 aic31xx = devm_kzalloc(&i2c->dev, sizeof(*aic31xx), GFP_KERNEL);
1405 if (!aic31xx)
1406 return -ENOMEM;
1407
1408 aic31xx->regmap = devm_regmap_init_i2c(i2c, &aic31xx_i2c_regmap);
1409 if (IS_ERR(aic31xx->regmap)) {
1410 ret = PTR_ERR(aic31xx->regmap);
1411 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1412 ret);
1413 return ret;
1414 }
1415 aic31xx->dev = &i2c->dev;
1416
1417 aic31xx->codec_type = id->driver_data;
1418
1419 dev_set_drvdata(aic31xx->dev, aic31xx);
1420
1421 fwnode_property_read_u32(aic31xx->dev->fwnode, "ai31xx-micbias-vg",
1422 &micbias_value);
1423 switch (micbias_value) {
1424 case MICBIAS_2_0V:
1425 case MICBIAS_2_5V:
1426 case MICBIAS_AVDDV:
1427 aic31xx->micbias_vg = micbias_value;
1428 break;
1429 default:
1430 dev_err(aic31xx->dev, "Bad ai31xx-micbias-vg value %d\n",
1431 micbias_value);
1432 aic31xx->micbias_vg = MICBIAS_2_0V;
1433 }
1434
1435 if (dev_get_platdata(aic31xx->dev)) {
1436 memcpy(&aic31xx->pdata, dev_get_platdata(aic31xx->dev), sizeof(aic31xx->pdata));
1437 aic31xx->codec_type = aic31xx->pdata.codec_type;
1438 aic31xx->micbias_vg = aic31xx->pdata.micbias_vg;
1439 }
1440
1441 aic31xx->gpio_reset = devm_gpiod_get_optional(aic31xx->dev, "reset",
1442 GPIOD_OUT_LOW);
1443 if (IS_ERR(aic31xx->gpio_reset)) {
1444 dev_err(aic31xx->dev, "not able to acquire gpio\n");
1445 return PTR_ERR(aic31xx->gpio_reset);
1446 }
1447
1448 for (i = 0; i < ARRAY_SIZE(aic31xx->supplies); i++)
1449 aic31xx->supplies[i].supply = aic31xx_supply_names[i];
1450
1451 ret = devm_regulator_bulk_get(aic31xx->dev,
1452 ARRAY_SIZE(aic31xx->supplies),
1453 aic31xx->supplies);
1454 if (ret) {
1455 dev_err(aic31xx->dev, "Failed to request supplies: %d\n", ret);
1456 return ret;
1457 }
1458
1459 if (aic31xx->codec_type & DAC31XX_BIT)
1460 return devm_snd_soc_register_component(&i2c->dev,
1461 &soc_codec_driver_aic31xx,
1462 dac31xx_dai_driver,
1463 ARRAY_SIZE(dac31xx_dai_driver));
1464 else
1465 return devm_snd_soc_register_component(&i2c->dev,
1466 &soc_codec_driver_aic31xx,
1467 aic31xx_dai_driver,
1468 ARRAY_SIZE(aic31xx_dai_driver));
1469 }
1470
1471 static const struct i2c_device_id aic31xx_i2c_id[] = {
1472 { "tlv320aic310x", AIC3100 },
1473 { "tlv320aic311x", AIC3110 },
1474 { "tlv320aic3100", AIC3100 },
1475 { "tlv320aic3110", AIC3110 },
1476 { "tlv320aic3120", AIC3120 },
1477 { "tlv320aic3111", AIC3111 },
1478 { "tlv320dac3100", DAC3100 },
1479 { "tlv320dac3101", DAC3101 },
1480 { }
1481 };
1482 MODULE_DEVICE_TABLE(i2c, aic31xx_i2c_id);
1483
1484 static struct i2c_driver aic31xx_i2c_driver = {
1485 .driver = {
1486 .name = "tlv320aic31xx-codec",
1487 .of_match_table = of_match_ptr(tlv320aic31xx_of_match),
1488 .acpi_match_table = ACPI_PTR(aic31xx_acpi_match),
1489 },
1490 .probe = aic31xx_i2c_probe,
1491 .id_table = aic31xx_i2c_id,
1492 };
1493 module_i2c_driver(aic31xx_i2c_driver);
1494
1495 MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
1496 MODULE_DESCRIPTION("ASoC TLV320AIC31xx CODEC Driver");
1497 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support