1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 1999-2000 Hewlett-Packard Co
4 * Copyright (C) 1999-2000 David Mosberger-Tang <davidm@hpl.hp.com>
6 * 64-bit integer division.
8 * This code is based on the application note entitled "Divide, Square Root
9 * and Remainder Algorithms for the IA-64 Architecture". This document
10 * is available as Intel document number 248725-002 or via the web at
11 * http://developer.intel.com/software/opensource/numerics/
13 * For more details on the theory behind these algorithms, see "IA-64
14 * and Elementary Functions" by Peter Markstein; HP Professional Books
15 * (http://www.goodreads.com/book/show/2019887.Ia_64_and_Elementary_Functions)
18 #include <asm/asmmacro.h>
19 #include <asm/export.h>
29 # define INT_TO_FP(a,b) fcvt.xuf.s1 a=b
30 # define FP_TO_INT(a,b) fcvt.fxu.trunc.s1 a=b
33 # define INT_TO_FP(a,b) fcvt.xf a=b
34 # define FP_TO_INT(a,b) fcvt.fx.trunc.s1 a=b
37 #define PASTE1(a,b) a##b
38 #define PASTE(a,b) PASTE1(a,b)
39 #define NAME PASTE(PASTE(__,SGN),PASTE(OP,di3))
43 // Transfer inputs to FP registers.
47 // Convert the inputs to FP, to avoid FP software-assist faults.
51 frcpa.s1 f11, p6 = f8, f9 // y0 = frcpa(b)
53 (p6) fmpy.s1 f7 = f8, f11 // q0 = a*y0
54 (p6) fnma.s1 f6 = f9, f11, f1 // e0 = -b*y0 + 1
56 (p6) fma.s1 f10 = f7, f6, f7 // q1 = q0*e0 + q0
57 (p6) fmpy.s1 f7 = f6, f6 // e1 = e0*e0
60 sub in1 = r0, in1 // in1 = -b
62 (p6) fma.s1 f10 = f10, f7, f10 // q2 = q1*e1 + q1
63 (p6) fma.s1 f6 = f11, f6, f11 // y1 = y0*e0 + y0
65 (p6) fma.s1 f6 = f6, f7, f6 // y2 = y1*e1 + y1
66 (p6) fnma.s1 f7 = f9, f10, f8 // r = -b*q2 + a
69 setf.sig f8 = in0 // f8 = a
70 setf.sig f9 = in1 // f9 = -b
72 (p6) fma.s1 f11 = f7, f6, f10 // q3 = r*y2 + q2
74 FP_TO_INT(f11, f11) // q = trunc(q3)
77 xma.l f11 = f11, f9, f8 // r = q*(-b) + a
80 getf.sig r8 = f11 // transfer result to result register