arch/mips/cavium-octeon/octeon-usb.c

   1 /*
   2  * XHCI HCD glue for Cavium Octeon III SOCs.
   3  *
   4  * Copyright (C) 2010-2017 Cavium Networks
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/device.h>
  13 #include <linux/mutex.h>
  14 #include <linux/delay.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/io.h>
  17
  18 #include <asm/octeon/octeon.h>
  19
  20 /* USB Control Register */
  21 union cvm_usbdrd_uctl_ctl {
  22         uint64_t u64;
  23         struct cvm_usbdrd_uctl_ctl_s {
  24         /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
  25         __BITFIELD_FIELD(uint64_t clear_bist:1,
  26         /* 1 = Start BIST and cleared by hardware */
  27         __BITFIELD_FIELD(uint64_t start_bist:1,
  28         /* Reference clock select for SuperSpeed and HighSpeed PLLs:
  29          *      0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
  30          *      0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
  31          *      0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
  32          *            HighSpeed PLL uses PLL_REF_CLK for reference clck
  33          *      0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
  34          *            HighSpeed PLL uses PLL_REF_CLK for reference clck
  35          */
  36         __BITFIELD_FIELD(uint64_t ref_clk_sel:2,
  37         /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */
  38         __BITFIELD_FIELD(uint64_t ssc_en:1,
  39         /* Spread-spectrum clock modulation range:
  40          *      0x0 = -4980 ppm downspread
  41          *      0x1 = -4492 ppm downspread
  42          *      0x2 = -4003 ppm downspread
  43          *      0x3 - 0x7 = Reserved
  44          */
  45         __BITFIELD_FIELD(uint64_t ssc_range:3,
  46         /* Enable non-standard oscillator frequencies:
  47          *      [55:53] = modules -1
  48          *      [52:47] = 2's complement push amount, 0 = Feature disabled
  49          */
  50         __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9,
  51         /* Reference clock multiplier for non-standard frequencies:
  52          *      0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
  53          *      0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
  54          *      0x32 =  50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1
  55          *      Other Values = Reserved
  56          */
  57         __BITFIELD_FIELD(uint64_t mpll_multiplier:7,
  58         /* Enable reference clock to prescaler for SuperSpeed functionality.
  59          * Should always be set to "1"
  60          */
  61         __BITFIELD_FIELD(uint64_t ref_ssp_en:1,
  62         /* Divide the reference clock by 2 before entering the
  63          * REF_CLK_FSEL divider:
  64          *      If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal
  65          *      If REF_CLK_SEL = 0x2 or 0x3, then:
  66          *              0x1 = DLMC_REF_CLK* is 125MHz
  67          *              0x0 = DLMC_REF_CLK* is another supported frequency
  68          */
  69         __BITFIELD_FIELD(uint64_t ref_clk_div2:1,
  70         /* Select reference clock freqnuency for both PLL blocks:
  71          *      0x27 = REF_CLK_SEL is 0x0 or 0x1
  72          *      0x07 = REF_CLK_SEL is 0x2 or 0x3
  73          */
  74         __BITFIELD_FIELD(uint64_t ref_clk_fsel:6,
  75         /* Reserved */
  76         __BITFIELD_FIELD(uint64_t reserved_31_31:1,
  77         /* Controller clock enable. */
  78         __BITFIELD_FIELD(uint64_t h_clk_en:1,
  79         /* Select bypass input to controller clock divider:
  80          *      0x0 = Use divided coprocessor clock from H_CLKDIV
  81          *      0x1 = Use clock from GPIO pins
  82          */
  83         __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1,
  84         /* Reset controller clock divider. */
  85         __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1,
  86         /* Reserved */
  87         __BITFIELD_FIELD(uint64_t reserved_27_27:1,
  88         /* Clock divider select:
  89          *      0x0 = divide by 1
  90          *      0x1 = divide by 2
  91          *      0x2 = divide by 4
  92          *      0x3 = divide by 6
  93          *      0x4 = divide by 8
  94          *      0x5 = divide by 16
  95          *      0x6 = divide by 24
  96          *      0x7 = divide by 32
  97          */
  98         __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3,
  99         /* Reserved */
 100         __BITFIELD_FIELD(uint64_t reserved_22_23:2,
 101         /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */
 102         __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1,
 103         /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */
 104         __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1,
 105         /* Reserved */
 106         __BITFIELD_FIELD(uint64_t reserved_19_19:1,
 107         /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */
 108         __BITFIELD_FIELD(uint64_t usb3_port_disable:1,
 109         /* Reserved */
 110         __BITFIELD_FIELD(uint64_t reserved_17_17:1,
 111         /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */
 112         __BITFIELD_FIELD(uint64_t usb2_port_disable:1,
 113         /* Reserved */
 114         __BITFIELD_FIELD(uint64_t reserved_15_15:1,
 115         /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */
 116         __BITFIELD_FIELD(uint64_t ss_power_en:1,
 117         /* Reserved */
 118         __BITFIELD_FIELD(uint64_t reserved_13_13:1,
 119         /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */
 120         __BITFIELD_FIELD(uint64_t hs_power_en:1,
 121         /* Reserved */
 122         __BITFIELD_FIELD(uint64_t reserved_5_11:7,
 123         /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */
 124         __BITFIELD_FIELD(uint64_t csclk_en:1,
 125         /* Controller mode: 0x0 = Host, 0x1 = Device */
 126         __BITFIELD_FIELD(uint64_t drd_mode:1,
 127         /* PHY reset */
 128         __BITFIELD_FIELD(uint64_t uphy_rst:1,
 129         /* Software reset UAHC */
 130         __BITFIELD_FIELD(uint64_t uahc_rst:1,
 131         /* Software resets UCTL */
 132         __BITFIELD_FIELD(uint64_t uctl_rst:1,
 133         ;)))))))))))))))))))))))))))))))))
 134         } s;
 135 };
 136
 137 /* UAHC Configuration Register */
 138 union cvm_usbdrd_uctl_host_cfg {
 139         uint64_t u64;
 140         struct cvm_usbdrd_uctl_host_cfg_s {
 141         /* Reserved */
 142         __BITFIELD_FIELD(uint64_t reserved_60_63:4,
 143         /* Indicates minimum value of all received BELT values */
 144         __BITFIELD_FIELD(uint64_t host_current_belt:12,
 145         /* Reserved */
 146         __BITFIELD_FIELD(uint64_t reserved_38_47:10,
 147         /* HS jitter adjustment */
 148         __BITFIELD_FIELD(uint64_t fla:6,
 149         /* Reserved */
 150         __BITFIELD_FIELD(uint64_t reserved_29_31:3,
 151         /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */
 152         __BITFIELD_FIELD(uint64_t bme:1,
 153         /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */
 154         __BITFIELD_FIELD(uint64_t oci_en:1,
 155         /* Overcurrent sene selection:
 156          *      0x0 = Overcurrent indication from off-chip is active-low
 157          *      0x1 = Overcurrent indication from off-chip is active-high
 158          */
 159         __BITFIELD_FIELD(uint64_t oci_active_high_en:1,
 160         /* Port power control enable: 0x0 = unavailable, 0x1 = available */
 161         __BITFIELD_FIELD(uint64_t ppc_en:1,
 162         /* Port power control sense selection:
 163          *      0x0 = Port power to off-chip is active-low
 164          *      0x1 = Port power to off-chip is active-high
 165          */
 166         __BITFIELD_FIELD(uint64_t ppc_active_high_en:1,
 167         /* Reserved */
 168         __BITFIELD_FIELD(uint64_t reserved_0_23:24,
 169         ;)))))))))))
 170         } s;
 171 };
 172
 173 /* UCTL Shim Features Register */
 174 union cvm_usbdrd_uctl_shim_cfg {
 175         uint64_t u64;
 176         struct cvm_usbdrd_uctl_shim_cfg_s {
 177         /* Out-of-bound UAHC register access: 0 = read, 1 = write */
 178         __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1,
 179         /* Reserved */
 180         __BITFIELD_FIELD(uint64_t reserved_60_62:3,
 181         /* SRCID error log for out-of-bound UAHC register access:
 182          *      [59:58] = chipID
 183          *      [57] = Request source: 0 = core, 1 = NCB-device
 184          *      [56:51] = Core/NCB-device number, [56] always 0 for NCB devices
 185          *      [50:48] = SubID
 186          */
 187         __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12,
 188         /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */
 189         __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1,
 190         /* Reserved */
 191         __BITFIELD_FIELD(uint64_t reserved_44_46:3,
 192         /* Encoded error type for bad UAHC DMA */
 193         __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4,
 194         /* Reserved */
 195         __BITFIELD_FIELD(uint64_t reserved_13_39:27,
 196         /* Select the IOI read command used by DMA accesses */
 197         __BITFIELD_FIELD(uint64_t dma_read_cmd:1,
 198         /* Reserved */
 199         __BITFIELD_FIELD(uint64_t reserved_10_11:2,
 200         /* Select endian format for DMA accesses to the L2c:
 201          *      0x0 = Little endian
 202          *`     0x1 = Big endian
 203          *      0x2 = Reserved
 204          *      0x3 = Reserved
 205          */
 206         __BITFIELD_FIELD(uint64_t dma_endian_mode:2,
 207         /* Reserved */
 208         __BITFIELD_FIELD(uint64_t reserved_2_7:6,
 209         /* Select endian format for IOI CSR access to UAHC:
 210          *      0x0 = Little endian
 211          *`     0x1 = Big endian
 212          *      0x2 = Reserved
 213          *      0x3 = Reserved
 214          */
 215         __BITFIELD_FIELD(uint64_t csr_endian_mode:2,
 216         ;))))))))))))
 217         } s;
 218 };
 219
 220 #define OCTEON_H_CLKDIV_SEL             8
 221 #define OCTEON_MIN_H_CLK_RATE           150000000
 222 #define OCTEON_MAX_H_CLK_RATE           300000000
 223
 224 static DEFINE_MUTEX(dwc3_octeon_clocks_mutex);
 225 static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32};
 226
 227
 228 static int dwc3_octeon_config_power(struct device *dev, u64 base)
 229 {
 230 #define UCTL_HOST_CFG   0xe0
 231         union cvm_usbdrd_uctl_host_cfg uctl_host_cfg;
 232         union cvmx_gpio_bit_cfgx gpio_bit;
 233         uint32_t gpio_pwr[3];
 234         int gpio, len, power_active_low;
 235         struct device_node *node = dev->of_node;
 236         int index = (base >> 24) & 1;
 237
 238         if (of_find_property(node, "power", &len) != NULL) {
 239                 if (len == 12) {
 240                         of_property_read_u32_array(node, "power", gpio_pwr, 3);
 241                         power_active_low = gpio_pwr[2] & 0x01;
 242                         gpio = gpio_pwr[1];
 243                 } else if (len == 8) {
 244                         of_property_read_u32_array(node, "power", gpio_pwr, 2);
 245                         power_active_low = 0;
 246                         gpio = gpio_pwr[1];
 247                 } else {
 248                         dev_err(dev, "dwc3 controller clock init failure.\n");
 249                         return -EINVAL;
 250                 }
 251                 if ((OCTEON_IS_MODEL(OCTEON_CN73XX) ||
 252                     OCTEON_IS_MODEL(OCTEON_CNF75XX))
 253                     && gpio <= 31) {
 254                         gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
 255                         gpio_bit.s.tx_oe = 1;
 256                         gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15);
 257                         cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
 258                 } else if (gpio <= 15) {
 259                         gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio));
 260                         gpio_bit.s.tx_oe = 1;
 261                         gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
 262                         cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64);
 263                 } else {
 264                         gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio));
 265                         gpio_bit.s.tx_oe = 1;
 266                         gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19);
 267                         cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64);
 268                 }
 269
 270                 /* Enable XHCI power control and set if active high or low. */
 271                 uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
 272                 uctl_host_cfg.s.ppc_en = 1;
 273                 uctl_host_cfg.s.ppc_active_high_en = !power_active_low;
 274                 cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
 275         } else {
 276                 /* Disable XHCI power control and set if active high. */
 277                 uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG);
 278                 uctl_host_cfg.s.ppc_en = 0;
 279                 uctl_host_cfg.s.ppc_active_high_en = 0;
 280                 cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64);
 281                 dev_warn(dev, "dwc3 controller clock init failure.\n");
 282         }
 283         return 0;
 284 }
 285
 286 static int dwc3_octeon_clocks_start(struct device *dev, u64 base)
 287 {
 288         union cvm_usbdrd_uctl_ctl uctl_ctl;
 289         int ref_clk_sel = 2;
 290         u64 div;
 291         u32 clock_rate;
 292         int mpll_mul;
 293         int i;
 294         u64 h_clk_rate;
 295         u64 uctl_ctl_reg = base;
 296
 297         if (dev->of_node) {
 298                 const char *ss_clock_type;
 299                 const char *hs_clock_type;
 300
 301                 i = of_property_read_u32(dev->of_node,
 302                                          "refclk-frequency", &clock_rate);
 303                 if (i) {
 304                         pr_err("No UCTL \"refclk-frequency\"\n");
 305                         return -EINVAL;
 306                 }
 307                 i = of_property_read_string(dev->of_node,
 308                                             "refclk-type-ss", &ss_clock_type);
 309                 if (i) {
 310                         pr_err("No UCTL \"refclk-type-ss\"\n");
 311                         return -EINVAL;
 312                 }
 313                 i = of_property_read_string(dev->of_node,
 314                                             "refclk-type-hs", &hs_clock_type);
 315                 if (i) {
 316                         pr_err("No UCTL \"refclk-type-hs\"\n");
 317                         return -EINVAL;
 318                 }
 319                 if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) {
 320                         if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0)
 321                                 ref_clk_sel = 0;
 322                         else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
 323                                 ref_clk_sel = 2;
 324                         else
 325                                 pr_err("Invalid HS clock type %s, using  pll_ref_clk instead\n",
 326                                        hs_clock_type);
 327                 } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) {
 328                         if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0)
 329                                 ref_clk_sel = 1;
 330                         else if (strcmp(hs_clock_type, "pll_ref_clk") == 0)
 331                                 ref_clk_sel = 3;
 332                         else {
 333                                 pr_err("Invalid HS clock type %s, using  pll_ref_clk instead\n",
 334                                        hs_clock_type);
 335                                 ref_clk_sel = 3;
 336                         }
 337                 } else
 338                         pr_err("Invalid SS clock type %s, using  dlmc_ref_clk0 instead\n",
 339                                ss_clock_type);
 340
 341                 if ((ref_clk_sel == 0 || ref_clk_sel == 1) &&
 342                                   (clock_rate != 100000000))
 343                         pr_err("Invalid UCTL clock rate of %u, using 100000000 instead\n",
 344                                clock_rate);
 345
 346         } else {
 347                 pr_err("No USB UCTL device node\n");
 348                 return -EINVAL;
 349         }
 350
 351         /*
 352          * Step 1: Wait for all voltages to be stable...that surely
 353          *         happened before starting the kernel. SKIP
 354          */
 355
 356         /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */
 357
 358         /* Step 3: Assert all resets. */
 359         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 360         uctl_ctl.s.uphy_rst = 1;
 361         uctl_ctl.s.uahc_rst = 1;
 362         uctl_ctl.s.uctl_rst = 1;
 363         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 364
 365         /* Step 4a: Reset the clock dividers. */
 366         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 367         uctl_ctl.s.h_clkdiv_rst = 1;
 368         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 369
 370         /* Step 4b: Select controller clock frequency. */
 371         for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) {
 372                 h_clk_rate = octeon_get_io_clock_rate() / clk_div[div];
 373                 if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE &&
 374                                  h_clk_rate >= OCTEON_MIN_H_CLK_RATE)
 375                         break;
 376         }
 377         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 378         uctl_ctl.s.h_clkdiv_sel = div;
 379         uctl_ctl.s.h_clk_en = 1;
 380         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 381         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 382         if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) {
 383                 dev_err(dev, "dwc3 controller clock init failure.\n");
 384                         return -EINVAL;
 385         }
 386
 387         /* Step 4c: Deassert the controller clock divider reset. */
 388         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 389         uctl_ctl.s.h_clkdiv_rst = 0;
 390         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 391
 392         /* Step 5a: Reference clock configuration. */
 393         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 394         uctl_ctl.s.ref_clk_sel = ref_clk_sel;
 395         uctl_ctl.s.ref_clk_fsel = 0x07;
 396         uctl_ctl.s.ref_clk_div2 = 0;
 397         switch (clock_rate) {
 398         default:
 399                 dev_err(dev, "Invalid ref_clk %u, using 100000000 instead\n",
 400                         clock_rate);
 401                 fallthrough;
 402         case 100000000:
 403                 mpll_mul = 0x19;
 404                 if (ref_clk_sel < 2)
 405                         uctl_ctl.s.ref_clk_fsel = 0x27;
 406                 break;
 407         case 50000000:
 408                 mpll_mul = 0x32;
 409                 break;
 410         case 125000000:
 411                 mpll_mul = 0x28;
 412                 break;
 413         }
 414         uctl_ctl.s.mpll_multiplier = mpll_mul;
 415
 416         /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */
 417         uctl_ctl.s.ssc_en = 1;
 418
 419         /* Step 5c: Enable SuperSpeed. */
 420         uctl_ctl.s.ref_ssp_en = 1;
 421
 422         /* Step 5d: Cofngiure PHYs. SKIP */
 423
 424         /* Step 6a & 6b: Power up PHYs. */
 425         uctl_ctl.s.hs_power_en = 1;
 426         uctl_ctl.s.ss_power_en = 1;
 427         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 428
 429         /* Step 7: Wait 10 controller-clock cycles to take effect. */
 430         udelay(10);
 431
 432         /* Step 8a: Deassert UCTL reset signal. */
 433         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 434         uctl_ctl.s.uctl_rst = 0;
 435         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 436
 437         /* Step 8b: Wait 10 controller-clock cycles. */
 438         udelay(10);
 439
 440         /* Steo 8c: Setup power-power control. */
 441         if (dwc3_octeon_config_power(dev, base)) {
 442                 dev_err(dev, "Error configuring power.\n");
 443                 return -EINVAL;
 444         }
 445
 446         /* Step 8d: Deassert UAHC reset signal. */
 447         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 448         uctl_ctl.s.uahc_rst = 0;
 449         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 450
 451         /* Step 8e: Wait 10 controller-clock cycles. */
 452         udelay(10);
 453
 454         /* Step 9: Enable conditional coprocessor clock of UCTL. */
 455         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 456         uctl_ctl.s.csclk_en = 1;
 457         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 458
 459         /*Step 10: Set for host mode only. */
 460         uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg);
 461         uctl_ctl.s.drd_mode = 0;
 462         cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64);
 463
 464         return 0;
 465 }
 466
 467 static void __init dwc3_octeon_set_endian_mode(u64 base)
 468 {
 469 #define UCTL_SHIM_CFG   0xe8
 470         union cvm_usbdrd_uctl_shim_cfg shim_cfg;
 471
 472         shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG);
 473 #ifdef __BIG_ENDIAN
 474         shim_cfg.s.dma_endian_mode = 1;
 475         shim_cfg.s.csr_endian_mode = 1;
 476 #else
 477         shim_cfg.s.dma_endian_mode = 0;
 478         shim_cfg.s.csr_endian_mode = 0;
 479 #endif
 480         cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64);
 481 }
 482
 483 #define CVMX_USBDRDX_UCTL_CTL(index)                            \
 484                 (CVMX_ADD_IO_SEG(0x0001180068000000ull) +       \
 485                 ((index & 1) * 0x1000000ull))
 486 static void __init dwc3_octeon_phy_reset(u64 base)
 487 {
 488         union cvm_usbdrd_uctl_ctl uctl_ctl;
 489         int index = (base >> 24) & 1;
 490
 491         uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index));
 492         uctl_ctl.s.uphy_rst = 0;
 493         cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64);
 494 }
 495
 496 static int __init dwc3_octeon_device_init(void)
 497 {
 498         const char compat_node_name[] = "cavium,octeon-7130-usb-uctl";
 499         struct platform_device *pdev;
 500         struct device_node *node;
 501         struct resource *res;
 502         void __iomem *base;
 503
 504         /*
 505          * There should only be three universal controllers, "uctl"
 506          * in the device tree. Two USB and a SATA, which we ignore.
 507          */
 508         node = NULL;
 509         do {
 510                 node = of_find_node_by_name(node, "uctl");
 511                 if (!node)
 512                         return -ENODEV;
 513
 514                 if (of_device_is_compatible(node, compat_node_name)) {
 515                         pdev = of_find_device_by_node(node);
 516                         if (!pdev)
 517                                 return -ENODEV;
 518
 519                         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 520                         if (res == NULL) {
 521                                 dev_err(&pdev->dev, "No memory resources\n");
 522                                 return -ENXIO;
 523                         }
 524
 525                         /*
 526                          * The code below maps in the registers necessary for
 527                          * setting up the clocks and reseting PHYs. We must
 528                          * release the resources so the dwc3 subsystem doesn't
 529                          * know the difference.
 530                          */
 531                         base = devm_ioremap_resource(&pdev->dev, res);
 532                         if (IS_ERR(base))
 533                                 return PTR_ERR(base);
 534
 535                         mutex_lock(&dwc3_octeon_clocks_mutex);
 536                         dwc3_octeon_clocks_start(&pdev->dev, (u64)base);
 537                         dwc3_octeon_set_endian_mode((u64)base);
 538                         dwc3_octeon_phy_reset((u64)base);
 539                         dev_info(&pdev->dev, "clocks initialized.\n");
 540                         mutex_unlock(&dwc3_octeon_clocks_mutex);
 541                         devm_iounmap(&pdev->dev, base);
 542                         devm_release_mem_region(&pdev->dev, res->start,
 543                                                 resource_size(res));
 544                 }
 545         } while (node != NULL);
 546
 547         return 0;
 548 }
 549 device_initcall(dwc3_octeon_device_init);
 550
 551 MODULE_AUTHOR("David Daney <david.daney@cavium.com>");
 552 MODULE_LICENSE("GPL");
 553 MODULE_DESCRIPTION("USB driver for OCTEON III SoC");