Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt

   1 ARM Mali Utgard GPU
   2 ===================
   3
   4 Required properties:
   5   - compatible
   6     * Must be one of the following:
   7       + "arm,mali-300"
   8       + "arm,mali-400"
   9       + "arm,mali-450"
  10     * And, optionally, one of the vendor specific compatible:
  11       + allwinner,sun4i-a10-mali
  12       + allwinner,sun7i-a20-mali
  13       + allwinner,sun8i-h3-mali
  14       + allwinner,sun50i-h5-mali
  15       + amlogic,meson-gxbb-mali
  16       + amlogic,meson-gxl-mali
  17       + rockchip,rk3036-mali
  18       + rockchip,rk3066-mali
  19       + rockchip,rk3188-mali
  20       + rockchip,rk3228-mali
  21       + rockchip,rk3328-mali
  22       + stericsson,db8500-mali
  23
  24   - reg: Physical base address and length of the GPU registers
  25
  26   - interrupts: an entry for each entry in interrupt-names.
  27     See ../interrupt-controller/interrupts.txt for details.
  28
  29   - interrupt-names:
  30     * ppX: Pixel Processor X interrupt (X from 0 to 7)
  31     * ppmmuX: Pixel Processor X MMU interrupt (X from 0 to 7)
  32     * pp: Pixel Processor broadcast interrupt (mali-450 only)
  33     * gp: Geometry Processor interrupt
  34     * gpmmu: Geometry Processor MMU interrupt
  35
  36   - clocks: an entry for each entry in clock-names
  37   - clock-names:
  38     * bus: bus clock for the GPU
  39     * core: clock driving the GPU itself
  40
  41 Optional properties:
  42   - interrupt-names and interrupts:
  43     * pmu: Power Management Unit interrupt, if implemented in hardware
  44
  45   - memory-region:
  46     Memory region to allocate from, as defined in
  47     Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
  48
  49   - mali-supply:
  50     Phandle to regulator for the Mali device, as defined in
  51     Documentation/devicetree/bindings/regulator/regulator.txt for details.
  52
  53   - operating-points-v2:
  54     Operating Points for the GPU, as defined in
  55     Documentation/devicetree/bindings/opp/opp.txt
  56
  57   - power-domains:
  58     A power domain consumer specifier as defined in
  59     Documentation/devicetree/bindings/power/power_domain.txt
  60
  61 Vendor-specific bindings
  62 ------------------------
  63
  64 The Mali GPU is integrated very differently from one SoC to
  65 another. In order to accomodate those differences, you have the option
  66 to specify one more vendor-specific compatible, among:
  67
  68   - allwinner,sun4i-a10-mali
  69     Required properties:
  70       * resets: phandle to the reset line for the GPU
  71
  72   - allwinner,sun7i-a20-mali
  73     Required properties:
  74       * resets: phandle to the reset line for the GPU
  75
  76   - allwinner,sun50i-h5-mali
  77     Required properties:
  78       * resets: phandle to the reset line for the GPU
  79
  80   - Rockchip variants:
  81     Required properties:
  82       * resets: phandle to the reset line for the GPU
  83
  84   - stericsson,db8500-mali
  85     Required properties:
  86       * interrupt-names and interrupts:
  87         + combined: combined interrupt of all of the above lines
  88
  89 Example:
  90
  91 mali: gpu@1c40000 {
  92         compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
  93         reg = <0x01c40000 0x10000>;
  94         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
  95                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
  96                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
  97                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
  98                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
  99                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
 100                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 101         interrupt-names = "gp",
 102                           "gpmmu",
 103                           "pp0",
 104                           "ppmmu0",
 105                           "pp1",
 106                           "ppmmu1",
 107                           "pmu";
 108         clocks = <&ccu CLK_BUS_GPU>, <&ccu CLK_GPU>;
 109         clock-names = "bus", "core";
 110         resets = <&ccu RST_BUS_GPU>;
 111 };
 112