| blob | 964f682a2b7b0b8da41248665d09980a1808983e |
1 config ARM64
2 def_bool y
3 select ACPI_CCA_REQUIRED if ACPI
4 select ACPI_GENERIC_GSI if ACPI
5 select ACPI_GTDT if ACPI
6 select ACPI_IORT if ACPI
7 select ACPI_REDUCED_HARDWARE_ONLY if ACPI
8 select ACPI_MCFG if ACPI
9 select ACPI_SPCR_TABLE if ACPI
10 select ACPI_PPTT if ACPI
11 select ARCH_CLOCKSOURCE_DATA
12 select ARCH_HAS_DEBUG_VIRTUAL
13 select ARCH_HAS_DEVMEM_IS_ALLOWED
14 select ARCH_HAS_DMA_COHERENT_TO_PFN
15 select ARCH_HAS_DMA_MMAP_PGPROT
16 select ARCH_HAS_ACPI_TABLE_UPGRADE if ACPI
17 select ARCH_HAS_ELF_RANDOMIZE
18 select ARCH_HAS_FAST_MULTIPLIER
19 select ARCH_HAS_FORTIFY_SOURCE
20 select ARCH_HAS_GCOV_PROFILE_ALL
21 select ARCH_HAS_GIGANTIC_PAGE if (MEMORY_ISOLATION && COMPACTION) || CMA
22 select ARCH_HAS_KCOV
23 select ARCH_HAS_MEMBARRIER_SYNC_CORE
24 select ARCH_HAS_PTE_SPECIAL
25 select ARCH_HAS_SET_MEMORY
26 select ARCH_HAS_SG_CHAIN
27 select ARCH_HAS_STRICT_KERNEL_RWX
28 select ARCH_HAS_STRICT_MODULE_RWX
29 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
30 select ARCH_HAS_SYNC_DMA_FOR_CPU
31 select ARCH_HAS_SYSCALL_WRAPPER
32 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
33 select ARCH_HAVE_NMI_SAFE_CMPXCHG
34 select ARCH_INLINE_READ_LOCK if !PREEMPT
35 select ARCH_INLINE_READ_LOCK_BH if !PREEMPT
36 select ARCH_INLINE_READ_LOCK_IRQ if !PREEMPT
37 select ARCH_INLINE_READ_LOCK_IRQSAVE if !PREEMPT
38 select ARCH_INLINE_READ_UNLOCK if !PREEMPT
39 select ARCH_INLINE_READ_UNLOCK_BH if !PREEMPT
40 select ARCH_INLINE_READ_UNLOCK_IRQ if !PREEMPT
41 select ARCH_INLINE_READ_UNLOCK_IRQRESTORE if !PREEMPT
42 select ARCH_INLINE_WRITE_LOCK if !PREEMPT
43 select ARCH_INLINE_WRITE_LOCK_BH if !PREEMPT
44 select ARCH_INLINE_WRITE_LOCK_IRQ if !PREEMPT
45 select ARCH_INLINE_WRITE_LOCK_IRQSAVE if !PREEMPT
46 select ARCH_INLINE_WRITE_UNLOCK if !PREEMPT
47 select ARCH_INLINE_WRITE_UNLOCK_BH if !PREEMPT
48 select ARCH_INLINE_WRITE_UNLOCK_IRQ if !PREEMPT
49 select ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE if !PREEMPT
50 select ARCH_INLINE_SPIN_TRYLOCK if !PREEMPT
51 select ARCH_INLINE_SPIN_TRYLOCK_BH if !PREEMPT
52 select ARCH_INLINE_SPIN_LOCK if !PREEMPT
53 select ARCH_INLINE_SPIN_LOCK_BH if !PREEMPT
54 select ARCH_INLINE_SPIN_LOCK_IRQ if !PREEMPT
55 select ARCH_INLINE_SPIN_LOCK_IRQSAVE if !PREEMPT
56 select ARCH_INLINE_SPIN_UNLOCK if !PREEMPT
57 select ARCH_INLINE_SPIN_UNLOCK_BH if !PREEMPT
58 select ARCH_INLINE_SPIN_UNLOCK_IRQ if !PREEMPT
59 select ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE if !PREEMPT
60 select ARCH_USE_CMPXCHG_LOCKREF
61 select ARCH_USE_QUEUED_RWLOCKS
62 select ARCH_USE_QUEUED_SPINLOCKS
63 select ARCH_SUPPORTS_MEMORY_FAILURE
64 select ARCH_SUPPORTS_ATOMIC_RMW
65 select ARCH_SUPPORTS_INT128 if GCC_VERSION >= 50000 || CC_IS_CLANG
66 select ARCH_SUPPORTS_NUMA_BALANCING
67 select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
68 select ARCH_WANT_FRAME_POINTERS
69 select ARCH_HAS_UBSAN_SANITIZE_ALL
70 select ARM_AMBA
71 select ARM_ARCH_TIMER
72 select ARM_GIC
73 select AUDIT_ARCH_COMPAT_GENERIC
74 select ARM_GIC_V2M if PCI
75 select ARM_GIC_V3
76 select ARM_GIC_V3_ITS if PCI
77 select ARM_PSCI_FW
78 select BUILDTIME_EXTABLE_SORT
79 select CLONE_BACKWARDS
80 select COMMON_CLK
81 select CPU_PM if (SUSPEND || CPU_IDLE)
82 select CRC32
83 select DCACHE_WORD_ACCESS
84 select DMA_DIRECT_OPS
85 select EDAC_SUPPORT
86 select FRAME_POINTER
87 select GENERIC_ALLOCATOR
88 select GENERIC_ARCH_TOPOLOGY
89 select GENERIC_CLOCKEVENTS
90 select GENERIC_CLOCKEVENTS_BROADCAST
91 select GENERIC_CPU_AUTOPROBE
92 select GENERIC_EARLY_IOREMAP
93 select GENERIC_IDLE_POLL_SETUP
94 select GENERIC_IRQ_MULTI_HANDLER
95 select GENERIC_IRQ_PROBE
96 select GENERIC_IRQ_SHOW
97 select GENERIC_IRQ_SHOW_LEVEL
98 select GENERIC_PCI_IOMAP
99 select GENERIC_SCHED_CLOCK
100 select GENERIC_SMP_IDLE_THREAD
101 select GENERIC_STRNCPY_FROM_USER
102 select GENERIC_STRNLEN_USER
103 select GENERIC_TIME_VSYSCALL
104 select HANDLE_DOMAIN_IRQ
105 select HARDIRQS_SW_RESEND
106 select HAVE_ACPI_APEI if (ACPI && EFI)
107 select HAVE_ALIGNED_STRUCT_PAGE if SLUB
108 select HAVE_ARCH_AUDITSYSCALL
109 select HAVE_ARCH_BITREVERSE
110 select HAVE_ARCH_HUGE_VMAP
111 select HAVE_ARCH_JUMP_LABEL
112 select HAVE_ARCH_JUMP_LABEL_RELATIVE
113 select HAVE_ARCH_KASAN if !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
114 select HAVE_ARCH_KGDB
115 select HAVE_ARCH_MMAP_RND_BITS
116 select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
117 select HAVE_ARCH_PREL32_RELOCATIONS
118 select HAVE_ARCH_SECCOMP_FILTER
119 select HAVE_ARCH_STACKLEAK
120 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
121 select HAVE_ARCH_TRACEHOOK
122 select HAVE_ARCH_TRANSPARENT_HUGEPAGE
123 select HAVE_ARCH_VMAP_STACK
124 select HAVE_ARM_SMCCC
125 select HAVE_EBPF_JIT
126 select HAVE_C_RECORDMCOUNT
127 select HAVE_CMPXCHG_DOUBLE
128 select HAVE_CMPXCHG_LOCAL
129 select HAVE_CONTEXT_TRACKING
130 select HAVE_DEBUG_BUGVERBOSE
131 select HAVE_DEBUG_KMEMLEAK
132 select HAVE_DMA_CONTIGUOUS
133 select HAVE_DYNAMIC_FTRACE
134 select HAVE_EFFICIENT_UNALIGNED_ACCESS
135 select HAVE_FTRACE_MCOUNT_RECORD
136 select HAVE_FUNCTION_TRACER
137 select HAVE_FUNCTION_GRAPH_TRACER
138 select HAVE_GCC_PLUGINS
139 select HAVE_GENERIC_DMA_COHERENT
140 select HAVE_HW_BREAKPOINT if PERF_EVENTS
141 select HAVE_IRQ_TIME_ACCOUNTING
142 select HAVE_MEMBLOCK
143 select HAVE_MEMBLOCK_NODE_MAP if NUMA
144 select HAVE_NMI
145 select HAVE_PATA_PLATFORM
146 select HAVE_PERF_EVENTS
147 select HAVE_PERF_REGS
148 select HAVE_PERF_USER_STACK_DUMP
149 select HAVE_REGS_AND_STACK_ACCESS_API
150 select HAVE_RCU_TABLE_FREE
151 select HAVE_RCU_TABLE_INVALIDATE
152 select HAVE_RSEQ
153 select HAVE_STACKPROTECTOR
154 select HAVE_SYSCALL_TRACEPOINTS
155 select HAVE_KPROBES
156 select HAVE_KRETPROBES
157 select IOMMU_DMA if IOMMU_SUPPORT
158 select IRQ_DOMAIN
159 select IRQ_FORCED_THREADING
160 select MODULES_USE_ELF_RELA
161 select MULTI_IRQ_HANDLER
162 select NEED_DMA_MAP_STATE
163 select NEED_SG_DMA_LENGTH
164 select NO_BOOTMEM
165 select OF
166 select OF_EARLY_FLATTREE
167 select OF_RESERVED_MEM
168 select PCI_ECAM if ACPI
169 select POWER_RESET
170 select POWER_SUPPLY
171 select REFCOUNT_FULL
172 select SPARSE_IRQ
173 select SWIOTLB
174 select SYSCTL_EXCEPTION_TRACE
175 select THREAD_INFO_IN_TASK
176 help
177 ARM 64-bit (AArch64) Linux support.
179 config 64BIT
180 def_bool y
182 config MMU
183 def_bool y
185 config ARM64_PAGE_SHIFT
186 int
187 default 16 if ARM64_64K_PAGES
188 default 14 if ARM64_16K_PAGES
189 default 12
191 config ARM64_CONT_SHIFT
192 int
193 default 5 if ARM64_64K_PAGES
194 default 7 if ARM64_16K_PAGES
195 default 4
197 config ARCH_MMAP_RND_BITS_MIN
198 default 14 if ARM64_64K_PAGES
199 default 16 if ARM64_16K_PAGES
200 default 18
202 # max bits determined by the following formula:
203 # VA_BITS - PAGE_SHIFT - 3
204 config ARCH_MMAP_RND_BITS_MAX
205 default 19 if ARM64_VA_BITS=36
206 default 24 if ARM64_VA_BITS=39
207 default 27 if ARM64_VA_BITS=42
208 default 30 if ARM64_VA_BITS=47
209 default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
210 default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
211 default 33 if ARM64_VA_BITS=48
212 default 14 if ARM64_64K_PAGES
213 default 16 if ARM64_16K_PAGES
214 default 18
216 config ARCH_MMAP_RND_COMPAT_BITS_MIN
217 default 7 if ARM64_64K_PAGES
218 default 9 if ARM64_16K_PAGES
219 default 11
221 config ARCH_MMAP_RND_COMPAT_BITS_MAX
222 default 16
224 config NO_IOPORT_MAP
225 def_bool y if !PCI
227 config STACKTRACE_SUPPORT
228 def_bool y
230 config ILLEGAL_POINTER_VALUE
231 hex
232 default 0xdead000000000000
234 config LOCKDEP_SUPPORT
235 def_bool y
237 config TRACE_IRQFLAGS_SUPPORT
238 def_bool y
240 config RWSEM_XCHGADD_ALGORITHM
241 def_bool y
243 config GENERIC_BUG
244 def_bool y
245 depends on BUG
247 config GENERIC_BUG_RELATIVE_POINTERS
248 def_bool y
249 depends on GENERIC_BUG
251 config GENERIC_HWEIGHT
252 def_bool y
254 config GENERIC_CSUM
255 def_bool y
257 config GENERIC_CALIBRATE_DELAY
258 def_bool y
260 config ZONE_DMA32
261 def_bool y
263 config HAVE_GENERIC_GUP
264 def_bool y
266 config SMP
267 def_bool y
269 config KERNEL_MODE_NEON
270 def_bool y
272 config FIX_EARLYCON_MEM
273 def_bool y
275 config PGTABLE_LEVELS
276 int
277 default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
278 default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
279 default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
280 default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
281 default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
282 default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
284 config ARCH_SUPPORTS_UPROBES
285 def_bool y
287 config ARCH_PROC_KCORE_TEXT
288 def_bool y
290 source "arch/arm64/Kconfig.platforms"
292 menu "Bus support"
294 config PCI
295 bool "PCI support"
296 help
297 This feature enables support for PCI bus system. If you say Y
298 here, the kernel will include drivers and infrastructure code
299 to support PCI bus devices.
301 config PCI_DOMAINS
302 def_bool PCI
304 config PCI_DOMAINS_GENERIC
305 def_bool PCI
307 config PCI_SYSCALL
308 def_bool PCI
310 source "drivers/pci/Kconfig"
312 endmenu
314 menu "Kernel Features"
316 menu "ARM errata workarounds via the alternatives framework"
318 config ARM64_ERRATUM_826319
319 bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
320 default y
321 help
322 This option adds an alternative code sequence to work around ARM
323 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
324 AXI master interface and an L2 cache.
326 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
327 and is unable to accept a certain write via this interface, it will
328 not progress on read data presented on the read data channel and the
329 system can deadlock.
331 The workaround promotes data cache clean instructions to
332 data cache clean-and-invalidate.
333 Please note that this does not necessarily enable the workaround,
334 as it depends on the alternative framework, which will only patch
335 the kernel if an affected CPU is detected.
337 If unsure, say Y.
339 config ARM64_ERRATUM_827319
340 bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
341 default y
342 help
343 This option adds an alternative code sequence to work around ARM
344 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
345 master interface and an L2 cache.
347 Under certain conditions this erratum can cause a clean line eviction
348 to occur at the same time as another transaction to the same address
349 on the AMBA 5 CHI interface, which can cause data corruption if the
350 interconnect reorders the two transactions.
352 The workaround promotes data cache clean instructions to
353 data cache clean-and-invalidate.
354 Please note that this does not necessarily enable the workaround,
355 as it depends on the alternative framework, which will only patch
356 the kernel if an affected CPU is detected.
358 If unsure, say Y.
360 config ARM64_ERRATUM_824069
361 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
362 default y
363 help
364 This option adds an alternative code sequence to work around ARM
365 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
366 to a coherent interconnect.
368 If a Cortex-A53 processor is executing a store or prefetch for
369 write instruction at the same time as a processor in another
370 cluster is executing a cache maintenance operation to the same
371 address, then this erratum might cause a clean cache line to be
372 incorrectly marked as dirty.
374 The workaround promotes data cache clean instructions to
375 data cache clean-and-invalidate.
376 Please note that this option does not necessarily enable the
377 workaround, as it depends on the alternative framework, which will
378 only patch the kernel if an affected CPU is detected.
380 If unsure, say Y.
382 config ARM64_ERRATUM_819472
383 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
384 default y
385 help
386 This option adds an alternative code sequence to work around ARM
387 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
388 present when it is connected to a coherent interconnect.
390 If the processor is executing a load and store exclusive sequence at
391 the same time as a processor in another cluster is executing a cache
392 maintenance operation to the same address, then this erratum might
393 cause data corruption.
395 The workaround promotes data cache clean instructions to
396 data cache clean-and-invalidate.
397 Please note that this does not necessarily enable the workaround,
398 as it depends on the alternative framework, which will only patch
399 the kernel if an affected CPU is detected.
401 If unsure, say Y.
403 config ARM64_ERRATUM_832075
404 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
405 default y
406 help
407 This option adds an alternative code sequence to work around ARM
408 erratum 832075 on Cortex-A57 parts up to r1p2.
410 Affected Cortex-A57 parts might deadlock when exclusive load/store
411 instructions to Write-Back memory are mixed with Device loads.
413 The workaround is to promote device loads to use Load-Acquire
414 semantics.
415 Please note that this does not necessarily enable the workaround,
416 as it depends on the alternative framework, which will only patch
417 the kernel if an affected CPU is detected.
419 If unsure, say Y.
421 config ARM64_ERRATUM_834220
422 bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
423 depends on KVM
424 default y
425 help
426 This option adds an alternative code sequence to work around ARM
427 erratum 834220 on Cortex-A57 parts up to r1p2.
429 Affected Cortex-A57 parts might report a Stage 2 translation
430 fault as the result of a Stage 1 fault for load crossing a
431 page boundary when there is a permission or device memory
432 alignment fault at Stage 1 and a translation fault at Stage 2.
434 The workaround is to verify that the Stage 1 translation
435 doesn't generate a fault before handling the Stage 2 fault.
436 Please note that this does not necessarily enable the workaround,
437 as it depends on the alternative framework, which will only patch
438 the kernel if an affected CPU is detected.
440 If unsure, say Y.
442 config ARM64_ERRATUM_845719
443 bool "Cortex-A53: 845719: a load might read incorrect data"
444 depends on COMPAT
445 default y
446 help
447 This option adds an alternative code sequence to work around ARM
448 erratum 845719 on Cortex-A53 parts up to r0p4.
450 When running a compat (AArch32) userspace on an affected Cortex-A53
451 part, a load at EL0 from a virtual address that matches the bottom 32
452 bits of the virtual address used by a recent load at (AArch64) EL1
453 might return incorrect data.
455 The workaround is to write the contextidr_el1 register on exception
456 return to a 32-bit task.
457 Please note that this does not necessarily enable the workaround,
458 as it depends on the alternative framework, which will only patch
459 the kernel if an affected CPU is detected.
461 If unsure, say Y.
463 config ARM64_ERRATUM_843419
464 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
465 default y
466 select ARM64_MODULE_PLTS if MODULES
467 help
468 This option links the kernel with '--fix-cortex-a53-843419' and
469 enables PLT support to replace certain ADRP instructions, which can
470 cause subsequent memory accesses to use an incorrect address on
471 Cortex-A53 parts up to r0p4.
473 If unsure, say Y.
475 config ARM64_ERRATUM_1024718
476 bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorrect update"
477 default y
478 help
479 This option adds work around for Arm Cortex-A55 Erratum 1024718.
481 Affected Cortex-A55 cores (r0p0, r0p1, r1p0) could cause incorrect
482 update of the hardware dirty bit when the DBM/AP bits are updated
483 without a break-before-make. The work around is to disable the usage
484 of hardware DBM locally on the affected cores. CPUs not affected by
485 erratum will continue to use the feature.
487 If unsure, say Y.
489 config ARM64_ERRATUM_1188873
490 bool "Cortex-A76: MRC read following MRRC read of specific Generic Timer in AArch32 might give incorrect result"
491 default y
492 select ARM_ARCH_TIMER_OOL_WORKAROUND
493 help
494 This option adds work arounds for ARM Cortex-A76 erratum 1188873
496 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could cause
497 register corruption when accessing the timer registers from
498 AArch32 userspace.
500 If unsure, say Y.
502 config CAVIUM_ERRATUM_22375
503 bool "Cavium erratum 22375, 24313"
504 default y
505 help
506 Enable workaround for erratum 22375, 24313.
508 This implements two gicv3-its errata workarounds for ThunderX. Both
509 with small impact affecting only ITS table allocation.
511 erratum 22375: only alloc 8MB table size
512 erratum 24313: ignore memory access type
514 The fixes are in ITS initialization and basically ignore memory access
515 type and table size provided by the TYPER and BASER registers.
517 If unsure, say Y.
519 config CAVIUM_ERRATUM_23144
520 bool "Cavium erratum 23144: ITS SYNC hang on dual socket system"
521 depends on NUMA
522 default y
523 help
524 ITS SYNC command hang for cross node io and collections/cpu mapping.
526 If unsure, say Y.
528 config CAVIUM_ERRATUM_23154
529 bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
530 default y
531 help
532 The gicv3 of ThunderX requires a modified version for
533 reading the IAR status to ensure data synchronization
534 (access to icc_iar1_el1 is not sync'ed before and after).
536 If unsure, say Y.
538 config CAVIUM_ERRATUM_27456
539 bool "Cavium erratum 27456: Broadcast TLBI instructions may cause icache corruption"
540 default y
541 help
542 On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
543 instructions may cause the icache to become corrupted if it
544 contains data for a non-current ASID. The fix is to
545 invalidate the icache when changing the mm context.
547 If unsure, say Y.
549 config CAVIUM_ERRATUM_30115
550 bool "Cavium erratum 30115: Guest may disable interrupts in host"
551 default y
552 help
553 On ThunderX T88 pass 1.x through 2.2, T81 pass 1.0 through
554 1.2, and T83 Pass 1.0, KVM guest execution may disable
555 interrupts in host. Trapping both GICv3 group-0 and group-1
556 accesses sidesteps the issue.
558 If unsure, say Y.
560 config QCOM_FALKOR_ERRATUM_1003
561 bool "Falkor E1003: Incorrect translation due to ASID change"
562 default y
563 help
564 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
565 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
566 in TTBR1_EL1, this situation only occurs in the entry trampoline and
567 then only for entries in the walk cache, since the leaf translation
568 is unchanged. Work around the erratum by invalidating the walk cache
569 entries for the trampoline before entering the kernel proper.
571 config QCOM_FALKOR_ERRATUM_1009
572 bool "Falkor E1009: Prematurely complete a DSB after a TLBI"
573 default y
574 help
575 On Falkor v1, the CPU may prematurely complete a DSB following a
576 TLBI xxIS invalidate maintenance operation. Repeat the TLBI operation
577 one more time to fix the issue.
579 If unsure, say Y.
581 config QCOM_QDF2400_ERRATUM_0065
582 bool "QDF2400 E0065: Incorrect GITS_TYPER.ITT_Entry_size"
583 default y
584 help
585 On Qualcomm Datacenter Technologies QDF2400 SoC, ITS hardware reports
586 ITE size incorrectly. The GITS_TYPER.ITT_Entry_size field should have
587 been indicated as 16Bytes (0xf), not 8Bytes (0x7).
589 If unsure, say Y.
591 config SOCIONEXT_SYNQUACER_PREITS
592 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
593 default y
594 help
595 Socionext Synquacer SoCs implement a separate h/w block to generate
596 MSI doorbell writes with non-zero values for the device ID.
598 If unsure, say Y.
600 config HISILICON_ERRATUM_161600802
601 bool "Hip07 161600802: Erroneous redistributor VLPI base"
602 default y
603 help
604 The HiSilicon Hip07 SoC usees the wrong redistributor base
605 when issued ITS commands such as VMOVP and VMAPP, and requires
606 a 128kB offset to be applied to the target address in this commands.
608 If unsure, say Y.
610 config QCOM_FALKOR_ERRATUM_E1041
611 bool "Falkor E1041: Speculative instruction fetches might cause errant memory access"
612 default y
613 help
614 Falkor CPU may speculatively fetch instructions from an improper
615 memory location when MMU translation is changed from SCTLR_ELn[M]=1
616 to SCTLR_ELn[M]=0. Prefix an ISB instruction to fix the problem.
618 If unsure, say Y.
620 endmenu
623 choice
624 prompt "Page size"
625 default ARM64_4K_PAGES
626 help
627 Page size (translation granule) configuration.
629 config ARM64_4K_PAGES
630 bool "4KB"
631 help
632 This feature enables 4KB pages support.
634 config ARM64_16K_PAGES
635 bool "16KB"
636 help
637 The system will use 16KB pages support. AArch32 emulation
638 requires applications compiled with 16K (or a multiple of 16K)
639 aligned segments.
641 config ARM64_64K_PAGES
642 bool "64KB"
643 help
644 This feature enables 64KB pages support (4KB by default)
645 allowing only two levels of page tables and faster TLB
646 look-up. AArch32 emulation requires applications compiled
647 with 64K aligned segments.
649 endchoice
651 choice
652 prompt "Virtual address space size"
653 default ARM64_VA_BITS_39 if ARM64_4K_PAGES
654 default ARM64_VA_BITS_47 if ARM64_16K_PAGES
655 default ARM64_VA_BITS_42 if ARM64_64K_PAGES
656 help
657 Allows choosing one of multiple possible virtual address
658 space sizes. The level of translation table is determined by
659 a combination of page size and virtual address space size.
661 config ARM64_VA_BITS_36
662 bool "36-bit" if EXPERT
663 depends on ARM64_16K_PAGES
665 config ARM64_VA_BITS_39
666 bool "39-bit"
667 depends on ARM64_4K_PAGES
669 config ARM64_VA_BITS_42
670 bool "42-bit"
671 depends on ARM64_64K_PAGES
673 config ARM64_VA_BITS_47
674 bool "47-bit"
675 depends on ARM64_16K_PAGES
677 config ARM64_VA_BITS_48
678 bool "48-bit"
680 endchoice
682 config ARM64_VA_BITS
683 int
684 default 36 if ARM64_VA_BITS_36
685 default 39 if ARM64_VA_BITS_39
686 default 42 if ARM64_VA_BITS_42
687 default 47 if ARM64_VA_BITS_47
688 default 48 if ARM64_VA_BITS_48
690 choice
691 prompt "Physical address space size"
692 default ARM64_PA_BITS_48
693 help
694 Choose the maximum physical address range that the kernel will
695 support.
697 config ARM64_PA_BITS_48
698 bool "48-bit"
700 config ARM64_PA_BITS_52
701 bool "52-bit (ARMv8.2)"
702 depends on ARM64_64K_PAGES
703 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
704 help
705 Enable support for a 52-bit physical address space, introduced as
706 part of the ARMv8.2-LPA extension.
708 With this enabled, the kernel will also continue to work on CPUs that
709 do not support ARMv8.2-LPA, but with some added memory overhead (and
710 minor performance overhead).
712 endchoice
714 config ARM64_PA_BITS
715 int
716 default 48 if ARM64_PA_BITS_48
717 default 52 if ARM64_PA_BITS_52
719 config CPU_BIG_ENDIAN
720 bool "Build big-endian kernel"
721 help
722 Say Y if you plan on running a kernel in big-endian mode.
724 config SCHED_MC
725 bool "Multi-core scheduler support"
726 help
727 Multi-core scheduler support improves the CPU scheduler's decision
728 making when dealing with multi-core CPU chips at a cost of slightly
729 increased overhead in some places. If unsure say N here.
731 config SCHED_SMT
732 bool "SMT scheduler support"
733 help
734 Improves the CPU scheduler's decision making when dealing with
735 MultiThreading at a cost of slightly increased overhead in some
736 places. If unsure say N here.
738 config NR_CPUS
739 int "Maximum number of CPUs (2-4096)"
740 range 2 4096
741 # These have to remain sorted largest to smallest
742 default "64"
744 config HOTPLUG_CPU
745 bool "Support for hot-pluggable CPUs"
746 select GENERIC_IRQ_MIGRATION
747 help
748 Say Y here to experiment with turning CPUs off and on. CPUs
749 can be controlled through /sys/devices/system/cpu.
751 # Common NUMA Features
752 config NUMA
753 bool "Numa Memory Allocation and Scheduler Support"
754 select ACPI_NUMA if ACPI
755 select OF_NUMA
756 help
757 Enable NUMA (Non Uniform Memory Access) support.
759 The kernel will try to allocate memory used by a CPU on the
760 local memory of the CPU and add some more
761 NUMA awareness to the kernel.
763 config NODES_SHIFT
764 int "Maximum NUMA Nodes (as a power of 2)"
765 range 1 10
766 default "2"
767 depends on NEED_MULTIPLE_NODES
768 help
769 Specify the maximum number of NUMA Nodes available on the target
770 system. Increases memory reserved to accommodate various tables.
772 config USE_PERCPU_NUMA_NODE_ID
773 def_bool y
774 depends on NUMA
776 config HAVE_SETUP_PER_CPU_AREA
777 def_bool y
778 depends on NUMA
780 config NEED_PER_CPU_EMBED_FIRST_CHUNK
781 def_bool y
782 depends on NUMA
784 config HOLES_IN_ZONE
785 def_bool y
787 source kernel/Kconfig.hz
789 config ARCH_SUPPORTS_DEBUG_PAGEALLOC
790 def_bool y
792 config ARCH_SPARSEMEM_ENABLE
793 def_bool y
794 select SPARSEMEM_VMEMMAP_ENABLE
796 config ARCH_SPARSEMEM_DEFAULT
797 def_bool ARCH_SPARSEMEM_ENABLE
799 config ARCH_SELECT_MEMORY_MODEL
800 def_bool ARCH_SPARSEMEM_ENABLE
802 config ARCH_FLATMEM_ENABLE
803 def_bool !NUMA
805 config HAVE_ARCH_PFN_VALID
806 def_bool y
808 config HW_PERF_EVENTS
809 def_bool y
810 depends on ARM_PMU
812 config SYS_SUPPORTS_HUGETLBFS
813 def_bool y
815 config ARCH_WANT_HUGE_PMD_SHARE
816 def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
818 config ARCH_HAS_CACHE_LINE_SIZE
819 def_bool y
821 config SECCOMP
822 bool "Enable seccomp to safely compute untrusted bytecode"
823 ---help---
824 This kernel feature is useful for number crunching applications
825 that may need to compute untrusted bytecode during their
826 execution. By using pipes or other transports made available to
827 the process as file descriptors supporting the read/write
828 syscalls, it's possible to isolate those applications in
829 their own address space using seccomp. Once seccomp is
830 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
831 and the task is only allowed to execute a few safe syscalls
832 defined by each seccomp mode.
834 config PARAVIRT
835 bool "Enable paravirtualization code"
836 help
837 This changes the kernel so it can modify itself when it is run
838 under a hypervisor, potentially improving performance significantly
839 over full virtualization.
841 config PARAVIRT_TIME_ACCOUNTING
842 bool "Paravirtual steal time accounting"
843 select PARAVIRT
844 default n
845 help
846 Select this option to enable fine granularity task steal time
847 accounting. Time spent executing other tasks in parallel with
848 the current vCPU is discounted from the vCPU power. To account for
849 that, there can be a small performance impact.
851 If in doubt, say N here.
853 config KEXEC
854 depends on PM_SLEEP_SMP
855 select KEXEC_CORE
856 bool "kexec system call"
857 ---help---
858 kexec is a system call that implements the ability to shutdown your
859 current kernel, and to start another kernel. It is like a reboot
860 but it is independent of the system firmware. And like a reboot
861 you can start any kernel with it, not just Linux.
863 config CRASH_DUMP
864 bool "Build kdump crash kernel"
865 help
866 Generate crash dump after being started by kexec. This should
867 be normally only set in special crash dump kernels which are
868 loaded in the main kernel with kexec-tools into a specially
869 reserved region and then later executed after a crash by
870 kdump/kexec.
872 For more details see Documentation/kdump/kdump.txt
874 config XEN_DOM0
875 def_bool y
876 depends on XEN
878 config XEN
879 bool "Xen guest support on ARM64"
880 depends on ARM64 && OF
881 select SWIOTLB_XEN
882 select PARAVIRT
883 help
884 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
886 config FORCE_MAX_ZONEORDER
887 int
888 default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
889 default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
890 default "11"
891 help
892 The kernel memory allocator divides physically contiguous memory
893 blocks into "zones", where each zone is a power of two number of
894 pages. This option selects the largest power of two that the kernel
895 keeps in the memory allocator. If you need to allocate very large
896 blocks of physically contiguous memory, then you may need to
897 increase this value.
899 This config option is actually maximum order plus one. For example,
900 a value of 11 means that the largest free memory block is 2^10 pages.
902 We make sure that we can allocate upto a HugePage size for each configuration.
903 Hence we have :
904 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
906 However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
907 4M allocations matching the default size used by generic code.
909 config UNMAP_KERNEL_AT_EL0
910 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
911 default y
912 help
913 Speculation attacks against some high-performance processors can
914 be used to bypass MMU permission checks and leak kernel data to
915 userspace. This can be defended against by unmapping the kernel
916 when running in userspace, mapping it back in on exception entry
917 via a trampoline page in the vector table.
919 If unsure, say Y.
921 config HARDEN_BRANCH_PREDICTOR
922 bool "Harden the branch predictor against aliasing attacks" if EXPERT
923 default y
924 help
925 Speculation attacks against some high-performance processors rely on
926 being able to manipulate the branch predictor for a victim context by
927 executing aliasing branches in the attacker context. Such attacks
928 can be partially mitigated against by clearing internal branch
929 predictor state and limiting the prediction logic in some situations.
931 This config option will take CPU-specific actions to harden the
932 branch predictor against aliasing attacks and may rely on specific
933 instruction sequences or control bits being set by the system
934 firmware.
936 If unsure, say Y.
938 config HARDEN_EL2_VECTORS
939 bool "Harden EL2 vector mapping against system register leak" if EXPERT
940 default y
941 help
942 Speculation attacks against some high-performance processors can
943 be used to leak privileged information such as the vector base
944 register, resulting in a potential defeat of the EL2 layout
945 randomization.
947 This config option will map the vectors to a fixed location,
948 independent of the EL2 code mapping, so that revealing VBAR_EL2
949 to an attacker does not give away any extra information. This
950 only gets enabled on affected CPUs.
952 If unsure, say Y.
954 config ARM64_SSBD
955 bool "Speculative Store Bypass Disable" if EXPERT
956 default y
957 help
958 This enables mitigation of the bypassing of previous stores
959 by speculative loads.
961 If unsure, say Y.
963 menuconfig ARMV8_DEPRECATED
964 bool "Emulate deprecated/obsolete ARMv8 instructions"
965 depends on COMPAT
966 depends on SYSCTL
967 help
968 Legacy software support may require certain instructions
969 that have been deprecated or obsoleted in the architecture.
971 Enable this config to enable selective emulation of these
972 features.
974 If unsure, say Y
976 if ARMV8_DEPRECATED
978 config SWP_EMULATION
979 bool "Emulate SWP/SWPB instructions"
980 help
981 ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
982 they are always undefined. Say Y here to enable software
983 emulation of these instructions for userspace using LDXR/STXR.
985 In some older versions of glibc [<=2.8] SWP is used during futex
986 trylock() operations with the assumption that the code will not
987 be preempted. This invalid assumption may be more likely to fail
988 with SWP emulation enabled, leading to deadlock of the user
989 application.
991 NOTE: when accessing uncached shared regions, LDXR/STXR rely
992 on an external transaction monitoring block called a global
993 monitor to maintain update atomicity. If your system does not
994 implement a global monitor, this option can cause programs that
995 perform SWP operations to uncached memory to deadlock.
997 If unsure, say Y
999 config CP15_BARRIER_EMULATION
1000 bool "Emulate CP15 Barrier instructions"
1001 help
1002 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1003 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1004 strongly recommended to use the ISB, DSB, and DMB
1005 instructions instead.
1007 Say Y here to enable software emulation of these
1008 instructions for AArch32 userspace code. When this option is
1009 enabled, CP15 barrier usage is traced which can help
1010 identify software that needs updating.
1012 If unsure, say Y
1014 config SETEND_EMULATION
1015 bool "Emulate SETEND instruction"
1016 help
1017 The SETEND instruction alters the data-endianness of the
1018 AArch32 EL0, and is deprecated in ARMv8.
1020 Say Y here to enable software emulation of the instruction
1021 for AArch32 userspace code.
1023 Note: All the cpus on the system must have mixed endian support at EL0
1024 for this feature to be enabled. If a new CPU - which doesn't support mixed
1025 endian - is hotplugged in after this feature has been enabled, there could
1026 be unexpected results in the applications.
1028 If unsure, say Y
1029 endif
1031 config ARM64_SW_TTBR0_PAN
1032 bool "Emulate Privileged Access Never using TTBR0_EL1 switching"
1033 help
1034 Enabling this option prevents the kernel from accessing
1035 user-space memory directly by pointing TTBR0_EL1 to a reserved
1036 zeroed area and reserved ASID. The user access routines
1037 restore the valid TTBR0_EL1 temporarily.
1039 menu "ARMv8.1 architectural features"
1041 config ARM64_HW_AFDBM
1042 bool "Support for hardware updates of the Access and Dirty page flags"
1043 default y
1044 help
1045 The ARMv8.1 architecture extensions introduce support for
1046 hardware updates of the access and dirty information in page
1047 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1048 capable processors, accesses to pages with PTE_AF cleared will
1049 set this bit instead of raising an access flag fault.
1050 Similarly, writes to read-only pages with the DBM bit set will
1051 clear the read-only bit (AP[2]) instead of raising a
1052 permission fault.
1054 Kernels built with this configuration option enabled continue
1055 to work on pre-ARMv8.1 hardware and the performance impact is
1056 minimal. If unsure, say Y.
1058 config ARM64_PAN
1059 bool "Enable support for Privileged Access Never (PAN)"
1060 default y
1061 help
1062 Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
1063 prevents the kernel or hypervisor from accessing user-space (EL0)
1064 memory directly.
1066 Choosing this option will cause any unprotected (not using
1067 copy_to_user et al) memory access to fail with a permission fault.
1069 The feature is detected at runtime, and will remain as a 'nop'
1070 instruction if the cpu does not implement the feature.
1072 config ARM64_LSE_ATOMICS
1073 bool "Atomic instructions"
1074 default y
1075 help
1076 As part of the Large System Extensions, ARMv8.1 introduces new
1077 atomic instructions that are designed specifically to scale in
1078 very large systems.
1080 Say Y here to make use of these instructions for the in-kernel
1081 atomic routines. This incurs a small overhead on CPUs that do
1082 not support these instructions and requires the kernel to be
1083 built with binutils >= 2.25 in order for the new instructions
1084 to be used.
1086 config ARM64_VHE
1087 bool "Enable support for Virtualization Host Extensions (VHE)"
1088 default y
1089 help
1090 Virtualization Host Extensions (VHE) allow the kernel to run
1091 directly at EL2 (instead of EL1) on processors that support
1092 it. This leads to better performance for KVM, as they reduce
1093 the cost of the world switch.
1095 Selecting this option allows the VHE feature to be detected
1096 at runtime, and does not affect processors that do not
1097 implement this feature.
1099 endmenu
1101 menu "ARMv8.2 architectural features"
1103 config ARM64_UAO
1104 bool "Enable support for User Access Override (UAO)"
1105 default y
1106 help
1107 User Access Override (UAO; part of the ARMv8.2 Extensions)
1108 causes the 'unprivileged' variant of the load/store instructions to
1109 be overridden to be privileged.
1111 This option changes get_user() and friends to use the 'unprivileged'
1112 variant of the load/store instructions. This ensures that user-space
1113 really did have access to the supplied memory. When addr_limit is
1114 set to kernel memory the UAO bit will be set, allowing privileged
1115 access to kernel memory.
1117 Choosing this option will cause copy_to_user() et al to use user-space
1118 memory permissions.
1120 The feature is detected at runtime, the kernel will use the
1121 regular load/store instructions if the cpu does not implement the
1122 feature.
1124 config ARM64_PMEM
1125 bool "Enable support for persistent memory"
1126 select ARCH_HAS_PMEM_API
1127 select ARCH_HAS_UACCESS_FLUSHCACHE
1128 help
1129 Say Y to enable support for the persistent memory API based on the
1130 ARMv8.2 DCPoP feature.
1132 The feature is detected at runtime, and the kernel will use DC CVAC
1133 operations if DC CVAP is not supported (following the behaviour of
1134 DC CVAP itself if the system does not define a point of persistence).
1136 config ARM64_RAS_EXTN
1137 bool "Enable support for RAS CPU Extensions"
1138 default y
1139 help
1140 CPUs that support the Reliability, Availability and Serviceability
1141 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1142 errors, classify them and report them to software.
1144 On CPUs with these extensions system software can use additional
1145 barriers to determine if faults are pending and read the
1146 classification from a new set of registers.
1148 Selecting this feature will allow the kernel to use these barriers
1149 and access the new registers if the system supports the extension.
1150 Platform RAS features may additionally depend on firmware support.
1152 config ARM64_CNP
1153 bool "Enable support for Common Not Private (CNP) translations"
1154 default y
1155 depends on ARM64_PAN || !ARM64_SW_TTBR0_PAN
1156 help
1157 Common Not Private (CNP) allows translation table entries to
1158 be shared between different PEs in the same inner shareable
1159 domain, so the hardware can use this fact to optimise the
1160 caching of such entries in the TLB.
1162 Selecting this option allows the CNP feature to be detected
1163 at runtime, and does not affect PEs that do not implement
1164 this feature.
1166 endmenu
1168 config ARM64_SVE
1169 bool "ARM Scalable Vector Extension support"
1170 default y
1171 depends on !KVM || ARM64_VHE
1172 help
1173 The Scalable Vector Extension (SVE) is an extension to the AArch64
1174 execution state which complements and extends the SIMD functionality
1175 of the base architecture to support much larger vectors and to enable
1176 additional vectorisation opportunities.
1178 To enable use of this extension on CPUs that implement it, say Y.
1180 Note that for architectural reasons, firmware _must_ implement SVE
1181 support when running on SVE capable hardware. The required support
1182 is present in:
1184 * version 1.5 and later of the ARM Trusted Firmware
1185 * the AArch64 boot wrapper since commit 5e1261e08abf
1186 ("bootwrapper: SVE: Enable SVE for EL2 and below").
1188 For other firmware implementations, consult the firmware documentation
1189 or vendor.
1191 If you need the kernel to boot on SVE-capable hardware with broken
1192 firmware, you may need to say N here until you get your firmware
1193 fixed. Otherwise, you may experience firmware panics or lockups when
1194 booting the kernel. If unsure and you are not observing these
1195 symptoms, you should assume that it is safe to say Y.
1197 CPUs that support SVE are architecturally required to support the
1198 Virtualization Host Extensions (VHE), so the kernel makes no
1199 provision for supporting SVE alongside KVM without VHE enabled.
1200 Thus, you will need to enable CONFIG_ARM64_VHE if you want to support
1201 KVM in the same kernel image.
1203 config ARM64_MODULE_PLTS
1204 bool
1205 select HAVE_MOD_ARCH_SPECIFIC
1207 config RELOCATABLE
1208 bool
1209 help
1210 This builds the kernel as a Position Independent Executable (PIE),
1211 which retains all relocation metadata required to relocate the
1212 kernel binary at runtime to a different virtual address than the
1213 address it was linked at.
1214 Since AArch64 uses the RELA relocation format, this requires a
1215 relocation pass at runtime even if the kernel is loaded at the
1216 same address it was linked at.
1218 config RANDOMIZE_BASE
1219 bool "Randomize the address of the kernel image"
1220 select ARM64_MODULE_PLTS if MODULES
1221 select RELOCATABLE
1222 help
1223 Randomizes the virtual address at which the kernel image is
1224 loaded, as a security feature that deters exploit attempts
1225 relying on knowledge of the location of kernel internals.
1227 It is the bootloader's job to provide entropy, by passing a
1228 random u64 value in /chosen/kaslr-seed at kernel entry.
1230 When booting via the UEFI stub, it will invoke the firmware's
1231 EFI_RNG_PROTOCOL implementation (if available) to supply entropy
1232 to the kernel proper. In addition, it will randomise the physical
1233 location of the kernel Image as well.
1235 If unsure, say N.
1237 config RANDOMIZE_MODULE_REGION_FULL
1238 bool "Randomize the module region over a 4 GB range"
1239 depends on RANDOMIZE_BASE
1240 default y
1241 help
1242 Randomizes the location of the module region inside a 4 GB window
1243 covering the core kernel. This way, it is less likely for modules
1244 to leak information about the location of core kernel data structures
1245 but it does imply that function calls between modules and the core
1246 kernel will need to be resolved via veneers in the module PLT.
1248 When this option is not set, the module region will be randomized over
1249 a limited range that contains the [_stext, _etext] interval of the
1250 core kernel, so branch relocations are always in range.
1252 endmenu
1254 menu "Boot options"
1256 config ARM64_ACPI_PARKING_PROTOCOL
1257 bool "Enable support for the ARM64 ACPI parking protocol"
1258 depends on ACPI
1259 help
1260 Enable support for the ARM64 ACPI parking protocol. If disabled
1261 the kernel will not allow booting through the ARM64 ACPI parking
1262 protocol even if the corresponding data is present in the ACPI
1263 MADT table.
1265 config CMDLINE
1266 string "Default kernel command string"
1267 default ""
1268 help
1269 Provide a set of default command-line options at build time by
1270 entering them here. As a minimum, you should specify the the
1271 root device (e.g. root=/dev/nfs).
1273 config CMDLINE_FORCE
1274 bool "Always use the default kernel command string"
1275 help
1276 Always use the default kernel command string, even if the boot
1277 loader passes other arguments to the kernel.
1278 This is useful if you cannot or don't want to change the
1279 command-line options your boot loader passes to the kernel.
1281 config EFI_STUB
1282 bool
1284 config EFI
1285 bool "UEFI runtime support"
1286 depends on OF && !CPU_BIG_ENDIAN
1287 depends on KERNEL_MODE_NEON
1288 select ARCH_SUPPORTS_ACPI
1289 select LIBFDT
1290 select UCS2_STRING
1291 select EFI_PARAMS_FROM_FDT
1292 select EFI_RUNTIME_WRAPPERS
1293 select EFI_STUB
1294 select EFI_ARMSTUB
1295 default y
1296 help
1297 This option provides support for runtime services provided
1298 by UEFI firmware (such as non-volatile variables, realtime
1299 clock, and platform reset). A UEFI stub is also provided to
1300 allow the kernel to be booted as an EFI application. This
1301 is only useful on systems that have UEFI firmware.
1303 config DMI
1304 bool "Enable support for SMBIOS (DMI) tables"
1305 depends on EFI
1306 default y
1307 help
1308 This enables SMBIOS/DMI feature for systems.
1310 This option is only useful on systems that have UEFI firmware.
1311 However, even with this option, the resultant kernel should
1312 continue to boot on existing non-UEFI platforms.
1314 endmenu
1316 config COMPAT
1317 bool "Kernel support for 32-bit EL0"
1318 depends on ARM64_4K_PAGES || EXPERT
1319 select COMPAT_BINFMT_ELF if BINFMT_ELF
1320 select HAVE_UID16
1321 select OLD_SIGSUSPEND3
1322 select COMPAT_OLD_SIGACTION
1323 help
1324 This option enables support for a 32-bit EL0 running under a 64-bit
1325 kernel at EL1. AArch32-specific components such as system calls,
1326 the user helper functions, VFP support and the ptrace interface are
1327 handled appropriately by the kernel.
1329 If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
1330 that you will only be able to execute AArch32 binaries that were compiled
1331 with page size aligned segments.
1333 If you want to execute 32-bit userspace applications, say Y.
1335 config SYSVIPC_COMPAT
1336 def_bool y
1337 depends on COMPAT && SYSVIPC
1339 menu "Power management options"
1341 source "kernel/power/Kconfig"
1343 config ARCH_HIBERNATION_POSSIBLE
1344 def_bool y
1345 depends on CPU_PM
1347 config ARCH_HIBERNATION_HEADER
1348 def_bool y
1349 depends on HIBERNATION
1351 config ARCH_SUSPEND_POSSIBLE
1352 def_bool y
1354 endmenu
1356 menu "CPU Power Management"
1358 source "drivers/cpuidle/Kconfig"
1360 source "drivers/cpufreq/Kconfig"
1362 endmenu
1364 source "drivers/firmware/Kconfig"
1366 source "drivers/acpi/Kconfig"
1368 source "arch/arm64/kvm/Kconfig"
1370 if CRYPTO
1371 source "arch/arm64/crypto/Kconfig"
1372 endif