arch/nds32/include/asm/bitfield.h

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (C) 2005-2017 Andes Technology Corporation
   3
   4 #ifndef __NDS32_BITFIELD_H__
   5 #define __NDS32_BITFIELD_H__
   6 /******************************************************************************
   7  * cr0: CPU_VER (CPU Version Register)
   8  *****************************************************************************/
   9 #define CPU_VER_offCFGID        0       /* Minor configuration */
  10 #define CPU_VER_offREV          16      /* Revision of the CPU version */
  11 #define CPU_VER_offCPUID        24      /* Major CPU versions */
  12
  13 #define CPU_VER_mskCFGID        ( 0xFFFF  << CPU_VER_offCFGID )
  14 #define CPU_VER_mskREV          ( 0xFF  << CPU_VER_offREV )
  15 #define CPU_VER_mskCPUID        ( 0xFF  << CPU_VER_offCPUID )
  16
  17 /******************************************************************************
  18  * cr1: ICM_CFG (Instruction Cache/Memory Configuration Register)
  19  *****************************************************************************/
  20 #define ICM_CFG_offISET         0       /* I-cache sets (# of cache lines) per way */
  21 #define ICM_CFG_offIWAY         3       /* I-cache ways */
  22 #define ICM_CFG_offISZ          6       /* I-cache line size */
  23 #define ICM_CFG_offILCK         9       /* I-cache locking support */
  24 #define ICM_CFG_offILMB         10      /* On-chip ILM banks */
  25 #define ICM_CFG_offBSAV         13      /* ILM base register alignment version */
  26 /* bit 15:31 reserved */
  27
  28 #define ICM_CFG_mskISET         ( 0x7  << ICM_CFG_offISET )
  29 #define ICM_CFG_mskIWAY         ( 0x7  << ICM_CFG_offIWAY )
  30 #define ICM_CFG_mskISZ          ( 0x7  << ICM_CFG_offISZ )
  31 #define ICM_CFG_mskILCK         ( 0x1  << ICM_CFG_offILCK )
  32 #define ICM_CFG_mskILMB         ( 0x7  << ICM_CFG_offILMB )
  33 #define ICM_CFG_mskBSAV         ( 0x3  << ICM_CFG_offBSAV )
  34
  35 /******************************************************************************
  36  * cr2: DCM_CFG (Data Cache/Memory Configuration Register)
  37  *****************************************************************************/
  38 #define DCM_CFG_offDSET         0       /* D-cache sets (# of cache lines) per way */
  39 #define DCM_CFG_offDWAY         3       /* D-cache ways */
  40 #define DCM_CFG_offDSZ          6       /* D-cache line size */
  41 #define DCM_CFG_offDLCK         9       /* D-cache locking support */
  42 #define DCM_CFG_offDLMB         10      /* On-chip DLM banks */
  43 #define DCM_CFG_offBSAV         13      /* DLM base register alignment version */
  44 /* bit 15:31 reserved */
  45
  46 #define DCM_CFG_mskDSET         ( 0x7  << DCM_CFG_offDSET )
  47 #define DCM_CFG_mskDWAY         ( 0x7  << DCM_CFG_offDWAY )
  48 #define DCM_CFG_mskDSZ          ( 0x7  << DCM_CFG_offDSZ )
  49 #define DCM_CFG_mskDLCK         ( 0x1  << DCM_CFG_offDLCK )
  50 #define DCM_CFG_mskDLMB         ( 0x7  << DCM_CFG_offDLMB )
  51 #define DCM_CFG_mskBSAV         ( 0x3  << DCM_CFG_offBSAV )
  52
  53 /******************************************************************************
  54  * cr3: MMU_CFG (MMU Configuration Register)
  55  *****************************************************************************/
  56 #define MMU_CFG_offMMPS         0       /* Memory management protection scheme */
  57 #define MMU_CFG_offMMPV         2       /* Memory management protection version number */
  58 #define MMU_CFG_offFATB         7       /* Fully-associative or non-fully-associative TLB */
  59
  60 #define MMU_CFG_offTBW          8       /* TLB ways(non-associative) TBS */
  61 #define MMU_CFG_offTBS          11      /* TLB sets per way(non-associative) TBS */
  62 /* bit 14:14 reserved */
  63
  64 #define MMU_CFG_offEP8MIN4      15      /* 8KB page supported while minimum page is 4KB */
  65 #define MMU_CFG_offfEPSZ        16      /* Extra page size supported */
  66 #define MMU_CFG_offTLBLCK       24      /* TLB locking support */
  67 #define MMU_CFG_offHPTWK        25      /* Hardware Page Table Walker implemented */
  68 #define MMU_CFG_offDE           26      /* Default endian */
  69 #define MMU_CFG_offNTPT         27      /* Partitions for non-translated attributes */
  70 #define MMU_CFG_offIVTB         28      /* Invisible TLB */
  71 #define MMU_CFG_offVLPT         29      /* VLPT for fast TLB fill handling implemented */
  72 #define MMU_CFG_offNTME         30      /* Non-translated VA to PA mapping */
  73 /* bit 31 reserved */
  74
  75 #define MMU_CFG_mskMMPS         ( 0x3  << MMU_CFG_offMMPS )
  76 #define MMU_CFG_mskMMPV         ( 0x1F  << MMU_CFG_offMMPV )
  77 #define MMU_CFG_mskFATB         ( 0x1  << MMU_CFG_offFATB )
  78 #define MMU_CFG_mskTBW          ( 0x7  << MMU_CFG_offTBW )
  79 #define MMU_CFG_mskTBS          ( 0x7  << MMU_CFG_offTBS )
  80 #define MMU_CFG_mskEP8MIN4      ( 0x1  << MMU_CFG_offEP8MIN4 )
  81 #define MMU_CFG_mskfEPSZ        ( 0xFF  << MMU_CFG_offfEPSZ )
  82 #define MMU_CFG_mskTLBLCK       ( 0x1  << MMU_CFG_offTLBLCK )
  83 #define MMU_CFG_mskHPTWK        ( 0x1  << MMU_CFG_offHPTWK )
  84 #define MMU_CFG_mskDE           ( 0x1  << MMU_CFG_offDE )
  85 #define MMU_CFG_mskNTPT         ( 0x1  << MMU_CFG_offNTPT )
  86 #define MMU_CFG_mskIVTB         ( 0x1  << MMU_CFG_offIVTB )
  87 #define MMU_CFG_mskVLPT         ( 0x1  << MMU_CFG_offVLPT )
  88 #define MMU_CFG_mskNTME         ( 0x1  << MMU_CFG_offNTME )
  89
  90 /******************************************************************************
  91  * cr4: MSC_CFG (Misc Configuration Register)
  92  *****************************************************************************/
  93 #define MSC_CFG_offEDM          0
  94 #define MSC_CFG_offLMDMA        1
  95 #define MSC_CFG_offPFM          2
  96 #define MSC_CFG_offHSMP         3
  97 #define MSC_CFG_offTRACE        4
  98 #define MSC_CFG_offDIV          5
  99 #define MSC_CFG_offMAC          6
 100 #define MSC_CFG_offAUDIO        7
 101 #define MSC_CFG_offL2C          9
 102 #define MSC_CFG_offRDREG        10
 103 #define MSC_CFG_offADR24        11
 104 #define MSC_CFG_offINTLC        12
 105 #define MSC_CFG_offBASEV        13
 106 #define MSC_CFG_offNOD          16
 107 /* bit 13:31 reserved */
 108
 109 #define MSC_CFG_mskEDM          ( 0x1  << MSC_CFG_offEDM )
 110 #define MSC_CFG_mskLMDMA        ( 0x1  << MSC_CFG_offLMDMA )
 111 #define MSC_CFG_mskPFM          ( 0x1  << MSC_CFG_offPFM )
 112 #define MSC_CFG_mskHSMP         ( 0x1  << MSC_CFG_offHSMP )
 113 #define MSC_CFG_mskTRACE        ( 0x1  << MSC_CFG_offTRACE )
 114 #define MSC_CFG_mskDIV          ( 0x1  << MSC_CFG_offDIV )
 115 #define MSC_CFG_mskMAC          ( 0x1  << MSC_CFG_offMAC )
 116 #define MSC_CFG_mskAUDIO        ( 0x3  << MSC_CFG_offAUDIO )
 117 #define MSC_CFG_mskL2C          ( 0x1  << MSC_CFG_offL2C )
 118 #define MSC_CFG_mskRDREG        ( 0x1  << MSC_CFG_offRDREG )
 119 #define MSC_CFG_mskADR24        ( 0x1  << MSC_CFG_offADR24 )
 120 #define MSC_CFG_mskINTLC        ( 0x1  << MSC_CFG_offINTLC )
 121 #define MSC_CFG_mskBASEV        ( 0x7  << MSC_CFG_offBASEV )
 122 #define MSC_CFG_mskNOD          ( 0x1  << MSC_CFG_offNOD )
 123
 124 /******************************************************************************
 125  * cr5: CORE_CFG (Core Identification Register)
 126  *****************************************************************************/
 127 #define CORE_ID_offCOREID       0
 128 /* bit 4:31 reserved */
 129
 130 #define CORE_ID_mskCOREID       ( 0xF  << CORE_ID_offCOREID )
 131
 132 /******************************************************************************
 133  * cr6: FUCOP_EXIST (FPU and Coprocessor Existence Configuration Register)
 134  *****************************************************************************/
 135 #define FUCOP_EXIST_offCP0EX    0
 136 #define FUCOP_EXIST_offCP1EX    1
 137 #define FUCOP_EXIST_offCP2EX    2
 138 #define FUCOP_EXIST_offCP3EX    3
 139 #define FUCOP_EXIST_offCP0ISFPU 31
 140
 141 #define FUCOP_EXIST_mskCP0EX    ( 0x1  << FUCOP_EXIST_offCP0EX )
 142 #define FUCOP_EXIST_mskCP1EX    ( 0x1  << FUCOP_EXIST_offCP1EX )
 143 #define FUCOP_EXIST_mskCP2EX    ( 0x1  << FUCOP_EXIST_offCP2EX )
 144 #define FUCOP_EXIST_mskCP3EX    ( 0x1  << FUCOP_EXIST_offCP3EX )
 145 #define FUCOP_EXIST_mskCP0ISFPU ( 0x1  << FUCOP_EXIST_offCP0ISFPU )
 146
 147 /******************************************************************************
 148  * ir0: PSW (Processor Status Word Register)
 149  * ir1: IPSW (Interruption PSW Register)
 150  * ir2: P_IPSW (Previous IPSW Register)
 151  *****************************************************************************/
 152 #define PSW_offGIE              0       /* Global Interrupt Enable */
 153 #define PSW_offINTL             1       /* Interruption Stack Level */
 154 #define PSW_offPOM              3       /* Processor Operation Mode, User/Superuser */
 155 #define PSW_offBE               5       /* Endianness for data memory access, 1:MSB, 0:LSB */
 156 #define PSW_offIT               6       /* Enable instruction address translation */
 157 #define PSW_offDT               7       /* Enable data address translation */
 158 #define PSW_offIME              8       /* Instruction Machine Error flag */
 159 #define PSW_offDME              9       /* Data Machine Error flag */
 160 #define PSW_offDEX              10      /* Debug Exception */
 161 #define PSW_offHSS              11      /* Hardware Single Stepping */
 162 #define PSW_offDRBE             12      /* Device Register Endian Mode */
 163 #define PSW_offAEN              13      /* Audio ISA special feature */
 164 #define PSW_offWBNA             14      /* Write Back Non-Allocate */
 165 #define PSW_offIFCON            15      /* IFC On */
 166 #define PSW_offCPL              16      /* Current Priority Level */
 167 /* bit 19:31 reserved */
 168
 169 #define PSW_mskGIE              ( 0x1  << PSW_offGIE )
 170 #define PSW_mskINTL             ( 0x3  << PSW_offINTL )
 171 #define PSW_mskPOM              ( 0x3  << PSW_offPOM )
 172 #define PSW_mskBE               ( 0x1  << PSW_offBE )
 173 #define PSW_mskIT               ( 0x1  << PSW_offIT )
 174 #define PSW_mskDT               ( 0x1  << PSW_offDT )
 175 #define PSW_mskIME              ( 0x1  << PSW_offIME )
 176 #define PSW_mskDME              ( 0x1  << PSW_offDME )
 177 #define PSW_mskDEX              ( 0x1  << PSW_offDEX )
 178 #define PSW_mskHSS              ( 0x1  << PSW_offHSS )
 179 #define PSW_mskDRBE             ( 0x1  << PSW_offDRBE )
 180 #define PSW_mskAEN              ( 0x1  << PSW_offAEN )
 181 #define PSW_mskWBNA             ( 0x1  << PSW_offWBNA )
 182 #define PSW_mskIFCON            ( 0x1  << PSW_offIFCON )
 183 #define PSW_mskCPL              ( 0x7  << PSW_offCPL )
 184
 185 #define PSW_SYSTEM              ( 1 << PSW_offPOM )
 186 #define PSW_INTL_1              ( 1 << PSW_offINTL )
 187 #define PSW_CPL_NO              ( 0 << PSW_offCPL )
 188 #define PSW_CPL_ANY             ( 7 << PSW_offCPL )
 189
 190 #define PSW_clr                 (PSW_mskGIE|PSW_mskINTL|PSW_mskPOM|PSW_mskIT|PSW_mskDT|PSW_mskIME|PSW_mskWBNA)
 191 #ifdef __NDS32_EB__
 192 #ifdef CONFIG_WBNA
 193 #define PSW_init                (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
 194 #else
 195 #define PSW_init                ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT|PSW_mskBE)
 196 #endif
 197 #else
 198 #ifdef CONFIG_WBNA
 199 #define PSW_init                (PSW_mskWBNA|(1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
 200 #else
 201 #define PSW_init                ((1<<PSW_offINTL)|(1<<PSW_offPOM)|PSW_mskIT|PSW_mskDT)
 202 #endif
 203 #endif
 204 /******************************************************************************
 205  * ir3: IVB (Interruption Vector Base Register)
 206  *****************************************************************************/
 207 /* bit 0:12 reserved */
 208 #define IVB_offNIVIC            1       /* Number of input for IVIC Controller */
 209 #define IVB_offIVIC_VER         11      /* IVIC Version */
 210 #define IVB_offEVIC             13      /* External Vector Interrupt Controller mode */
 211 #define IVB_offESZ              14      /* Size of each vector entry */
 212 #define IVB_offIVBASE           16      /* BasePA of interrupt vector table */
 213
 214 #define IVB_mskNIVIC            ( 0x7  << IVB_offNIVIC )
 215 #define IVB_mskIVIC_VER         ( 0x3  << IVB_offIVIC_VER )
 216 #define IVB_mskEVIC             ( 0x1  << IVB_offEVIC )
 217 #define IVB_mskESZ              ( 0x3  << IVB_offESZ )
 218 #define IVB_mskIVBASE           ( 0xFFFF  << IVB_offIVBASE )
 219
 220 #define IVB_valESZ4             0
 221 #define IVB_valESZ16            1
 222 #define IVB_valESZ64            2
 223 #define IVB_valESZ256           3
 224 /******************************************************************************
 225  * ir4: EVA (Exception Virtual Address Register)
 226  * ir5: P_EVA (Previous EVA Register)
 227  *****************************************************************************/
 228
 229         /* This register contains the VA that causes the exception */
 230
 231 /******************************************************************************
 232  * ir6: ITYPE (Interruption Type Register)
 233  * ir7: P_ITYPE (Previous ITYPE Register)
 234  *****************************************************************************/
 235 #define ITYPE_offETYPE          0       /* Exception Type */
 236 #define ITYPE_offINST           4       /* Exception caused by insn fetch or data access */
 237 /* bit 5:15 reserved */
 238 #define ITYPE_offVECTOR         5       /* Vector */
 239 #define ITYPE_offSWID           16      /* SWID of debugging exception */
 240 /* bit 31:31 reserved */
 241
 242 #define ITYPE_mskETYPE          ( 0xF  << ITYPE_offETYPE )
 243 #define ITYPE_mskINST           ( 0x1  << ITYPE_offINST )
 244 #define ITYPE_mskVECTOR         ( 0x7F  << ITYPE_offVECTOR )
 245 #define ITYPE_mskSWID           ( 0x7FFF  << ITYPE_offSWID )
 246
 247 /* Additional definitions for ITYPE register */
 248 #define ITYPE_offSTYPE          16      /* Arithmetic Sub Type */
 249 #define ITYPE_offCPID           20      /* Co-Processor ID which generate the exception */
 250
 251 #define ITYPE_mskSTYPE          ( 0xF  << ITYPE_offSTYPE )
 252 #define ITYPE_mskCPID           ( 0x3  << ITYPE_offCPID )
 253
 254 #define NDS32_VECTOR_mskNONEXCEPTION    0x78
 255 #define NDS32_VECTOR_offEXCEPTION       8
 256 #define NDS32_VECTOR_offINTERRUPT       9
 257
 258 /* Interrupt vector entry */
 259 #define ENTRY_RESET_NMI                 0
 260 #define ENTRY_TLB_FILL                  1
 261 #define ENTRY_PTE_NOT_PRESENT           2
 262 #define ENTRY_TLB_MISC                  3
 263 #define ENTRY_TLB_VLPT_MISS             4
 264 #define ENTRY_MACHINE_ERROR             5
 265 #define ENTRY_DEBUG_RELATED             6
 266 #define ENTRY_GENERAL_EXCPETION         7
 267 #define ENTRY_SYSCALL                   8
 268
 269 /* PTE not present exception definition */
 270 #define ETYPE_NON_LEAF_PTE_NOT_PRESENT  0
 271 #define ETYPE_LEAF_PTE_NOT_PRESENT      1
 272
 273 /* General exception ETYPE definition */
 274 #define ETYPE_ALIGNMENT_CHECK           0
 275 #define ETYPE_RESERVED_INSTRUCTION      1
 276 #define ETYPE_TRAP                      2
 277 #define ETYPE_ARITHMETIC                3
 278 #define ETYPE_PRECISE_BUS_ERROR         4
 279 #define ETYPE_IMPRECISE_BUS_ERROR       5
 280 #define ETYPE_COPROCESSOR               6
 281 #define ETYPE_RESERVED_VALUE            7
 282 #define ETYPE_NONEXISTENT_MEM_ADDRESS   8
 283 #define ETYPE_MPZIU_CONTROL             9
 284 #define ETYPE_NEXT_PRECISE_STACK_OFL    10
 285
 286 /* Kerenl reserves software ID */
 287 #define SWID_RAISE_INTERRUPT_LEVEL      0x1a    /* SWID_RAISE_INTERRUPT_LEVEL is used to
 288                                                  * raise interrupt level for debug exception
 289                                                  */
 290
 291 /******************************************************************************
 292  * ir8: MERR (Machine Error Log Register)
 293  *****************************************************************************/
 294 /* bit 0:30 reserved */
 295 #define MERR_offBUSERR          31      /* Bus error caused by a load insn */
 296
 297 #define MERR_mskBUSERR          ( 0x1  << MERR_offBUSERR )
 298
 299 /******************************************************************************
 300  * ir9: IPC (Interruption Program Counter Register)
 301  * ir10: P_IPC (Previous IPC Register)
 302  * ir11: OIPC (Overflow Interruption Program Counter Register)
 303  *****************************************************************************/
 304
 305         /* This is the shadow stack register of the Program Counter */
 306
 307 /******************************************************************************
 308  * ir12: P_P0 (Previous P0 Register)
 309  * ir13: P_P1 (Previous P1 Register)
 310  *****************************************************************************/
 311
 312         /* These are shadow registers of $p0 and $p1 */
 313
 314 /******************************************************************************
 315  * ir14: INT_MASK (Interruption Masking Register)
 316  *****************************************************************************/
 317 #define INT_MASK_offH0IM        0       /* Hardware Interrupt 0 Mask bit */
 318 #define INT_MASK_offH1IM        1       /* Hardware Interrupt 1 Mask bit */
 319 #define INT_MASK_offH2IM        2       /* Hardware Interrupt 2 Mask bit */
 320 #define INT_MASK_offH3IM        3       /* Hardware Interrupt 3 Mask bit */
 321 #define INT_MASK_offH4IM        4       /* Hardware Interrupt 4 Mask bit */
 322 #define INT_MASK_offH5IM        5       /* Hardware Interrupt 5 Mask bit */
 323 /* bit 6:15 reserved */
 324 #define INT_MASK_offSIM         16      /* Software Interrupt Mask bit */
 325 /* bit 17:29 reserved */
 326 #define INT_MASK_offIDIVZE      30      /* Enable detection for Divide-By-Zero */
 327 #define INT_MASK_offDSSIM       31      /* Default Single Stepping Interruption Mask */
 328
 329 #define INT_MASK_mskH0IM        ( 0x1  << INT_MASK_offH0IM )
 330 #define INT_MASK_mskH1IM        ( 0x1  << INT_MASK_offH1IM )
 331 #define INT_MASK_mskH2IM        ( 0x1  << INT_MASK_offH2IM )
 332 #define INT_MASK_mskH3IM        ( 0x1  << INT_MASK_offH3IM )
 333 #define INT_MASK_mskH4IM        ( 0x1  << INT_MASK_offH4IM )
 334 #define INT_MASK_mskH5IM        ( 0x1  << INT_MASK_offH5IM )
 335 #define INT_MASK_mskSIM         ( 0x1  << INT_MASK_offSIM )
 336 #define INT_MASK_mskIDIVZE      ( 0x1  << INT_MASK_offIDIVZE )
 337 #define INT_MASK_mskDSSIM       ( 0x1  << INT_MASK_offDSSIM )
 338
 339 #define INT_MASK_INITAIAL_VAL   (INT_MASK_mskDSSIM|INT_MASK_mskIDIVZE)
 340
 341 /******************************************************************************
 342  * ir15: INT_PEND (Interrupt Pending Register)
 343  *****************************************************************************/
 344 #define INT_PEND_offH0I         0       /* Hardware Interrupt 0 pending bit */
 345 #define INT_PEND_offH1I         1       /* Hardware Interrupt 1 pending bit */
 346 #define INT_PEND_offH2I         2       /* Hardware Interrupt 2 pending bit */
 347 #define INT_PEND_offH3I         3       /* Hardware Interrupt 3 pending bit */
 348 #define INT_PEND_offH4I         4       /* Hardware Interrupt 4 pending bit */
 349 #define INT_PEND_offH5I         5       /* Hardware Interrupt 5 pending bit */
 350
 351 #define INT_PEND_offCIPL        0       /* Current Interrupt Priority Level */
 352
 353 /* bit 6:15 reserved */
 354 #define INT_PEND_offSWI         16      /* Software Interrupt pending bit */
 355 /* bit 17:31 reserved */
 356
 357 #define INT_PEND_mskH0I         ( 0x1  << INT_PEND_offH0I )
 358 #define INT_PEND_mskH1I         ( 0x1  << INT_PEND_offH1I )
 359 #define INT_PEND_mskH2I         ( 0x1  << INT_PEND_offH2I )
 360 #define INT_PEND_mskH3I         ( 0x1  << INT_PEND_offH3I )
 361 #define INT_PEND_mskH4I         ( 0x1  << INT_PEND_offH4I )
 362 #define INT_PEND_mskH5I         ( 0x1  << INT_PEND_offH5I )
 363 #define INT_PEND_mskCIPL        ( 0x1  << INT_PEND_offCIPL )
 364 #define INT_PEND_mskSWI         ( 0x1  << INT_PEND_offSWI )
 365
 366 /******************************************************************************
 367  * mr0: MMU_CTL (MMU Control Register)
 368  *****************************************************************************/
 369 #define MMU_CTL_offD            0       /* Default minimum page size */
 370 #define MMU_CTL_offNTC0         1       /* Non-Translated Cachebility of partition 0 */
 371 #define MMU_CTL_offNTC1         3       /* Non-Translated Cachebility of partition 1 */
 372 #define MMU_CTL_offNTC2         5       /* Non-Translated Cachebility of partition 2 */
 373 #define MMU_CTL_offNTC3         7       /* Non-Translated Cachebility of partition 3 */
 374 #define MMU_CTL_offTBALCK       9       /* TLB all-lock resolution scheme */
 375 #define MMU_CTL_offMPZIU        10      /* Multiple Page Size In Use bit */
 376 #define MMU_CTL_offNTM0         11      /* Non-Translated VA to PA of partition 0 */
 377 #define MMU_CTL_offNTM1         13      /* Non-Translated VA to PA of partition 1 */
 378 #define MMU_CTL_offNTM2         15      /* Non-Translated VA to PA of partition 2 */
 379 #define MMU_CTL_offNTM3         17      /* Non-Translated VA to PA of partition 3 */
 380 #define MMU_CTL_offUNA          23      /* Unaligned access */
 381 /* bit 24:31 reserved */
 382
 383 #define MMU_CTL_mskD            ( 0x1  << MMU_CTL_offD )
 384 #define MMU_CTL_mskNTC0         ( 0x3  << MMU_CTL_offNTC0 )
 385 #define MMU_CTL_mskNTC1         ( 0x3  << MMU_CTL_offNTC1 )
 386 #define MMU_CTL_mskNTC2         ( 0x3  << MMU_CTL_offNTC2 )
 387 #define MMU_CTL_mskNTC3         ( 0x3  << MMU_CTL_offNTC3 )
 388 #define MMU_CTL_mskTBALCK       ( 0x1  << MMU_CTL_offTBALCK )
 389 #define MMU_CTL_mskMPZIU        ( 0x1  << MMU_CTL_offMPZIU )
 390 #define MMU_CTL_mskNTM0         ( 0x3  << MMU_CTL_offNTM0 )
 391 #define MMU_CTL_mskNTM1         ( 0x3  << MMU_CTL_offNTM1 )
 392 #define MMU_CTL_mskNTM2         ( 0x3  << MMU_CTL_offNTM2 )
 393 #define MMU_CTL_mskNTM3         ( 0x3  << MMU_CTL_offNTM3 )
 394
 395 #define MMU_CTL_D4KB            0
 396 #define MMU_CTL_D8KB            1
 397 #define MMU_CTL_UNA             ( 0x1  << MMU_CTL_offUNA )
 398
 399 #define MMU_CTL_CACHEABLE_NON   0
 400 #define MMU_CTL_CACHEABLE_WB    2
 401 #define MMU_CTL_CACHEABLE_WT    3
 402
 403 /******************************************************************************
 404  * mr1: L1_PPTB (L1 Physical Page Table Base Register)
 405  *****************************************************************************/
 406 #define L1_PPTB_offNV           0       /* Enable Hardware Page Table Walker (HPTWK) */
 407 /* bit 1:11 reserved */
 408 #define L1_PPTB_offBASE         12      /* First level physical page table base address */
 409
 410 #define L1_PPTB_mskNV           ( 0x1  << L1_PPTB_offNV )
 411 #define L1_PPTB_mskBASE         ( 0xFFFFF  << L1_PPTB_offBASE )
 412
 413 /******************************************************************************
 414  * mr2: TLB_VPN (TLB Access VPN Register)
 415  *****************************************************************************/
 416 /* bit 0:11 reserved */
 417 #define TLB_VPN_offVPN          12      /* Virtual Page Number */
 418
 419 #define TLB_VPN_mskVPN          ( 0xFFFFF  << TLB_VPN_offVPN )
 420
 421 /******************************************************************************
 422  * mr3: TLB_DATA (TLB Access Data Register)
 423  *****************************************************************************/
 424 #define TLB_DATA_offV           0       /* PTE is valid and present */
 425 #define TLB_DATA_offM           1       /* Page read/write access privilege */
 426 #define TLB_DATA_offD           4       /* Dirty bit */
 427 #define TLB_DATA_offX           5       /* Executable bit */
 428 #define TLB_DATA_offA           6       /* Access bit */
 429 #define TLB_DATA_offG           7       /* Global page (shared across contexts) */
 430 #define TLB_DATA_offC           8       /* Cacheability atribute */
 431 /* bit 11:11 reserved */
 432 #define TLB_DATA_offPPN         12      /* Phisical Page Number */
 433
 434 #define TLB_DATA_mskV           ( 0x1  << TLB_DATA_offV )
 435 #define TLB_DATA_mskM           ( 0x7  << TLB_DATA_offM )
 436 #define TLB_DATA_mskD           ( 0x1  << TLB_DATA_offD )
 437 #define TLB_DATA_mskX           ( 0x1  << TLB_DATA_offX )
 438 #define TLB_DATA_mskA           ( 0x1  << TLB_DATA_offA )
 439 #define TLB_DATA_mskG           ( 0x1  << TLB_DATA_offG )
 440 #define TLB_DATA_mskC           ( 0x7  << TLB_DATA_offC )
 441 #define TLB_DATA_mskPPN         ( 0xFFFFF  << TLB_DATA_offPPN )
 442
 443 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
 444 #define TLB_DATA_kernel_text_attr       (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|TLB_DATA_mskC)
 445 #else
 446 #define TLB_DATA_kernel_text_attr       (TLB_DATA_mskV|TLB_DATA_mskM|TLB_DATA_mskD|TLB_DATA_mskX|TLB_DATA_mskG|(0x6 << TLB_DATA_offC))
 447 #endif
 448
 449 /******************************************************************************
 450  * mr4: TLB_MISC (TLB Access Misc Register)
 451  *****************************************************************************/
 452 #define TLB_MISC_offACC_PSZ     0       /* Page size of a PTE entry */
 453 #define TLB_MISC_offCID         4       /* Context id */
 454 /* bit 13:31 reserved */
 455
 456 #define TLB_MISC_mskACC_PSZ    ( 0xF  << TLB_MISC_offACC_PSZ )
 457 #define TLB_MISC_mskCID        ( 0x1FF  << TLB_MISC_offCID )
 458
 459 /******************************************************************************
 460  * mr5: VLPT_IDX (Virtual Linear Page Table Index Register)
 461  *****************************************************************************/
 462 #define VLPT_IDX_offZERO        0       /* Always 0 */
 463 #define VLPT_IDX_offEVPN        2       /* Exception Virtual Page Number */
 464 #define VLPT_IDX_offVLPTB       22      /* Base VA of VLPT */
 465
 466 #define VLPT_IDX_mskZERO        ( 0x3  << VLPT_IDX_offZERO )
 467 #define VLPT_IDX_mskEVPN        ( 0xFFFFF  << VLPT_IDX_offEVPN )
 468 #define VLPT_IDX_mskVLPTB       ( 0x3FF  << VLPT_IDX_offVLPTB )
 469
 470 /******************************************************************************
 471  * mr6: ILMB (Instruction Local Memory Base Register)
 472  *****************************************************************************/
 473 #define ILMB_offIEN             0       /* Enable ILM */
 474 #define ILMB_offILMSZ           1       /* Size of ILM */
 475 /* bit 5:19 reserved */
 476 #define ILMB_offIBPA            20      /* Base PA of ILM */
 477
 478 #define ILMB_mskIEN             ( 0x1  << ILMB_offIEN )
 479 #define ILMB_mskILMSZ           ( 0xF  << ILMB_offILMSZ )
 480 #define ILMB_mskIBPA            ( 0xFFF  << ILMB_offIBPA )
 481
 482 /******************************************************************************
 483  * mr7: DLMB (Data Local Memory Base Register)
 484  *****************************************************************************/
 485 #define DLMB_offDEN             0       /* Enable DLM */
 486 #define DLMB_offDLMSZ           1       /* Size of DLM */
 487 #define DLMB_offDBM             5       /* Enable Double-Buffer Mode for DLM */
 488 #define DLMB_offDBB             6       /* Double-buffer bank which can be accessed by the processor */
 489 /* bit 7:19 reserved */
 490 #define DLMB_offDBPA            20      /* Base PA of DLM */
 491
 492 #define DLMB_mskDEN             ( 0x1  << DLMB_offDEN )
 493 #define DLMB_mskDLMSZ           ( 0xF  << DLMB_offDLMSZ )
 494 #define DLMB_mskDBM             ( 0x1  << DLMB_offDBM )
 495 #define DLMB_mskDBB             ( 0x1  << DLMB_offDBB )
 496 #define DLMB_mskDBPA            ( 0xFFF  << DLMB_offDBPA )
 497
 498 /******************************************************************************
 499  * mr8: CACHE_CTL (Cache Control Register)
 500  *****************************************************************************/
 501 #define CACHE_CTL_offIC_EN      0       /* Enable I-cache */
 502 #define CACHE_CTL_offDC_EN      1       /* Enable D-cache */
 503 #define CACHE_CTL_offICALCK     2       /* I-cache all-lock resolution scheme */
 504 #define CACHE_CTL_offDCALCK     3       /* D-cache all-lock resolution scheme */
 505 #define CACHE_CTL_offDCCWF      4       /* Enable D-cache Critical Word Forwarding */
 506 #define CACHE_CTL_offDCPMW      5       /* Enable D-cache concurrent miss and write-back processing */
 507 /* bit 6:31 reserved */
 508
 509 #define CACHE_CTL_mskIC_EN      ( 0x1  << CACHE_CTL_offIC_EN )
 510 #define CACHE_CTL_mskDC_EN      ( 0x1  << CACHE_CTL_offDC_EN )
 511 #define CACHE_CTL_mskICALCK     ( 0x1  << CACHE_CTL_offICALCK )
 512 #define CACHE_CTL_mskDCALCK     ( 0x1  << CACHE_CTL_offDCALCK )
 513 #define CACHE_CTL_mskDCCWF      ( 0x1  << CACHE_CTL_offDCCWF )
 514 #define CACHE_CTL_mskDCPMW      ( 0x1  << CACHE_CTL_offDCPMW )
 515
 516 /******************************************************************************
 517  * mr9: HSMP_SADDR (High Speed Memory Port Starting Address)
 518  *****************************************************************************/
 519 #define HSMP_SADDR_offEN        0       /* Enable control bit for the High Speed Memory port */
 520 /* bit 1:19 reserved */
 521
 522 #define HSMP_SADDR_offRANGE     1       /* Denote the address range (only defined in HSMP v2 ) */
 523 #define HSMP_SADDR_offSADDR     20      /* Starting base PA of the High Speed Memory Port region */
 524
 525 #define HSMP_SADDR_mskEN        ( 0x1  << HSMP_SADDR_offEN )
 526 #define HSMP_SADDR_mskRANGE     ( 0xFFF  << HSMP_SADDR_offRANGE )
 527 #define HSMP_SADDR_mskSADDR     ( 0xFFF  << HSMP_SADDR_offSADDR )
 528
 529 /******************************************************************************
 530  * mr10: HSMP_EADDR (High Speed Memory Port Ending Address)
 531  *****************************************************************************/
 532 /* bit 0:19 reserved */
 533 #define HSMP_EADDR_offEADDR     20
 534
 535 #define HSMP_EADDR_mskEADDR     ( 0xFFF  << HSMP_EADDR_offEADDR )
 536
 537 /******************************************************************************
 538  * dr0+(n*5): BPCn (n=0-7) (Breakpoint Control Register)
 539  *****************************************************************************/
 540 #define BPC_offWP               0       /* Configuration of BPAn */
 541 #define BPC_offEL               1       /* Enable BPAn */
 542 #define BPC_offS                2       /* Data address comparison for a store instruction */
 543 #define BPC_offP                3       /* Compared data address is PA */
 544 #define BPC_offC                4       /* CID value is compared with the BPCIDn register */
 545 #define BPC_offBE0              5       /* Enable byte mask for the comparison with register */
 546 #define BPC_offBE1              6       /* Enable byte mask for the comparison with register */
 547 #define BPC_offBE2              7       /* Enable byte mask for the comparison with register */
 548 #define BPC_offBE3              8       /* Enable byte mask for the comparison with register */
 549 #define BPC_offT                9       /* Enable breakpoint Embedded Tracer triggering operation */
 550
 551 #define BPC_mskWP               ( 0x1  << BPC_offWP )
 552 #define BPC_mskEL               ( 0x1  << BPC_offEL )
 553 #define BPC_mskS                ( 0x1  << BPC_offS )
 554 #define BPC_mskP                ( 0x1  << BPC_offP )
 555 #define BPC_mskC                ( 0x1  << BPC_offC )
 556 #define BPC_mskBE0              ( 0x1  << BPC_offBE0 )
 557 #define BPC_mskBE1              ( 0x1  << BPC_offBE1 )
 558 #define BPC_mskBE2              ( 0x1  << BPC_offBE2 )
 559 #define BPC_mskBE3              ( 0x1  << BPC_offBE3 )
 560 #define BPC_mskT                ( 0x1  << BPC_offT )
 561
 562 /******************************************************************************
 563  * dr1+(n*5): BPAn (n=0-7) (Breakpoint Address Register)
 564  *****************************************************************************/
 565
 566         /* These registers contain break point address */
 567
 568 /******************************************************************************
 569  * dr2+(n*5): BPAMn (n=0-7) (Breakpoint Address Mask Register)
 570  *****************************************************************************/
 571
 572         /* These registerd contain the address comparison mask for the BPAn register */
 573
 574 /******************************************************************************
 575  * dr3+(n*5): BPVn (n=0-7) Breakpoint Data Value Register
 576  *****************************************************************************/
 577
 578         /* The BPVn register contains the data value that will be compared with the
 579          * incoming load/store data value */
 580
 581 /******************************************************************************
 582  * dr4+(n*5): BPCIDn (n=0-7) (Breakpoint Context ID Register)
 583  *****************************************************************************/
 584 #define BPCID_offCID            0       /* CID that will be compared with a process's CID */
 585 /* bit 9:31 reserved */
 586
 587 #define BPCID_mskCID            ( 0x1FF  << BPCID_offCID )
 588
 589 /******************************************************************************
 590  * dr40: EDM_CFG (EDM Configuration Register)
 591  *****************************************************************************/
 592 #define EDM_CFG_offBC           0       /* Number of hardware breakpoint sets implemented */
 593 #define EDM_CFG_offDIMU         3       /* Debug Instruction Memory Unit exists */
 594 /* bit 4:15 reserved */
 595 #define EDM_CFG_offVER          16      /* EDM version */
 596
 597 #define EDM_CFG_mskBC           ( 0x7  << EDM_CFG_offBC )
 598 #define EDM_CFG_mskDIMU         ( 0x1  << EDM_CFG_offDIMU )
 599 #define EDM_CFG_mskVER          ( 0xFFFF  << EDM_CFG_offVER )
 600
 601 /******************************************************************************
 602  * dr41: EDMSW (EDM Status Word)
 603  *****************************************************************************/
 604 #define EDMSW_offWV             0       /* Write Valid */
 605 #define EDMSW_offRV             1       /* Read Valid */
 606 #define EDMSW_offDE             2       /* Debug exception has occurred for this core */
 607 /* bit 3:31 reserved */
 608
 609 #define EDMSW_mskWV             ( 0x1  << EDMSW_offWV )
 610 #define EDMSW_mskRV             ( 0x1  << EDMSW_offRV )
 611 #define EDMSW_mskDE             ( 0x1  << EDMSW_offDE )
 612
 613 /******************************************************************************
 614  * dr42: EDM_CTL (EDM Control Register)
 615  *****************************************************************************/
 616 /* bit 0:30 reserved */
 617 #define EDM_CTL_offV3_EDM_MODE  6       /* EDM compatibility control bit */
 618 #define EDM_CTL_offDEH_SEL      31      /* Controls where debug exception is directed to */
 619
 620 #define EDM_CTL_mskV3_EDM_MODE  ( 0x1 << EDM_CTL_offV3_EDM_MODE )
 621 #define EDM_CTL_mskDEH_SEL      ( 0x1 << EDM_CTL_offDEH_SEL )
 622
 623 /******************************************************************************
 624  * dr43: EDM_DTR (EDM Data Transfer Register)
 625  *****************************************************************************/
 626
 627         /* This is used to exchange data between the embedded EDM logic
 628          * and the processor core */
 629
 630 /******************************************************************************
 631  * dr44: BPMTC (Breakpoint Match Trigger Counter Register)
 632  *****************************************************************************/
 633 #define BPMTC_offBPMTC          0       /* Breakpoint match trigger counter value */
 634 /* bit 16:31 reserved */
 635
 636 #define BPMTC_mskBPMTC          ( 0xFFFF  << BPMTC_offBPMTC )
 637
 638 /******************************************************************************
 639  * dr45: DIMBR (Debug Instruction Memory Base Register)
 640  *****************************************************************************/
 641 /* bit 0:11 reserved */
 642 #define DIMBR_offDIMB           12      /* Base address of the Debug Instruction Memory (DIM) */
 643 #define DIMBR_mskDIMB           ( 0xFFFFF  << DIMBR_offDIMB )
 644
 645 /******************************************************************************
 646  * dr46: TECR0(Trigger Event Control register 0)
 647  * dr47: TECR1 (Trigger Event Control register 1)
 648  *****************************************************************************/
 649 #define TECR_offBP              0       /* Controld which BP is used as a trigger source */
 650 #define TECR_offNMI             8       /* Use NMI as a trigger source */
 651 #define TECR_offHWINT           9       /* Corresponding interrupt is used as a trigger source */
 652 #define TECR_offEVIC            15      /* Enable HWINT as a trigger source in EVIC mode */
 653 #define TECR_offSYS             16      /* Enable SYSCALL instruction as a trigger source */
 654 #define TECR_offDBG             17      /* Enable debug exception as a trigger source */
 655 #define TECR_offMRE             18      /* Enable MMU related exception as a trigger source */
 656 #define TECR_offE               19      /* An exception is used as a trigger source */
 657 /* bit 20:30 reserved */
 658 #define TECR_offL               31      /* Link/Cascade TECR0 trigger event to TECR1 trigger event */
 659
 660 #define TECR_mskBP              ( 0xFF  << TECR_offBP )
 661 #define TECR_mskNMI             ( 0x1  << TECR_offBNMI )
 662 #define TECR_mskHWINT           ( 0x3F  << TECR_offBHWINT )
 663 #define TECR_mskEVIC            ( 0x1  << TECR_offBEVIC )
 664 #define TECR_mskSYS             ( 0x1  << TECR_offBSYS )
 665 #define TECR_mskDBG             ( 0x1  << TECR_offBDBG )
 666 #define TECR_mskMRE             ( 0x1  << TECR_offBMRE )
 667 #define TECR_mskE               ( 0x1  << TECR_offE )
 668 #define TECR_mskL               ( 0x1  << TECR_offL )
 669
 670 /******************************************************************************
 671  * pfr0-2: PFMC0-2 (Performance Counter Register 0-2)
 672  *****************************************************************************/
 673
 674         /* These registers contains performance event count */
 675
 676 /******************************************************************************
 677  * pfr3: PFM_CTL (Performance Counter Control Register)
 678  *****************************************************************************/
 679 #define PFM_CTL_offEN0          0       /* Enable PFMC0 */
 680 #define PFM_CTL_offEN1          1       /* Enable PFMC1 */
 681 #define PFM_CTL_offEN2          2       /* Enable PFMC2 */
 682 #define PFM_CTL_offIE0          3       /* Enable interrupt for PFMC0 */
 683 #define PFM_CTL_offIE1          4       /* Enable interrupt for PFMC1 */
 684 #define PFM_CTL_offIE2          5       /* Enable interrupt for PFMC2 */
 685 #define PFM_CTL_offOVF0         6       /* Overflow bit of PFMC0 */
 686 #define PFM_CTL_offOVF1         7       /* Overflow bit of PFMC1 */
 687 #define PFM_CTL_offOVF2         8       /* Overflow bit of PFMC2 */
 688 #define PFM_CTL_offKS0          9       /* Enable superuser mode event counting for PFMC0 */
 689 #define PFM_CTL_offKS1          10      /* Enable superuser mode event counting for PFMC1 */
 690 #define PFM_CTL_offKS2          11      /* Enable superuser mode event counting for PFMC2 */
 691 #define PFM_CTL_offKU0          12      /* Enable user mode event counting for PFMC0 */
 692 #define PFM_CTL_offKU1          13      /* Enable user mode event counting for PFMC1 */
 693 #define PFM_CTL_offKU2          14      /* Enable user mode event counting for PFMC2 */
 694 #define PFM_CTL_offSEL0         15      /* The event selection for PFMC0 */
 695 #define PFM_CTL_offSEL1         21      /* The event selection for PFMC1 */
 696 #define PFM_CTL_offSEL2         27      /* The event selection for PFMC2 */
 697 /* bit 28:31 reserved */
 698
 699 #define PFM_CTL_mskEN0          ( 0x01  << PFM_CTL_offEN0 )
 700 #define PFM_CTL_mskEN1          ( 0x01  << PFM_CTL_offEN1 )
 701 #define PFM_CTL_mskEN2          ( 0x01  << PFM_CTL_offEN2 )
 702 #define PFM_CTL_mskIE0          ( 0x01  << PFM_CTL_offIE0 )
 703 #define PFM_CTL_mskIE1          ( 0x01  << PFM_CTL_offIE1 )
 704 #define PFM_CTL_mskIE2          ( 0x01  << PFM_CTL_offIE2 )
 705 #define PFM_CTL_mskOVF0         ( 0x01  << PFM_CTL_offOVF0 )
 706 #define PFM_CTL_mskOVF1         ( 0x01  << PFM_CTL_offOVF1 )
 707 #define PFM_CTL_mskOVF2         ( 0x01  << PFM_CTL_offOVF2 )
 708 #define PFM_CTL_mskKS0          ( 0x01  << PFM_CTL_offKS0 )
 709 #define PFM_CTL_mskKS1          ( 0x01  << PFM_CTL_offKS1 )
 710 #define PFM_CTL_mskKS2          ( 0x01  << PFM_CTL_offKS2 )
 711 #define PFM_CTL_mskKU0          ( 0x01  << PFM_CTL_offKU0 )
 712 #define PFM_CTL_mskKU1          ( 0x01  << PFM_CTL_offKU1 )
 713 #define PFM_CTL_mskKU2          ( 0x01  << PFM_CTL_offKU2 )
 714 #define PFM_CTL_mskSEL0         ( 0x01  << PFM_CTL_offSEL0 )
 715 #define PFM_CTL_mskSEL1         ( 0x3F  << PFM_CTL_offSEL1 )
 716 #define PFM_CTL_mskSEL2         ( 0x3F  << PFM_CTL_offSEL2 )
 717
 718 /******************************************************************************
 719  * SDZ_CTL (Structure Downsizing Control Register)
 720  *****************************************************************************/
 721 #define SDZ_CTL_offICDZ         0       /* I-cache downsizing control */
 722 #define SDZ_CTL_offDCDZ         3       /* D-cache downsizing control */
 723 #define SDZ_CTL_offMTBDZ        6       /* MTLB downsizing control */
 724 #define SDZ_CTL_offBTBDZ        9       /* Branch Target Table downsizing control */
 725 /* bit 12:31 reserved */
 726 #define SDZ_CTL_mskICDZ         ( 0x07  << SDZ_CTL_offICDZ )
 727 #define SDZ_CTL_mskDCDZ         ( 0x07  << SDZ_CTL_offDCDZ )
 728 #define SDZ_CTL_mskMTBDZ        ( 0x07  << SDZ_CTL_offMTBDZ )
 729 #define SDZ_CTL_mskBTBDZ        ( 0x07  << SDZ_CTL_offBTBDZ )
 730
 731 /******************************************************************************
 732  * N13MISC_CTL (N13 Miscellaneous Control Register)
 733  *****************************************************************************/
 734 #define N13MISC_CTL_offBTB      0       /* Disable Branch Target Buffer */
 735 #define N13MISC_CTL_offRTP      1       /* Disable Return Target Predictor */
 736 #define N13MISC_CTL_offPTEPF    2       /* Disable HPTWK L2 PTE pefetch */
 737 #define N13MISC_CTL_offSP_SHADOW_EN     4       /* Enable shadow stack pointers */
 738 /* bit 6, 9:31 reserved */
 739
 740 #define N13MISC_CTL_makBTB      ( 0x1  << N13MISC_CTL_offBTB )
 741 #define N13MISC_CTL_makRTP      ( 0x1  << N13MISC_CTL_offRTP )
 742 #define N13MISC_CTL_makPTEPF    ( 0x1  << N13MISC_CTL_offPTEPF )
 743 #define N13MISC_CTL_makSP_SHADOW_EN     ( 0x1  << N13MISC_CTL_offSP_SHADOW_EN )
 744
 745 #define MISC_init       (N13MISC_CTL_makBTB|N13MISC_CTL_makRTP|N13MISC_CTL_makSP_SHADOW_EN)
 746
 747 /******************************************************************************
 748  * PRUSR_ACC_CTL (Privileged Resource User Access Control Registers)
 749  *****************************************************************************/
 750 #define PRUSR_ACC_CTL_offDMA_EN 0       /* Allow user mode access of DMA registers */
 751 #define PRUSR_ACC_CTL_offPFM_EN 1       /* Allow user mode access of PFM registers */
 752
 753 #define PRUSR_ACC_CTL_mskDMA_EN ( 0x1  << PRUSR_ACC_CTL_offDMA_EN )
 754 #define PRUSR_ACC_CTL_mskPFM_EN ( 0x1  << PRUSR_ACC_CTL_offPFM_EN )
 755
 756 /******************************************************************************
 757  * dmar0: DMA_CFG (DMA Configuration Register)
 758  *****************************************************************************/
 759 #define DMA_CFG_offNCHN         0       /* The number of DMA channels implemented */
 760 #define DMA_CFG_offUNEA         2       /* Un-aligned External Address transfer feature */
 761 #define DMA_CFG_off2DET         3       /* 2-D Element Transfer feature */
 762 /* bit 4:15 reserved */
 763 #define DMA_CFG_offVER          16      /* DMA architecture and implementation version */
 764
 765 #define DMA_CFG_mskNCHN         ( 0x3  << DMA_CFG_offNCHN )
 766 #define DMA_CFG_mskUNEA         ( 0x1  << DMA_CFG_offUNEA )
 767 #define DMA_CFG_msk2DET         ( 0x1  << DMA_CFG_off2DET )
 768 #define DMA_CFG_mskVER          ( 0xFFFF  << DMA_CFG_offVER )
 769
 770 /******************************************************************************
 771  * dmar1: DMA_GCSW (DMA Global Control and Status Word Register)
 772  *****************************************************************************/
 773 #define DMA_GCSW_offC0STAT      0       /* DMA channel 0 state */
 774 #define DMA_GCSW_offC1STAT      3       /* DMA channel 1 state */
 775 /* bit 6:11 reserved */
 776 #define DMA_GCSW_offC0INT       12      /* DMA channel 0 generate interrupt */
 777 #define DMA_GCSW_offC1INT       13      /* DMA channel 1 generate interrupt */
 778 /* bit 14:30 reserved */
 779 #define DMA_GCSW_offEN          31      /* Enable DMA engine */
 780
 781 #define DMA_GCSW_mskC0STAT      ( 0x7  << DMA_GCSW_offC0STAT )
 782 #define DMA_GCSW_mskC1STAT      ( 0x7  << DMA_GCSW_offC1STAT )
 783 #define DMA_GCSW_mskC0INT       ( 0x1  << DMA_GCSW_offC0INT )
 784 #define DMA_GCSW_mskC1INT       ( 0x1  << DMA_GCSW_offC1INT )
 785 #define DMA_GCSW_mskEN          ( 0x1  << DMA_GCSW_offEN )
 786
 787 /******************************************************************************
 788  * dmar2: DMA_CHNSEL (DMA Channel Selection Register)
 789  *****************************************************************************/
 790 #define DMA_CHNSEL_offCHAN      0       /* Selected channel number */
 791 /* bit 2:31 reserved */
 792
 793 #define DMA_CHNSEL_mskCHAN      ( 0x3  << DMA_CHNSEL_offCHAN )
 794
 795 /******************************************************************************
 796  * dmar3: DMA_ACT (DMA Action Register)
 797  *****************************************************************************/
 798 #define DMA_ACT_offACMD         0       /* DMA Action Command */
 799 /* bit 2:31 reserved */
 800 #define DMA_ACT_mskACMD         ( 0x3  << DMA_ACT_offACMD )
 801
 802 /******************************************************************************
 803  * dmar4: DMA_SETUP (DMA Setup Register)
 804  *****************************************************************************/
 805 #define DMA_SETUP_offLM         0       /* Local Memory Selection */
 806 #define DMA_SETUP_offTDIR       1       /* Transfer Direction */
 807 #define DMA_SETUP_offTES        2       /* Transfer Element Size */
 808 #define DMA_SETUP_offESTR       4       /* External memory transfer Stride */
 809 #define DMA_SETUP_offCIE        16      /* Interrupt Enable on Completion */
 810 #define DMA_SETUP_offSIE        17      /* Interrupt Enable on explicit Stop */
 811 #define DMA_SETUP_offEIE        18      /* Interrupt Enable on Error */
 812 #define DMA_SETUP_offUE         19      /* Enable the Un-aligned External Address */
 813 #define DMA_SETUP_off2DE        20      /* Enable the 2-D External Transfer */
 814 #define DMA_SETUP_offCOA        21      /* Transfer Coalescable */
 815 /* bit 22:31 reserved */
 816
 817 #define DMA_SETUP_mskLM         ( 0x1  << DMA_SETUP_offLM )
 818 #define DMA_SETUP_mskTDIR       ( 0x1  << DMA_SETUP_offTDIR )
 819 #define DMA_SETUP_mskTES        ( 0x3  << DMA_SETUP_offTES )
 820 #define DMA_SETUP_mskESTR       ( 0xFFF  << DMA_SETUP_offESTR )
 821 #define DMA_SETUP_mskCIE        ( 0x1  << DMA_SETUP_offCIE )
 822 #define DMA_SETUP_mskSIE        ( 0x1  << DMA_SETUP_offSIE )
 823 #define DMA_SETUP_mskEIE        ( 0x1  << DMA_SETUP_offEIE )
 824 #define DMA_SETUP_mskUE         ( 0x1  << DMA_SETUP_offUE )
 825 #define DMA_SETUP_msk2DE        ( 0x1  << DMA_SETUP_off2DE )
 826 #define DMA_SETUP_mskCOA        ( 0x1  << DMA_SETUP_offCOA )
 827
 828 /******************************************************************************
 829  * dmar5: DMA_ISADDR (DMA Internal Start Address Register)
 830  *****************************************************************************/
 831 #define DMA_ISADDR_offISADDR    0       /* Internal Start Address */
 832 /* bit 20:31 reserved */
 833 #define DMA_ISADDR_mskISADDR    ( 0xFFFFF  << DMA_ISADDR_offISADDR )
 834
 835 /******************************************************************************
 836  * dmar6: DMA_ESADDR (DMA External Start Address Register)
 837  *****************************************************************************/
 838 /* This register holds External Start Address */
 839
 840 /******************************************************************************
 841  * dmar7: DMA_TCNT (DMA Transfer Element Count Register)
 842  *****************************************************************************/
 843 #define DMA_TCNT_offTCNT        0       /* DMA transfer element count */
 844 /* bit 18:31 reserved */
 845 #define DMA_TCNT_mskTCNT        ( 0x3FFFF  << DMA_TCNT_offTCNT )
 846
 847 /******************************************************************************
 848  * dmar8: DMA_STATUS (DMA Status Register)
 849  *****************************************************************************/
 850 #define DMA_STATUS_offSTAT      0       /* DMA channel state */
 851 #define DMA_STATUS_offSTUNA     3       /* Un-aligned error on External Stride value */
 852 #define DMA_STATUS_offDERR      4       /* DMA Transfer Disruption Error */
 853 #define DMA_STATUS_offEUNA      5       /* Un-aligned error on the External address */
 854 #define DMA_STATUS_offIUNA      6       /* Un-aligned error on the Internal address */
 855 #define DMA_STATUS_offIOOR      7       /* Out-Of-Range error on the Internal address */
 856 #define DMA_STATUS_offEBUS      8       /* Bus Error on an External DMA transfer */
 857 #define DMA_STATUS_offESUP      9       /* DMA setup error */
 858 /* bit 10:31 reserved */
 859
 860 #define DMA_STATUS_mskSTAT      ( 0x7  << DMA_STATUS_offSTAT )
 861 #define DMA_STATUS_mskSTUNA     ( 0x1  << DMDMA_STATUS_offSTUNA )
 862 #define DMA_STATUS_mskDERR      ( 0x1  << DMDMA_STATUS_offDERR )
 863 #define DMA_STATUS_mskEUNA      ( 0x1  << DMDMA_STATUS_offEUNA )
 864 #define DMA_STATUS_mskIUNA      ( 0x1  << DMDMA_STATUS_offIUNA )
 865 #define DMA_STATUS_mskIOOR      ( 0x1  << DMDMA_STATUS_offIOOR )
 866 #define DMA_STATUS_mskEBUS      ( 0x1  << DMDMA_STATUS_offEBUS )
 867 #define DMA_STATUS_mskESUP      ( 0x1  << DMDMA_STATUS_offESUP )
 868
 869 /******************************************************************************
 870  * dmar9: DMA_2DSET (DMA 2D Setup Register)
 871  *****************************************************************************/
 872 #define DMA_2DSET_offWECNT      0       /* The Width Element Count for a 2-D region */
 873 #define DMA_2DSET_offHTSTR      16      /* The Height Stride for a 2-D region */
 874
 875 #define DMA_2DSET_mskHTSTR      ( 0xFFFF  << DMA_2DSET_offHTSTR )
 876 #define DMA_2DSET_mskWECNT      ( 0xFFFF  << DMA_2DSET_offWECNT )
 877
 878 /******************************************************************************
 879  * dmar10: DMA_2DSCTL (DMA 2D Startup Control Register)
 880  *****************************************************************************/
 881 #define DMA_2DSCTL_offSTWECNT   0       /* Startup Width Element Count for a 2-D region */
 882 /* bit 16:31 reserved */
 883
 884 #define DMA_2DSCTL_mskSTWECNT   ( 0xFFFF  << DMA_2DSCTL_offSTWECNT )
 885
 886 /******************************************************************************
 887  * fpcsr: FPCSR (Floating-Point Control Status Register)
 888  *****************************************************************************/
 889 #define FPCSR_offRM             0
 890 #define FPCSR_offIVO            2
 891 #define FPCSR_offDBZ            3
 892 #define FPCSR_offOVF            4
 893 #define FPCSR_offUDF            5
 894 #define FPCSR_offIEX            6
 895 #define FPCSR_offIVOE           7
 896 #define FPCSR_offDBZE           8
 897 #define FPCSR_offOVFE           9
 898 #define FPCSR_offUDFE           10
 899 #define FPCSR_offIEXE           11
 900 #define FPCSR_offDNZ            12
 901 #define FPCSR_offIVOT           13
 902 #define FPCSR_offDBZT           14
 903 #define FPCSR_offOVFT           15
 904 #define FPCSR_offUDFT           16
 905 #define FPCSR_offIEXT           17
 906 #define FPCSR_offDNIT           18
 907 #define FPCSR_offRIT            19
 908
 909 #define FPCSR_mskRM             ( 0x3  << FPCSR_offRM )
 910 #define FPCSR_mskIVO            ( 0x1  << FPCSR_offIVO )
 911 #define FPCSR_mskDBZ            ( 0x1  << FPCSR_offDBZ )
 912 #define FPCSR_mskOVF            ( 0x1  << FPCSR_offOVF )
 913 #define FPCSR_mskUDF            ( 0x1  << FPCSR_offUDF )
 914 #define FPCSR_mskIEX            ( 0x1  << FPCSR_offIEX )
 915 #define FPCSR_mskIVOE           ( 0x1  << FPCSR_offIVOE )
 916 #define FPCSR_mskDBZE           ( 0x1  << FPCSR_offDBZE )
 917 #define FPCSR_mskOVFE           ( 0x1  << FPCSR_offOVFE )
 918 #define FPCSR_mskUDFE           ( 0x1  << FPCSR_offUDFE )
 919 #define FPCSR_mskIEXE           ( 0x1  << FPCSR_offIEXE )
 920 #define FPCSR_mskDNZ            ( 0x1  << FPCSR_offDNZ )
 921 #define FPCSR_mskIVOT           ( 0x1  << FPCSR_offIVOT )
 922 #define FPCSR_mskDBZT           ( 0x1  << FPCSR_offDBZT )
 923 #define FPCSR_mskOVFT           ( 0x1  << FPCSR_offOVFT )
 924 #define FPCSR_mskUDFT           ( 0x1  << FPCSR_offUDFT )
 925 #define FPCSR_mskIEXT           ( 0x1  << FPCSR_offIEXT )
 926 #define FPCSR_mskDNIT           ( 0x1  << FPCSR_offDNIT )
 927 #define FPCSR_mskRIT            ( 0x1  << FPCSR_offRIT )
 928 #define FPCSR_mskALL            (FPCSR_mskIVO | FPCSR_mskDBZ | FPCSR_mskOVF | FPCSR_mskUDF | FPCSR_mskIEX)
 929 #define FPCSR_mskALLE           (FPCSR_mskIVOE | FPCSR_mskDBZE | FPCSR_mskOVFE | FPCSR_mskUDFE | FPCSR_mskIEXE)
 930 #define FPCSR_mskALLT           (FPCSR_mskIVOT | FPCSR_mskDBZT | FPCSR_mskOVFT | FPCSR_mskUDFT | FPCSR_mskIEXT |FPCSR_mskDNIT | FPCSR_mskRIT)
 931
 932 /******************************************************************************
 933  * fpcfg: FPCFG (Floating-Point Configuration Register)
 934  *****************************************************************************/
 935 #define FPCFG_offSP             0
 936 #define FPCFG_offDP             1
 937 #define FPCFG_offFREG           2
 938 #define FPCFG_offFMA            4
 939 #define FPCFG_offIMVER          22
 940 #define FPCFG_offAVER           27
 941
 942 #define FPCFG_mskSP             ( 0x1  << FPCFG_offSP )
 943 #define FPCFG_mskDP             ( 0x1  << FPCFG_offDP )
 944 #define FPCFG_mskFREG           ( 0x3  << FPCFG_offFREG )
 945 #define FPCFG_mskFMA            ( 0x1  << FPCFG_offFMA )
 946 #define FPCFG_mskIMVER          ( 0x1F  << FPCFG_offIMVER )
 947 #define FPCFG_mskAVER           ( 0x1F  << FPCFG_offAVER )
 948
 949 /******************************************************************************
 950  * fucpr: FUCOP_CTL (FPU and Coprocessor Enable Control Register)
 951  *****************************************************************************/
 952 #define FUCOP_CTL_offCP0EN      0
 953 #define FUCOP_CTL_offCP1EN      1
 954 #define FUCOP_CTL_offCP2EN      2
 955 #define FUCOP_CTL_offCP3EN      3
 956 #define FUCOP_CTL_offAUEN       31
 957
 958 #define FUCOP_CTL_mskCP0EN      ( 0x1  << FUCOP_CTL_offCP0EN )
 959 #define FUCOP_CTL_mskCP1EN      ( 0x1  << FUCOP_CTL_offCP1EN )
 960 #define FUCOP_CTL_mskCP2EN      ( 0x1  << FUCOP_CTL_offCP2EN )
 961 #define FUCOP_CTL_mskCP3EN      ( 0x1  << FUCOP_CTL_offCP3EN )
 962 #define FUCOP_CTL_mskAUEN       ( 0x1  << FUCOP_CTL_offAUEN )
 963
 964 #endif /* __NDS32_BITFIELD_H__ */