1 /* SPDX-License-Identifier: GPL-2.0 */
3 * S390 low-level entry points.
5 * Copyright IBM Corp. 1999, 2012
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
7 * Hartmut Penner (hp@de.ibm.com),
8 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
9 * Heiko Carstens <heiko.carstens@de.ibm.com>
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/alternative-asm.h>
15 #include <asm/processor.h>
16 #include <asm/cache.h>
17 #include <asm/ctl_reg.h>
18 #include <asm/dwarf.h>
19 #include <asm/errno.h>
20 #include <asm/ptrace.h>
21 #include <asm/thread_info.h>
22 #include <asm/asm-offsets.h>
23 #include <asm/unistd.h>
27 #include <asm/vx-insn.h>
28 #include <asm/setup.h>
30 #include <asm/export.h>
31 #include <asm/nospec-insn.h>
34 __PT_R1 = __PT_GPRS + 8
35 __PT_R2 = __PT_GPRS + 16
36 __PT_R3 = __PT_GPRS + 24
37 __PT_R4 = __PT_GPRS + 32
38 __PT_R5 = __PT_GPRS + 40
39 __PT_R6 = __PT_GPRS + 48
40 __PT_R7 = __PT_GPRS + 56
41 __PT_R8 = __PT_GPRS + 64
42 __PT_R9 = __PT_GPRS + 72
43 __PT_R10 = __PT_GPRS + 80
44 __PT_R11 = __PT_GPRS + 88
45 __PT_R12 = __PT_GPRS + 96
46 __PT_R13 = __PT_GPRS + 104
47 __PT_R14 = __PT_GPRS + 112
48 __PT_R15 = __PT_GPRS + 120
50 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
51 STACK_SIZE = 1 << STACK_SHIFT
52 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
54 _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
55 _TIF_UPROBE | _TIF_GUARDED_STORAGE | _TIF_PATCH_PENDING)
56 _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
57 _TIF_SYSCALL_TRACEPOINT)
58 _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
59 _CIF_ASCE_SECONDARY | _CIF_FPU)
60 _PIF_WORK = (_PIF_PER_TRAP | _PIF_SYSCALL_RESTART)
62 _LPP_OFFSET = __LC_LPP
64 #define BASED(name) name-cleanup_critical(%r13)
67 #ifdef CONFIG_TRACE_IRQFLAGS
69 brasl %r14,trace_hardirqs_on_caller
74 #ifdef CONFIG_TRACE_IRQFLAGS
76 brasl %r14,trace_hardirqs_off_caller
80 .macro LOCKDEP_SYS_EXIT
82 tm __PT_PSW+1(%r11),0x01 # returning to user ?
84 brasl %r14,lockdep_sys_exit
88 .macro CHECK_STACK savearea
89 #ifdef CONFIG_CHECK_STACK
90 tml %r15,STACK_SIZE - CONFIG_STACK_GUARD
96 .macro CHECK_VMAP_STACK savearea,oklabel
97 #ifdef CONFIG_VMAP_STACK
99 nill %r14,0x10000 - STACK_SIZE
101 clg %r14,__LC_KERNEL_STACK
103 clg %r14,__LC_ASYNC_STACK
105 clg %r14,__LC_NODAT_STACK
107 clg %r14,__LC_RESTART_STACK
116 .macro SWITCH_ASYNC savearea,timer
117 tmhh %r8,0x0001 # interrupting from user ?
120 slg %r14,BASED(.Lcritical_start)
121 clg %r14,BASED(.Lcritical_length)
123 lghi %r11,\savearea # inside critical section, do cleanup
124 brasl %r14,cleanup_critical
125 tmhh %r8,0x0001 # retest problem state after cleanup
127 0: lg %r14,__LC_ASYNC_STACK # are we already on the target stack?
129 srag %r14,%r14,STACK_SHIFT
131 CHECK_STACK \savearea
132 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
134 1: UPDATE_VTIME %r14,%r15,\timer
135 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
136 2: lg %r15,__LC_ASYNC_STACK # load async stack
137 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
140 .macro UPDATE_VTIME w1,w2,enter_timer
141 lg \w1,__LC_EXIT_TIMER
142 lg \w2,__LC_LAST_UPDATE_TIMER
144 slg \w2,__LC_EXIT_TIMER
145 alg \w1,__LC_USER_TIMER
146 alg \w2,__LC_SYSTEM_TIMER
147 stg \w1,__LC_USER_TIMER
148 stg \w2,__LC_SYSTEM_TIMER
149 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
153 stg %r8,__LC_RETURN_PSW
154 ni __LC_RETURN_PSW,0xbf
159 #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
160 .insn s,0xb27c0000,\savearea # store clock fast
162 .insn s,0xb2050000,\savearea # store clock
167 * The TSTMSK macro generates a test-under-mask instruction by
168 * calculating the memory offset for the specified mask value.
169 * Mask value can be any constant. The macro shifts the mask
170 * value to calculate the memory offset for the test-under-mask
173 .macro TSTMSK addr, mask, size=8, bytepos=0
174 .if (\bytepos < \size) && (\mask >> 8)
176 .error "Mask exceeds byte boundary"
178 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
182 .error "Mask must not be zero"
184 off = \size - \bytepos - 1
189 ALTERNATIVE "", ".long 0xb2e8c000", 82
193 ALTERNATIVE "", ".long 0xb2e8d000", 82
196 .macro BPENTER tif_ptr,tif_mask
197 ALTERNATIVE "TSTMSK \tif_ptr,\tif_mask; jz .+8; .long 0xb2e8d000", \
201 .macro BPEXIT tif_ptr,tif_mask
202 TSTMSK \tif_ptr,\tif_mask
203 ALTERNATIVE "jz .+8; .long 0xb2e8c000", \
204 "jnz .+8; .long 0xb2e8d000", 82
209 GEN_BR_THUNK %r14,%r11
211 .section .kprobes.text, "ax"
214 * This nop exists only in order to avoid that __switch_to starts at
215 * the beginning of the kprobes text section. In that case we would
216 * have several symbols at the same address. E.g. objdump would take
217 * an arbitrary symbol name when disassembling this code.
218 * With the added nop in between the __switch_to symbol is unique
229 * Scheduler resume function, called by switch_to
230 * gpr2 = (task_struct *) prev
231 * gpr3 = (task_struct *) next
236 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
237 lghi %r4,__TASK_stack
238 lghi %r1,__TASK_thread
239 lg %r5,0(%r4,%r3) # start of kernel stack of next
240 stg %r15,__THREAD_ksp(%r1,%r2) # store kernel stack of prev
242 aghi %r15,STACK_INIT # end of kernel stack of next
243 stg %r3,__LC_CURRENT # store task struct of next
244 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
245 lg %r15,__THREAD_ksp(%r1,%r3) # load kernel stack of next
247 mvc __LC_CURRENT_PID(4,%r0),0(%r3) # store pid of next
248 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
249 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
254 #if IS_ENABLED(CONFIG_KVM)
256 * sie64a calling convention:
257 * %r2 pointer to sie control block
258 * %r3 guest register save area
261 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
263 stg %r2,__SF_SIE_CONTROL(%r15) # save control block pointer
264 stg %r3,__SF_SIE_SAVEAREA(%r15) # save guest register save area
265 xc __SF_SIE_REASON(8,%r15),__SF_SIE_REASON(%r15) # reason code = 0
266 mvc __SF_SIE_FLAGS(8,%r15),__TI_flags(%r12) # copy thread flags
267 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
268 jno .Lsie_load_guest_gprs
269 brasl %r14,load_fpu_regs # load guest fp/vx regs
270 .Lsie_load_guest_gprs:
271 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
272 lg %r14,__LC_GMAP # get gmap pointer
275 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
277 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
278 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
279 tm __SIE_PROG20+3(%r14),3 # last exit...
281 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
282 jo .Lsie_skip # exit if fp/vx regs changed
283 BPEXIT __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
288 BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
290 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
291 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
293 # some program checks are suppressing. C code (e.g. do_protection_exception)
294 # will rewind the PSW by the ILC, which is often 4 bytes in case of SIE. There
295 # are some corner cases (e.g. runtime instrumentation) where ILC is unpredictable.
296 # Other instructions between sie64a and .Lsie_done should not cause program
297 # interrupts. So lets use 3 nops as a landing pad for all possible rewinds.
298 # See also .Lcleanup_sie
307 lg %r14,__SF_SIE_SAVEAREA(%r15) # load guest register save area
308 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
309 xgr %r0,%r0 # clear guest registers to
310 xgr %r1,%r1 # prevent speculative use
315 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
316 lg %r2,__SF_SIE_REASON(%r15) # return exit reason code
320 stg %r14,__SF_SIE_REASON(%r15) # set exit reason code
323 EX_TABLE(.Lrewind_pad6,.Lsie_fault)
324 EX_TABLE(.Lrewind_pad4,.Lsie_fault)
325 EX_TABLE(.Lrewind_pad2,.Lsie_fault)
326 EX_TABLE(sie_exit,.Lsie_fault)
327 EXPORT_SYMBOL(sie64a)
328 EXPORT_SYMBOL(sie_exit)
332 * SVC interrupt handler routine. System calls are synchronous events and
333 * are executed with interrupts enabled.
337 stpt __LC_SYNC_ENTER_TIMER
339 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
342 lghi %r13,__TASK_thread
343 lghi %r14,_PIF_SYSCALL
345 lg %r15,__LC_KERNEL_STACK
346 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
348 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
349 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
350 stmg %r0,%r7,__PT_R0(%r11)
351 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
352 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
353 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
354 stg %r14,__PT_FLAGS(%r11)
356 # clear user controlled register to prevent speculative use
358 # load address of system call table
359 lg %r10,__THREAD_sysc_table(%r13,%r12)
360 llgh %r8,__PT_INT_CODE+2(%r11)
361 slag %r8,%r8,2 # shift and test for svc 0
363 # svc 0: system call number in %r1
364 llgfr %r1,%r1 # clear high word in r1
367 sth %r1,__PT_INT_CODE+2(%r11)
370 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
371 stg %r2,__PT_ORIG_GPR2(%r11)
372 stg %r7,STACK_FRAME_OVERHEAD(%r15)
373 lgf %r9,0(%r8,%r10) # get system call add.
374 TSTMSK __TI_flags(%r12),_TIF_TRACE
376 BASR_EX %r14,%r9 # call sys_xxxx
377 stg %r2,__PT_R2(%r11) # store return value
380 #ifdef CONFIG_DEBUG_RSEQ
382 brasl %r14,rseq_syscall
386 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
388 TSTMSK __TI_flags(%r12),_TIF_WORK
389 jnz .Lsysc_work # check for work
390 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
392 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
394 lg %r14,__LC_VDSO_PER_CPU
395 lmg %r0,%r10,__PT_R0(%r11)
396 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
399 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
400 lmg %r11,%r15,__PT_R11(%r11)
401 lpswe __LC_RETURN_PSW
405 # One of the work bits is on. Find out which one.
408 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
409 jo .Lsysc_mcck_pending
410 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
412 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
413 jo .Lsysc_syscall_restart
414 #ifdef CONFIG_UPROBES
415 TSTMSK __TI_flags(%r12),_TIF_UPROBE
416 jo .Lsysc_uprobe_notify
418 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
419 jo .Lsysc_guarded_storage
420 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
422 #ifdef CONFIG_LIVEPATCH
423 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
424 jo .Lsysc_patch_pending # handle live patching just before
425 # signals and possible syscall restart
427 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL_RESTART
428 jo .Lsysc_syscall_restart
429 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
431 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
432 jo .Lsysc_notify_resume
433 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
435 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
437 j .Lsysc_return # beware of critical section cleanup
440 # _TIF_NEED_RESCHED is set, call schedule
443 larl %r14,.Lsysc_return
447 # _CIF_MCCK_PENDING is set, call handler
450 larl %r14,.Lsysc_return
451 jg s390_handle_mcck # TIF bit will be cleared by handler
454 # _CIF_ASCE_PRIMARY and/or _CIF_ASCE_SECONDARY set, load user space asce
457 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
458 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
459 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
461 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
462 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
463 jnz .Lsysc_set_fs_fixup
464 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
465 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
469 larl %r14,.Lsysc_return
473 # CIF_FPU is set, restore floating-point controls and floating-point registers.
476 larl %r14,.Lsysc_return
480 # _TIF_SIGPENDING is set, call do_signal
483 lgr %r2,%r11 # pass pointer to pt_regs
485 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
488 lghi %r13,__TASK_thread
489 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
490 lghi %r1,0 # svc 0 returns -ENOSYS
494 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
496 .Lsysc_notify_resume:
497 lgr %r2,%r11 # pass pointer to pt_regs
498 larl %r14,.Lsysc_return
502 # _TIF_UPROBE is set, call uprobe_notify_resume
504 #ifdef CONFIG_UPROBES
505 .Lsysc_uprobe_notify:
506 lgr %r2,%r11 # pass pointer to pt_regs
507 larl %r14,.Lsysc_return
508 jg uprobe_notify_resume
512 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
514 .Lsysc_guarded_storage:
515 lgr %r2,%r11 # pass pointer to pt_regs
516 larl %r14,.Lsysc_return
519 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
521 #ifdef CONFIG_LIVEPATCH
522 .Lsysc_patch_pending:
523 lg %r2,__LC_CURRENT # pass pointer to task struct
524 larl %r14,.Lsysc_return
525 jg klp_update_patch_state
529 # _PIF_PER_TRAP is set, call do_per_trap
532 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
533 lgr %r2,%r11 # pass pointer to pt_regs
534 larl %r14,.Lsysc_return
538 # _PIF_SYSCALL_RESTART is set, repeat the current system call
540 .Lsysc_syscall_restart:
541 ni __PT_FLAGS+7(%r11),255-_PIF_SYSCALL_RESTART
542 lmg %r1,%r7,__PT_R1(%r11) # load svc arguments
543 lg %r2,__PT_ORIG_GPR2(%r11)
547 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
548 # and after the system call
551 lgr %r2,%r11 # pass pointer to pt_regs
553 llgh %r0,__PT_INT_CODE+2(%r11)
554 stg %r0,__PT_R2(%r11)
555 brasl %r14,do_syscall_trace_enter
562 lmg %r3,%r7,__PT_R3(%r11)
563 stg %r7,STACK_FRAME_OVERHEAD(%r15)
564 lg %r2,__PT_ORIG_GPR2(%r11)
565 BASR_EX %r14,%r9 # call sys_xxx
566 stg %r2,__PT_R2(%r11) # store return value
568 TSTMSK __TI_flags(%r12),_TIF_TRACE
570 lgr %r2,%r11 # pass pointer to pt_regs
571 larl %r14,.Lsysc_return
572 jg do_syscall_trace_exit
575 # a new process exits the kernel with ret_from_fork
578 la %r11,STACK_FRAME_OVERHEAD(%r15)
580 brasl %r14,schedule_tail
582 ssm __LC_SVC_NEW_PSW # reenable interrupts
583 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
585 # it's a kernel thread
586 lmg %r9,%r10,__PT_R9(%r11) # load gprs
587 ENTRY(kernel_thread_starter)
593 * Program check handler routine
596 ENTRY(pgm_check_handler)
597 stpt __LC_SYNC_ENTER_TIMER
599 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
600 lg %r10,__LC_LAST_BREAK
603 larl %r13,cleanup_critical
604 lmg %r8,%r9,__LC_PGM_OLD_PSW
605 tmhh %r8,0x0001 # test problem state bit
606 jnz 2f # -> fault in user space
607 #if IS_ENABLED(CONFIG_KVM)
608 # cleanup critical section for program checks in sie64a
610 slg %r14,BASED(.Lsie_critical_start)
611 clg %r14,BASED(.Lsie_critical_length)
613 lg %r14,__SF_SIE_CONTROL(%r15) # get control block pointer
614 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
615 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
616 larl %r9,sie_exit # skip forward to sie_exit
617 lghi %r11,_PIF_GUEST_FAULT
619 0: tmhh %r8,0x4000 # PER bit set in old PSW ?
620 jnz 1f # -> enabled, can't be a double fault
621 tm __LC_PGM_ILC+3,0x80 # check for per exception
622 jnz .Lpgm_svcper # -> single stepped svc
623 1: CHECK_STACK __LC_SAVE_AREA_SYNC
624 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
625 # CHECK_VMAP_STACK branches to stack_overflow or 4f
626 CHECK_VMAP_STACK __LC_SAVE_AREA_SYNC,4f
627 2: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
628 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
629 lg %r15,__LC_KERNEL_STACK
631 aghi %r14,__TASK_thread # pointer to thread_struct
632 lghi %r13,__LC_PGM_TDB
633 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
635 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
636 3: stg %r10,__THREAD_last_break(%r14)
638 la %r11,STACK_FRAME_OVERHEAD(%r15)
639 stmg %r0,%r7,__PT_R0(%r11)
640 # clear user controlled registers to prevent speculative use
649 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
650 stmg %r8,%r9,__PT_PSW(%r11)
651 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
652 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
653 stg %r13,__PT_FLAGS(%r11)
654 stg %r10,__PT_ARGS(%r11)
655 tm __LC_PGM_ILC+3,0x80 # check for per exception
657 tmhh %r8,0x0001 # kernel per event ?
659 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
660 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
661 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
662 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
664 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
665 larl %r1,pgm_check_table
666 llgh %r10,__PT_INT_CODE+2(%r11)
670 lgf %r9,0(%r10,%r1) # load address of handler routine
671 lgr %r2,%r11 # pass pointer to pt_regs
672 BASR_EX %r14,%r9 # branch to interrupt-handler
675 tm __PT_PSW+1(%r11),0x01 # returning to user ?
677 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
682 # PER event in supervisor state, must be kprobes
686 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
687 lgr %r2,%r11 # pass pointer to pt_regs
688 brasl %r14,do_per_trap
692 # single stepped system call
695 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
696 lghi %r13,__TASK_thread
698 stg %r14,__LC_RETURN_PSW+8
699 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
700 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
703 * IO interrupt handler routine
705 ENTRY(io_int_handler)
707 stpt __LC_ASYNC_ENTER_TIMER
709 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
711 larl %r13,cleanup_critical
712 lmg %r8,%r9,__LC_IO_OLD_PSW
713 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
714 stmg %r0,%r7,__PT_R0(%r11)
715 # clear user controlled registers to prevent speculative use
725 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
726 stmg %r8,%r9,__PT_PSW(%r11)
727 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
728 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
729 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
732 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
734 lgr %r2,%r11 # pass pointer to pt_regs
735 lghi %r3,IO_INTERRUPT
736 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
738 lghi %r3,THIN_INTERRUPT
741 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
745 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
751 TSTMSK __TI_flags(%r12),_TIF_WORK
752 jnz .Lio_work # there is work to do (signals etc.)
753 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
756 lg %r14,__LC_VDSO_PER_CPU
757 lmg %r0,%r10,__PT_R0(%r11)
758 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
759 tm __PT_PSW+1(%r11),0x01 # returning to user ?
761 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
764 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
766 lmg %r11,%r15,__PT_R11(%r11)
767 lpswe __LC_RETURN_PSW
771 # There is work todo, find out in which context we have been interrupted:
772 # 1) if we return to user space we can do all _TIF_WORK work
773 # 2) if we return to kernel code and kvm is enabled check if we need to
774 # modify the psw to leave SIE
775 # 3) if we return to kernel code and preemptive scheduling is enabled check
776 # the preemption counter and if it is zero call preempt_schedule_irq
777 # Before any work can be done, a switch to the kernel stack is required.
780 tm __PT_PSW+1(%r11),0x01 # returning to user ?
781 jo .Lio_work_user # yes -> do resched & signal
782 #ifdef CONFIG_PREEMPT
783 # check for preemptive scheduling
784 icm %r0,15,__LC_PREEMPT_COUNT
785 jnz .Lio_restore # preemption is disabled
786 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
788 # switch to kernel stack
789 lg %r1,__PT_R15(%r11)
790 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
791 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
792 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
793 la %r11,STACK_FRAME_OVERHEAD(%r1)
795 # TRACE_IRQS_ON already done at .Lio_return, call
796 # TRACE_IRQS_OFF to keep things symmetrical
798 brasl %r14,preempt_schedule_irq
805 # Need to do work before returning to userspace, switch to kernel stack
808 lg %r1,__LC_KERNEL_STACK
809 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
810 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
811 la %r11,STACK_FRAME_OVERHEAD(%r1)
815 # One of the work bits is on. Find out which one.
818 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
820 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
822 #ifdef CONFIG_LIVEPATCH
823 TSTMSK __TI_flags(%r12),_TIF_PATCH_PENDING
824 jo .Lio_patch_pending
826 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
828 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
829 jo .Lio_notify_resume
830 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
831 jo .Lio_guarded_storage
832 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
834 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
836 j .Lio_return # beware of critical section cleanup
839 # _CIF_MCCK_PENDING is set, call handler
842 # TRACE_IRQS_ON already done at .Lio_return
843 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
848 # _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
851 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_SECONDARY
852 lctlg %c7,%c7,__LC_VDSO_ASCE # load secondary asce
853 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_PRIMARY
855 #ifndef CONFIG_HAVE_MARCH_Z10_FEATURES
856 tm __LC_STFLE_FAC_LIST+3,0x10 # has MVCOS ?
857 jnz .Lio_set_fs_fixup
858 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
859 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
863 larl %r14,.Lio_return
867 # CIF_FPU is set, restore floating-point controls and floating-point registers.
870 larl %r14,.Lio_return
874 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
876 .Lio_guarded_storage:
877 # TRACE_IRQS_ON already done at .Lio_return
878 ssm __LC_SVC_NEW_PSW # reenable interrupts
879 lgr %r2,%r11 # pass pointer to pt_regs
880 brasl %r14,gs_load_bc_cb
881 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
886 # _TIF_NEED_RESCHED is set, call schedule
889 # TRACE_IRQS_ON already done at .Lio_return
890 ssm __LC_SVC_NEW_PSW # reenable interrupts
891 brasl %r14,schedule # call scheduler
892 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
897 # _TIF_PATCH_PENDING is set, call klp_update_patch_state
899 #ifdef CONFIG_LIVEPATCH
901 lg %r2,__LC_CURRENT # pass pointer to task struct
902 larl %r14,.Lio_return
903 jg klp_update_patch_state
907 # _TIF_SIGPENDING or is set, call do_signal
910 # TRACE_IRQS_ON already done at .Lio_return
911 ssm __LC_SVC_NEW_PSW # reenable interrupts
912 lgr %r2,%r11 # pass pointer to pt_regs
914 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
919 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
922 # TRACE_IRQS_ON already done at .Lio_return
923 ssm __LC_SVC_NEW_PSW # reenable interrupts
924 lgr %r2,%r11 # pass pointer to pt_regs
925 brasl %r14,do_notify_resume
926 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
931 * External interrupt handler routine
933 ENTRY(ext_int_handler)
935 stpt __LC_ASYNC_ENTER_TIMER
937 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
939 larl %r13,cleanup_critical
940 lmg %r8,%r9,__LC_EXT_OLD_PSW
941 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
942 stmg %r0,%r7,__PT_R0(%r11)
943 # clear user controlled registers to prevent speculative use
953 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
954 stmg %r8,%r9,__PT_PSW(%r11)
955 lghi %r1,__LC_EXT_PARAMS2
956 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
957 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
958 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
959 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
960 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
963 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
964 lgr %r2,%r11 # pass pointer to pt_regs
965 lghi %r3,EXT_INTERRUPT
970 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
973 stg %r3,__SF_EMPTY(%r15)
974 larl %r1,.Lpsw_idle_lpsw+4
975 stg %r1,__SF_EMPTY+8(%r15)
977 larl %r1,smp_cpu_mtid
981 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
984 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
986 STCK __CLOCK_IDLE_ENTER(%r2)
987 stpt __TIMER_IDLE_ENTER(%r2)
989 lpswe __SF_EMPTY(%r15)
994 * Store floating-point controls and floating-point or vector register
995 * depending whether the vector facility is available. A critical section
996 * cleanup assures that the registers are stored even if interrupted for
997 * some other work. The CIF_FPU flag is set to trigger a lazy restore
998 * of the register contents at return from io or a system call.
1000 ENTRY(save_fpu_regs)
1002 aghi %r2,__TASK_thread
1003 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1004 jo .Lsave_fpu_regs_exit
1005 stfpc __THREAD_FPU_fpc(%r2)
1006 lg %r3,__THREAD_FPU_regs(%r2)
1007 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1008 jz .Lsave_fpu_regs_fp # no -> store FP regs
1009 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
1010 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
1011 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
1029 .Lsave_fpu_regs_done:
1030 oi __LC_CPU_FLAGS+7,_CIF_FPU
1031 .Lsave_fpu_regs_exit:
1033 .Lsave_fpu_regs_end:
1034 EXPORT_SYMBOL(save_fpu_regs)
1037 * Load floating-point controls and floating-point or vector registers.
1038 * A critical section cleanup assures that the register contents are
1039 * loaded even if interrupted for some other work.
1041 * There are special calling conventions to fit into sysc and io return work:
1042 * %r15: <kernel stack>
1043 * The function requires:
1048 aghi %r4,__TASK_thread
1049 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
1050 jno .Lload_fpu_regs_exit
1051 lfpc __THREAD_FPU_fpc(%r4)
1052 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1053 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
1054 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
1056 VLM %v16,%v31,256,%r4
1057 j .Lload_fpu_regs_done
1075 .Lload_fpu_regs_done:
1076 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
1077 .Lload_fpu_regs_exit:
1079 .Lload_fpu_regs_end:
1084 * Machine check handler routines
1086 ENTRY(mcck_int_handler)
1087 STCK __LC_MCCK_CLOCK
1089 la %r1,4095 # validate r1
1090 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # validate cpu timer
1091 sckc __LC_CLOCK_COMPARATOR # validate comparator
1092 lam %a0,%a15,__LC_AREGS_SAVE_AREA-4095(%r1) # validate acrs
1093 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# validate gprs
1094 lg %r12,__LC_CURRENT
1095 larl %r13,cleanup_critical
1096 lmg %r8,%r9,__LC_MCK_OLD_PSW
1097 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
1098 jo .Lmcck_panic # yes -> rest of mcck code invalid
1099 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CR_VALID
1100 jno .Lmcck_panic # control registers invalid -> panic
1102 lctlg %c0,%c15,__LC_CREGS_SAVE_AREA-4095(%r14) # validate ctl regs
1104 lg %r11,__LC_MCESAD-4095(%r14) # extended machine check save area
1105 nill %r11,0xfc00 # MCESA_ORIGIN_MASK
1106 TSTMSK __LC_CREGS_SAVE_AREA+16-4095(%r14),CR2_GUARDED_STORAGE
1108 TSTMSK __LC_MCCK_CODE,MCCK_CODE_GS_VALID
1110 .insn rxy,0xe3000000004d,0,__MCESA_GS_SAVE_AREA(%r11) # LGSC
1111 0: l %r14,__LC_FP_CREG_SAVE_AREA-4095(%r14)
1112 TSTMSK __LC_MCCK_CODE,MCCK_CODE_FC_VALID
1116 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
1118 lghi %r14,__LC_FPREGS_SAVE_AREA
1136 0: VLM %v0,%v15,0,%r11
1137 VLM %v16,%v31,256,%r11
1138 1: lghi %r14,__LC_CPU_TIMER_SAVE_AREA
1139 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1140 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
1142 la %r14,__LC_SYNC_ENTER_TIMER
1143 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
1145 la %r14,__LC_ASYNC_ENTER_TIMER
1146 0: clc 0(8,%r14),__LC_EXIT_TIMER
1148 la %r14,__LC_EXIT_TIMER
1149 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
1151 la %r14,__LC_LAST_UPDATE_TIMER
1153 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
1154 3: TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_MWP_VALID
1156 tmhh %r8,0x0001 # interrupting from user ?
1158 TSTMSK __LC_MCCK_CODE,MCCK_CODE_PSW_IA_VALID
1160 4: ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
1161 SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
1163 lghi %r14,__LC_GPREGS_SAVE_AREA+64
1164 stmg %r0,%r7,__PT_R0(%r11)
1165 # clear user controlled registers to prevent speculative use
1175 mvc __PT_R8(64,%r11),0(%r14)
1176 stmg %r8,%r9,__PT_PSW(%r11)
1177 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
1178 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1179 lgr %r2,%r11 # pass pointer to pt_regs
1180 brasl %r14,s390_do_machine_check
1181 tm __PT_PSW+1(%r11),0x01 # returning to user ?
1183 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
1184 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
1185 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
1186 la %r11,STACK_FRAME_OVERHEAD(%r1)
1188 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
1191 brasl %r14,s390_handle_mcck
1194 lg %r14,__LC_VDSO_PER_CPU
1195 lmg %r0,%r10,__PT_R0(%r11)
1196 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
1197 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
1199 BPEXIT __TI_flags(%r12),_TIF_ISOLATE_BP
1200 stpt __LC_EXIT_TIMER
1201 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
1202 0: lmg %r11,%r15,__PT_R11(%r11)
1203 lpswe __LC_RETURN_MCCK_PSW
1206 lg %r15,__LC_NODAT_STACK
1207 la %r11,STACK_FRAME_OVERHEAD(%r15)
1211 # PSW restart interrupt handler
1213 ENTRY(restart_int_handler)
1214 ALTERNATIVE "", ".insn s,0xb2800000,_LPP_OFFSET", 40
1215 stg %r15,__LC_SAVE_AREA_RESTART
1216 lg %r15,__LC_RESTART_STACK
1217 xc STACK_FRAME_OVERHEAD(__PT_SIZE,%r15),STACK_FRAME_OVERHEAD(%r15)
1218 stmg %r0,%r14,STACK_FRAME_OVERHEAD+__PT_R0(%r15)
1219 mvc STACK_FRAME_OVERHEAD+__PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
1220 mvc STACK_FRAME_OVERHEAD+__PT_PSW(16,%r15),__LC_RST_OLD_PSW
1221 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
1222 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
1223 lg %r2,__LC_RESTART_DATA
1224 lg %r3,__LC_RESTART_SOURCE
1225 ltgr %r3,%r3 # test source cpu address
1226 jm 1f # negative -> skip source stop
1227 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
1228 brc 10,0b # wait for status stored
1229 1: basr %r14,%r1 # call function
1230 stap __SF_EMPTY(%r15) # store cpu address
1231 llgh %r3,__SF_EMPTY(%r15)
1232 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
1236 .section .kprobes.text, "ax"
1238 #if defined(CONFIG_CHECK_STACK) || defined(CONFIG_VMAP_STACK)
1240 * The synchronous or the asynchronous stack overflowed. We are dead.
1241 * No need to properly save the registers, we are going to panic anyway.
1242 * Setup a pt_regs so that show_trace can provide a good call trace.
1245 lg %r15,__LC_NODAT_STACK # change to panic stack
1246 la %r11,STACK_FRAME_OVERHEAD(%r15)
1247 stmg %r0,%r7,__PT_R0(%r11)
1248 stmg %r8,%r9,__PT_PSW(%r11)
1249 mvc __PT_R8(64,%r11),0(%r14)
1250 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1251 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1252 lgr %r2,%r11 # pass pointer to pt_regs
1253 jg kernel_stack_overflow
1257 #if IS_ENABLED(CONFIG_KVM)
1258 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1260 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1263 clg %r9,BASED(.Lcleanup_table) # system_call
1265 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1266 jl .Lcleanup_system_call
1267 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1269 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1270 jl .Lcleanup_sysc_tif
1271 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1272 jl .Lcleanup_sysc_restore
1273 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1275 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1277 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1278 jl .Lcleanup_io_restore
1279 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1281 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1283 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1285 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1286 jl .Lcleanup_save_fpu_regs
1287 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1289 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1290 jl .Lcleanup_load_fpu_regs
1298 .quad .Lsysc_restore
1304 .quad .Lpsw_idle_end
1306 .quad .Lsave_fpu_regs_end
1308 .quad .Lload_fpu_regs_end
1310 #if IS_ENABLED(CONFIG_KVM)
1311 .Lcleanup_table_sie:
1316 cghi %r11,__LC_SAVE_AREA_ASYNC #Is this in normal interrupt?
1318 slg %r9,BASED(.Lsie_crit_mcck_start)
1319 clg %r9,BASED(.Lsie_crit_mcck_length)
1321 oi __LC_CPU_FLAGS+7, _CIF_MCCK_GUEST
1322 1: BPENTER __SF_SIE_FLAGS(%r15),(_TIF_ISOLATE_BP|_TIF_ISOLATE_BP_GUEST)
1323 lg %r9,__SF_SIE_CONTROL(%r15) # get control block pointer
1324 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1325 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1326 larl %r9,sie_exit # skip forward to sie_exit
1330 .Lcleanup_system_call:
1331 # check if stpt has been executed
1332 clg %r9,BASED(.Lcleanup_system_call_insn)
1334 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1335 cghi %r11,__LC_SAVE_AREA_ASYNC
1337 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
1338 0: # check if stmg has been executed
1339 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1341 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
1342 0: # check if base register setup + TIF bit load has been done
1343 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1345 # set up saved register r12 task struct pointer
1347 # set up saved register r13 __TASK_thread offset
1348 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
1349 0: # check if the user time update has been done
1350 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1352 lg %r15,__LC_EXIT_TIMER
1353 slg %r15,__LC_SYNC_ENTER_TIMER
1354 alg %r15,__LC_USER_TIMER
1355 stg %r15,__LC_USER_TIMER
1356 0: # check if the system time update has been done
1357 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1359 lg %r15,__LC_LAST_UPDATE_TIMER
1360 slg %r15,__LC_EXIT_TIMER
1361 alg %r15,__LC_SYSTEM_TIMER
1362 stg %r15,__LC_SYSTEM_TIMER
1363 0: # update accounting time stamp
1364 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1365 BPENTER __TI_flags(%r12),_TIF_ISOLATE_BP
1366 # set up saved register r11
1367 lg %r15,__LC_KERNEL_STACK
1368 la %r9,STACK_FRAME_OVERHEAD(%r15)
1369 stg %r9,24(%r11) # r11 pt_regs pointer
1371 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1372 stmg %r0,%r7,__PT_R0(%r9)
1373 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1374 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1375 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1376 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1377 # setup saved register r15
1378 stg %r15,56(%r11) # r15 stack pointer
1379 # set new psw address and exit
1380 larl %r9,.Lsysc_do_svc
1382 .Lcleanup_system_call_insn:
1386 .quad .Lsysc_vtime+36
1387 .quad .Lsysc_vtime+42
1388 .Lcleanup_system_call_const:
1395 .Lcleanup_sysc_restore:
1396 # check if stpt has been executed
1397 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1399 mvc __LC_EXIT_TIMER(8),__LC_ASYNC_ENTER_TIMER
1400 cghi %r11,__LC_SAVE_AREA_ASYNC
1402 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1403 0: clg %r9,BASED(.Lcleanup_sysc_restore_insn+8)
1405 lg %r9,24(%r11) # get saved pointer to pt_regs
1406 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1407 mvc 0(64,%r11),__PT_R8(%r9)
1408 lmg %r0,%r7,__PT_R0(%r9)
1409 1: lmg %r8,%r9,__LC_RETURN_PSW
1411 .Lcleanup_sysc_restore_insn:
1412 .quad .Lsysc_exit_timer
1413 .quad .Lsysc_done - 4
1419 .Lcleanup_io_restore:
1420 # check if stpt has been executed
1421 clg %r9,BASED(.Lcleanup_io_restore_insn)
1423 mvc __LC_EXIT_TIMER(8),__LC_MCCK_ENTER_TIMER
1424 0: clg %r9,BASED(.Lcleanup_io_restore_insn+8)
1426 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1427 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1428 mvc 0(64,%r11),__PT_R8(%r9)
1429 lmg %r0,%r7,__PT_R0(%r9)
1430 1: lmg %r8,%r9,__LC_RETURN_PSW
1432 .Lcleanup_io_restore_insn:
1433 .quad .Lio_exit_timer
1437 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1438 # copy interrupt clock & cpu timer
1439 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1440 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1441 cghi %r11,__LC_SAVE_AREA_ASYNC
1443 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1444 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
1445 0: # check if stck & stpt have been executed
1446 clg %r9,BASED(.Lcleanup_idle_insn)
1448 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1449 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
1450 1: # calculate idle cycles
1452 clg %r9,BASED(.Lcleanup_idle_insn)
1454 larl %r1,smp_cpu_mtid
1458 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1460 ag %r3,__LC_PERCPU_OFFSET
1461 la %r4,__SF_EMPTY+16(%r15)
1470 3: # account system time going idle
1471 lg %r9,__LC_STEAL_TIMER
1472 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1473 slg %r9,__LC_LAST_UPDATE_CLOCK
1474 stg %r9,__LC_STEAL_TIMER
1475 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1476 lg %r9,__LC_SYSTEM_TIMER
1477 alg %r9,__LC_LAST_UPDATE_TIMER
1478 slg %r9,__TIMER_IDLE_ENTER(%r2)
1479 stg %r9,__LC_SYSTEM_TIMER
1480 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1481 # prepare return psw
1482 nihh %r8,0xfcfd # clear irq & wait state bits
1483 lg %r9,48(%r11) # return from psw_idle
1485 .Lcleanup_idle_insn:
1486 .quad .Lpsw_idle_lpsw
1488 .Lcleanup_save_fpu_regs:
1489 larl %r9,save_fpu_regs
1492 .Lcleanup_load_fpu_regs:
1493 larl %r9,load_fpu_regs
1501 .quad .L__critical_start
1503 .quad .L__critical_end - .L__critical_start
1504 #if IS_ENABLED(CONFIG_KVM)
1505 .Lsie_critical_start:
1507 .Lsie_critical_length:
1508 .quad .Lsie_done - .Lsie_gmap
1509 .Lsie_crit_mcck_start:
1511 .Lsie_crit_mcck_length:
1512 .quad .Lsie_skip - .Lsie_entry
1514 .section .rodata, "a"
1515 #define SYSCALL(esame,emu) .long esame
1516 .globl sys_call_table
1518 #include "asm/syscall_table.h"
1521 #ifdef CONFIG_COMPAT
1523 #define SYSCALL(esame,emu) .long emu
1524 .globl sys_call_table_emu
1526 #include "asm/syscall_table.h"