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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / block / sx8.c
blob064b8c5c7a326125459ada392a1ea83e475f59ac
1 /*
2 * sx8.c: Driver for Promise SATA SX8 looks-like-I2O hardware
3 *
4 * Copyright 2004-2005 Red Hat, Inc.
5 *
6 * Author/maintainer: Jeff Garzik <jgarzik@pobox.com>
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/init.h>
16 #include <linux/pci.h>
17 #include <linux/slab.h>
18 #include <linux/spinlock.h>
19 #include <linux/blk-mq.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/compiler.h>
23 #include <linux/workqueue.h>
24 #include <linux/bitops.h>
25 #include <linux/delay.h>
26 #include <linux/ktime.h>
27 #include <linux/hdreg.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/completion.h>
30 #include <linux/scatterlist.h>
31 #include <asm/io.h>
32 #include <linux/uaccess.h>
33
34 #if 0
35 #define CARM_DEBUG
36 #define CARM_VERBOSE_DEBUG
37 #else
38 #undef CARM_DEBUG
39 #undef CARM_VERBOSE_DEBUG
40 #endif
41 #undef CARM_NDEBUG
42
43 #define DRV_NAME "sx8"
44 #define DRV_VERSION "1.0"
45 #define PFX DRV_NAME ": "
46
47 MODULE_AUTHOR("Jeff Garzik");
48 MODULE_LICENSE("GPL");
49 MODULE_DESCRIPTION("Promise SATA SX8 block driver");
50 MODULE_VERSION(DRV_VERSION);
51
52 /*
53 * SX8 hardware has a single message queue for all ATA ports.
54 * When this driver was written, the hardware (firmware?) would
55 * corrupt data eventually, if more than one request was outstanding.
56 * As one can imagine, having 8 ports bottlenecking on a single
57 * command hurts performance.
58 *
59 * Based on user reports, later versions of the hardware (firmware?)
60 * seem to be able to survive with more than one command queued.
61 *
62 * Therefore, we default to the safe option -- 1 command -- but
63 * allow the user to increase this.
64 *
65 * SX8 should be able to support up to ~60 queued commands (CARM_MAX_REQ),
66 * but problems seem to occur when you exceed ~30, even on newer hardware.
67 */
68 static int max_queue = 1;
69 module_param(max_queue, int, 0444);
70 MODULE_PARM_DESC(max_queue, "Maximum number of queued commands. (min==1, max==30, safe==1)");
71
72
73 #define NEXT_RESP(idx) ((idx + 1) % RMSG_Q_LEN)
74
75 /* 0xf is just arbitrary, non-zero noise; this is sorta like poisoning */
76 #define TAG_ENCODE(tag) (((tag) << 16) | 0xf)
77 #define TAG_DECODE(tag) (((tag) >> 16) & 0x1f)
78 #define TAG_VALID(tag) ((((tag) & 0xf) == 0xf) && (TAG_DECODE(tag) < 32))
79
80 /* note: prints function name for you */
81 #ifdef CARM_DEBUG
82 #define DPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
83 #ifdef CARM_VERBOSE_DEBUG
84 #define VPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
85 #else
86 #define VPRINTK(fmt, args...)
87 #endif /* CARM_VERBOSE_DEBUG */
88 #else
89 #define DPRINTK(fmt, args...)
90 #define VPRINTK(fmt, args...)
91 #endif /* CARM_DEBUG */
92
93 #ifdef CARM_NDEBUG
94 #define assert(expr)
95 #else
96 #define assert(expr) \
97 if(unlikely(!(expr))) { \
98 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
99 #expr, __FILE__, __func__, __LINE__); \
100 }
101 #endif
102
103 /* defines only for the constants which don't work well as enums */
104 struct carm_host;
105
106 enum {
107 /* adapter-wide limits */
108 CARM_MAX_PORTS = 8,
109 CARM_SHM_SIZE = (4096 << 7),
110 CARM_MINORS_PER_MAJOR = 256 / CARM_MAX_PORTS,
111 CARM_MAX_WAIT_Q = CARM_MAX_PORTS + 1,
112
113 /* command message queue limits */
114 CARM_MAX_REQ = 64, /* max command msgs per host */
115 CARM_MSG_LOW_WATER = (CARM_MAX_REQ / 4), /* refill mark */
116
117 /* S/G limits, host-wide and per-request */
118 CARM_MAX_REQ_SG = 32, /* max s/g entries per request */
119 CARM_MAX_HOST_SG = 600, /* max s/g entries per host */
120 CARM_SG_LOW_WATER = (CARM_MAX_HOST_SG / 4), /* re-fill mark */
121
122 /* hardware registers */
123 CARM_IHQP = 0x1c,
124 CARM_INT_STAT = 0x10, /* interrupt status */
125 CARM_INT_MASK = 0x14, /* interrupt mask */
126 CARM_HMUC = 0x18, /* host message unit control */
127 RBUF_ADDR_LO = 0x20, /* response msg DMA buf low 32 bits */
128 RBUF_ADDR_HI = 0x24, /* response msg DMA buf high 32 bits */
129 RBUF_BYTE_SZ = 0x28,
130 CARM_RESP_IDX = 0x2c,
131 CARM_CMS0 = 0x30, /* command message size reg 0 */
132 CARM_LMUC = 0x48,
133 CARM_HMPHA = 0x6c,
134 CARM_INITC = 0xb5,
135
136 /* bits in CARM_INT_{STAT,MASK} */
137 INT_RESERVED = 0xfffffff0,
138 INT_WATCHDOG = (1 << 3), /* watchdog timer */
139 INT_Q_OVERFLOW = (1 << 2), /* cmd msg q overflow */
140 INT_Q_AVAILABLE = (1 << 1), /* cmd msg q has free space */
141 INT_RESPONSE = (1 << 0), /* response msg available */
142 INT_ACK_MASK = INT_WATCHDOG | INT_Q_OVERFLOW,
143 INT_DEF_MASK = INT_RESERVED | INT_Q_OVERFLOW |
144 INT_RESPONSE,
145
146 /* command messages, and related register bits */
147 CARM_HAVE_RESP = 0x01,
148 CARM_MSG_READ = 1,
149 CARM_MSG_WRITE = 2,
150 CARM_MSG_VERIFY = 3,
151 CARM_MSG_GET_CAPACITY = 4,
152 CARM_MSG_FLUSH = 5,
153 CARM_MSG_IOCTL = 6,
154 CARM_MSG_ARRAY = 8,
155 CARM_MSG_MISC = 9,
156 CARM_CME = (1 << 2),
157 CARM_RME = (1 << 1),
158 CARM_WZBC = (1 << 0),
159 CARM_RMI = (1 << 0),
160 CARM_Q_FULL = (1 << 3),
161 CARM_MSG_SIZE = 288,
162 CARM_Q_LEN = 48,
163
164 /* CARM_MSG_IOCTL messages */
165 CARM_IOC_SCAN_CHAN = 5, /* scan channels for devices */
166 CARM_IOC_GET_TCQ = 13, /* get tcq/ncq depth */
167 CARM_IOC_SET_TCQ = 14, /* set tcq/ncq depth */
168
169 IOC_SCAN_CHAN_NODEV = 0x1f,
170 IOC_SCAN_CHAN_OFFSET = 0x40,
171
172 /* CARM_MSG_ARRAY messages */
173 CARM_ARRAY_INFO = 0,
174
175 ARRAY_NO_EXIST = (1 << 31),
176
177 /* response messages */
178 RMSG_SZ = 8, /* sizeof(struct carm_response) */
179 RMSG_Q_LEN = 48, /* resp. msg list length */
180 RMSG_OK = 1, /* bit indicating msg was successful */
181 /* length of entire resp. msg buffer */
182 RBUF_LEN = RMSG_SZ * RMSG_Q_LEN,
183
184 PDC_SHM_SIZE = (4096 << 7), /* length of entire h/w buffer */
185
186 /* CARM_MSG_MISC messages */
187 MISC_GET_FW_VER = 2,
188 MISC_ALLOC_MEM = 3,
189 MISC_SET_TIME = 5,
190
191 /* MISC_GET_FW_VER feature bits */
192 FW_VER_4PORT = (1 << 2), /* 1=4 ports, 0=8 ports */
193 FW_VER_NON_RAID = (1 << 1), /* 1=non-RAID firmware, 0=RAID */
194 FW_VER_ZCR = (1 << 0), /* zero channel RAID (whatever that is) */
195
196 /* carm_host flags */
197 FL_NON_RAID = FW_VER_NON_RAID,
198 FL_4PORT = FW_VER_4PORT,
199 FL_FW_VER_MASK = (FW_VER_NON_RAID | FW_VER_4PORT),
200 FL_DYN_MAJOR = (1 << 17),
201 };
202
203 enum {
204 CARM_SG_BOUNDARY = 0xffffUL, /* s/g segment boundary */
205 };
206
207 enum scatter_gather_types {
208 SGT_32BIT = 0,
209 SGT_64BIT = 1,
210 };
211
212 enum host_states {
213 HST_INVALID, /* invalid state; never used */
214 HST_ALLOC_BUF, /* setting up master SHM area */
215 HST_ERROR, /* we never leave here */
216 HST_PORT_SCAN, /* start dev scan */
217 HST_DEV_SCAN_START, /* start per-device probe */
218 HST_DEV_SCAN, /* continue per-device probe */
219 HST_DEV_ACTIVATE, /* activate devices we found */
220 HST_PROBE_FINISHED, /* probe is complete */
221 HST_PROBE_START, /* initiate probe */
222 HST_SYNC_TIME, /* tell firmware what time it is */
223 HST_GET_FW_VER, /* get firmware version, adapter port cnt */
224 };
225
226 #ifdef CARM_DEBUG
227 static const char *state_name[] = {
228 "HST_INVALID",
229 "HST_ALLOC_BUF",
230 "HST_ERROR",
231 "HST_PORT_SCAN",
232 "HST_DEV_SCAN_START",
233 "HST_DEV_SCAN",
234 "HST_DEV_ACTIVATE",
235 "HST_PROBE_FINISHED",
236 "HST_PROBE_START",
237 "HST_SYNC_TIME",
238 "HST_GET_FW_VER",
239 };
240 #endif
241
242 struct carm_port {
243 unsigned int port_no;
244 struct gendisk *disk;
245 struct carm_host *host;
246 struct blk_mq_tag_set tag_set;
247
248 /* attached device characteristics */
249 u64 capacity;
250 char name[41];
251 u16 dev_geom_head;
252 u16 dev_geom_sect;
253 u16 dev_geom_cyl;
254 };
255
256 struct carm_request {
257 unsigned int tag;
258 int n_elem;
259 unsigned int msg_type;
260 unsigned int msg_subtype;
261 unsigned int msg_bucket;
262 struct request *rq;
263 struct carm_port *port;
264 struct scatterlist sg[CARM_MAX_REQ_SG];
265 };
266
267 struct carm_host {
268 unsigned long flags;
269 void __iomem *mmio;
270 void *shm;
271 dma_addr_t shm_dma;
272
273 int major;
274 int id;
275 char name[32];
276
277 spinlock_t lock;
278 struct pci_dev *pdev;
279 unsigned int state;
280 u32 fw_ver;
281
282 struct blk_mq_tag_set tag_set;
283 struct request_queue *oob_q;
284 unsigned int n_oob;
285
286 unsigned int hw_sg_used;
287
288 unsigned int resp_idx;
289
290 unsigned int wait_q_prod;
291 unsigned int wait_q_cons;
292 struct request_queue *wait_q[CARM_MAX_WAIT_Q];
293
294 unsigned int n_msgs;
295 u64 msg_alloc;
296 struct carm_request req[CARM_MAX_REQ];
297 void *msg_base;
298 dma_addr_t msg_dma;
299
300 int cur_scan_dev;
301 unsigned long dev_active;
302 unsigned long dev_present;
303 struct carm_port port[CARM_MAX_PORTS];
304
305 struct work_struct fsm_task;
306
307 struct completion probe_comp;
308 };
309
310 struct carm_response {
311 __le32 ret_handle;
312 __le32 status;
313 } __attribute__((packed));
314
315 struct carm_msg_sg {
316 __le32 start;
317 __le32 len;
318 } __attribute__((packed));
319
320 struct carm_msg_rw {
321 u8 type;
322 u8 id;
323 u8 sg_count;
324 u8 sg_type;
325 __le32 handle;
326 __le32 lba;
327 __le16 lba_count;
328 __le16 lba_high;
329 struct carm_msg_sg sg[32];
330 } __attribute__((packed));
331
332 struct carm_msg_allocbuf {
333 u8 type;
334 u8 subtype;
335 u8 n_sg;
336 u8 sg_type;
337 __le32 handle;
338 __le32 addr;
339 __le32 len;
340 __le32 evt_pool;
341 __le32 n_evt;
342 __le32 rbuf_pool;
343 __le32 n_rbuf;
344 __le32 msg_pool;
345 __le32 n_msg;
346 struct carm_msg_sg sg[8];
347 } __attribute__((packed));
348
349 struct carm_msg_ioctl {
350 u8 type;
351 u8 subtype;
352 u8 array_id;
353 u8 reserved1;
354 __le32 handle;
355 __le32 data_addr;
356 u32 reserved2;
357 } __attribute__((packed));
358
359 struct carm_msg_sync_time {
360 u8 type;
361 u8 subtype;
362 u16 reserved1;
363 __le32 handle;
364 u32 reserved2;
365 __le32 timestamp;
366 } __attribute__((packed));
367
368 struct carm_msg_get_fw_ver {
369 u8 type;
370 u8 subtype;
371 u16 reserved1;
372 __le32 handle;
373 __le32 data_addr;
374 u32 reserved2;
375 } __attribute__((packed));
376
377 struct carm_fw_ver {
378 __le32 version;
379 u8 features;
380 u8 reserved1;
381 u16 reserved2;
382 } __attribute__((packed));
383
384 struct carm_array_info {
385 __le32 size;
386
387 __le16 size_hi;
388 __le16 stripe_size;
389
390 __le32 mode;
391
392 __le16 stripe_blk_sz;
393 __le16 reserved1;
394
395 __le16 cyl;
396 __le16 head;
397
398 __le16 sect;
399 u8 array_id;
400 u8 reserved2;
401
402 char name[40];
403
404 __le32 array_status;
405
406 /* device list continues beyond this point? */
407 } __attribute__((packed));
408
409 static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
410 static void carm_remove_one (struct pci_dev *pdev);
411 static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo);
412
413 static const struct pci_device_id carm_pci_tbl[] = {
414 { PCI_VENDOR_ID_PROMISE, 0x8000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
415 { PCI_VENDOR_ID_PROMISE, 0x8002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
416 { } /* terminate list */
417 };
418 MODULE_DEVICE_TABLE(pci, carm_pci_tbl);
419
420 static struct pci_driver carm_driver = {
421 .name = DRV_NAME,
422 .id_table = carm_pci_tbl,
423 .probe = carm_init_one,
424 .remove = carm_remove_one,
425 };
426
427 static const struct block_device_operations carm_bd_ops = {
428 .owner = THIS_MODULE,
429 .getgeo = carm_bdev_getgeo,
430 };
431
432 static unsigned int carm_host_id;
433 static unsigned long carm_major_alloc;
434
435
436
437 static int carm_bdev_getgeo(struct block_device *bdev, struct hd_geometry *geo)
438 {
439 struct carm_port *port = bdev->bd_disk->private_data;
440
441 geo->heads = (u8) port->dev_geom_head;
442 geo->sectors = (u8) port->dev_geom_sect;
443 geo->cylinders = port->dev_geom_cyl;
444 return 0;
445 }
446
447 static const u32 msg_sizes[] = { 32, 64, 128, CARM_MSG_SIZE };
448
449 static inline int carm_lookup_bucket(u32 msg_size)
450 {
451 int i;
452
453 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
454 if (msg_size <= msg_sizes[i])
455 return i;
456
457 return -ENOENT;
458 }
459
460 static void carm_init_buckets(void __iomem *mmio)
461 {
462 unsigned int i;
463
464 for (i = 0; i < ARRAY_SIZE(msg_sizes); i++)
465 writel(msg_sizes[i], mmio + CARM_CMS0 + (4 * i));
466 }
467
468 static inline void *carm_ref_msg(struct carm_host *host,
469 unsigned int msg_idx)
470 {
471 return host->msg_base + (msg_idx * CARM_MSG_SIZE);
472 }
473
474 static inline dma_addr_t carm_ref_msg_dma(struct carm_host *host,
475 unsigned int msg_idx)
476 {
477 return host->msg_dma + (msg_idx * CARM_MSG_SIZE);
478 }
479
480 static int carm_send_msg(struct carm_host *host,
481 struct carm_request *crq)
482 {
483 void __iomem *mmio = host->mmio;
484 u32 msg = (u32) carm_ref_msg_dma(host, crq->tag);
485 u32 cm_bucket = crq->msg_bucket;
486 u32 tmp;
487 int rc = 0;
488
489 VPRINTK("ENTER\n");
490
491 tmp = readl(mmio + CARM_HMUC);
492 if (tmp & CARM_Q_FULL) {
493 #if 0
494 tmp = readl(mmio + CARM_INT_MASK);
495 tmp |= INT_Q_AVAILABLE;
496 writel(tmp, mmio + CARM_INT_MASK);
497 readl(mmio + CARM_INT_MASK); /* flush */
498 #endif
499 DPRINTK("host msg queue full\n");
500 rc = -EBUSY;
501 } else {
502 writel(msg | (cm_bucket << 1), mmio + CARM_IHQP);
503 readl(mmio + CARM_IHQP); /* flush */
504 }
505
506 return rc;
507 }
508
509 static struct carm_request *carm_get_request(struct carm_host *host)
510 {
511 unsigned int i;
512
513 /* obey global hardware limit on S/G entries */
514 if (host->hw_sg_used >= (CARM_MAX_HOST_SG - CARM_MAX_REQ_SG))
515 return NULL;
516
517 for (i = 0; i < max_queue; i++)
518 if ((host->msg_alloc & (1ULL << i)) == 0) {
519 struct carm_request *crq = &host->req[i];
520 crq->port = NULL;
521 crq->n_elem = 0;
522
523 host->msg_alloc |= (1ULL << i);
524 host->n_msgs++;
525
526 assert(host->n_msgs <= CARM_MAX_REQ);
527 sg_init_table(crq->sg, CARM_MAX_REQ_SG);
528 return crq;
529 }
530
531 DPRINTK("no request available, returning NULL\n");
532 return NULL;
533 }
534
535 static int carm_put_request(struct carm_host *host, struct carm_request *crq)
536 {
537 assert(crq->tag < max_queue);
538
539 if (unlikely((host->msg_alloc & (1ULL << crq->tag)) == 0))
540 return -EINVAL; /* tried to clear a tag that was not active */
541
542 assert(host->hw_sg_used >= crq->n_elem);
543
544 host->msg_alloc &= ~(1ULL << crq->tag);
545 host->hw_sg_used -= crq->n_elem;
546 host->n_msgs--;
547
548 return 0;
549 }
550
551 static struct carm_request *carm_get_special(struct carm_host *host)
552 {
553 unsigned long flags;
554 struct carm_request *crq = NULL;
555 struct request *rq;
556 int tries = 5000;
557
558 while (tries-- > 0) {
559 spin_lock_irqsave(&host->lock, flags);
560 crq = carm_get_request(host);
561 spin_unlock_irqrestore(&host->lock, flags);
562
563 if (crq)
564 break;
565 msleep(10);
566 }
567
568 if (!crq)
569 return NULL;
570
571 rq = blk_get_request(host->oob_q, REQ_OP_DRV_OUT, 0);
572 if (IS_ERR(rq)) {
573 spin_lock_irqsave(&host->lock, flags);
574 carm_put_request(host, crq);
575 spin_unlock_irqrestore(&host->lock, flags);
576 return NULL;
577 }
578
579 crq->rq = rq;
580 return crq;
581 }
582
583 static int carm_array_info (struct carm_host *host, unsigned int array_idx)
584 {
585 struct carm_msg_ioctl *ioc;
586 unsigned int idx;
587 u32 msg_data;
588 dma_addr_t msg_dma;
589 struct carm_request *crq;
590 int rc;
591
592 crq = carm_get_special(host);
593 if (!crq) {
594 rc = -ENOMEM;
595 goto err_out;
596 }
597
598 idx = crq->tag;
599
600 ioc = carm_ref_msg(host, idx);
601 msg_dma = carm_ref_msg_dma(host, idx);
602 msg_data = (u32) (msg_dma + sizeof(struct carm_array_info));
603
604 crq->msg_type = CARM_MSG_ARRAY;
605 crq->msg_subtype = CARM_ARRAY_INFO;
606 rc = carm_lookup_bucket(sizeof(struct carm_msg_ioctl) +
607 sizeof(struct carm_array_info));
608 BUG_ON(rc < 0);
609 crq->msg_bucket = (u32) rc;
610
611 memset(ioc, 0, sizeof(*ioc));
612 ioc->type = CARM_MSG_ARRAY;
613 ioc->subtype = CARM_ARRAY_INFO;
614 ioc->array_id = (u8) array_idx;
615 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
616 ioc->data_addr = cpu_to_le32(msg_data);
617
618 spin_lock_irq(&host->lock);
619 assert(host->state == HST_DEV_SCAN_START ||
620 host->state == HST_DEV_SCAN);
621 spin_unlock_irq(&host->lock);
622
623 DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx);
624 crq->rq->special = crq;
625 blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL);
626
627 return 0;
628
629 err_out:
630 spin_lock_irq(&host->lock);
631 host->state = HST_ERROR;
632 spin_unlock_irq(&host->lock);
633 return rc;
634 }
635
636 typedef unsigned int (*carm_sspc_t)(struct carm_host *, unsigned int, void *);
637
638 static int carm_send_special (struct carm_host *host, carm_sspc_t func)
639 {
640 struct carm_request *crq;
641 struct carm_msg_ioctl *ioc;
642 void *mem;
643 unsigned int idx, msg_size;
644 int rc;
645
646 crq = carm_get_special(host);
647 if (!crq)
648 return -ENOMEM;
649
650 idx = crq->tag;
651
652 mem = carm_ref_msg(host, idx);
653
654 msg_size = func(host, idx, mem);
655
656 ioc = mem;
657 crq->msg_type = ioc->type;
658 crq->msg_subtype = ioc->subtype;
659 rc = carm_lookup_bucket(msg_size);
660 BUG_ON(rc < 0);
661 crq->msg_bucket = (u32) rc;
662
663 DPRINTK("blk_execute_rq_nowait, tag == %u\n", idx);
664 crq->rq->special = crq;
665 blk_execute_rq_nowait(host->oob_q, NULL, crq->rq, true, NULL);
666
667 return 0;
668 }
669
670 static unsigned int carm_fill_sync_time(struct carm_host *host,
671 unsigned int idx, void *mem)
672 {
673 struct carm_msg_sync_time *st = mem;
674
675 time64_t tv = ktime_get_real_seconds();
676
677 memset(st, 0, sizeof(*st));
678 st->type = CARM_MSG_MISC;
679 st->subtype = MISC_SET_TIME;
680 st->handle = cpu_to_le32(TAG_ENCODE(idx));
681 st->timestamp = cpu_to_le32(tv);
682
683 return sizeof(struct carm_msg_sync_time);
684 }
685
686 static unsigned int carm_fill_alloc_buf(struct carm_host *host,
687 unsigned int idx, void *mem)
688 {
689 struct carm_msg_allocbuf *ab = mem;
690
691 memset(ab, 0, sizeof(*ab));
692 ab->type = CARM_MSG_MISC;
693 ab->subtype = MISC_ALLOC_MEM;
694 ab->handle = cpu_to_le32(TAG_ENCODE(idx));
695 ab->n_sg = 1;
696 ab->sg_type = SGT_32BIT;
697 ab->addr = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
698 ab->len = cpu_to_le32(PDC_SHM_SIZE >> 1);
699 ab->evt_pool = cpu_to_le32(host->shm_dma + (16 * 1024));
700 ab->n_evt = cpu_to_le32(1024);
701 ab->rbuf_pool = cpu_to_le32(host->shm_dma);
702 ab->n_rbuf = cpu_to_le32(RMSG_Q_LEN);
703 ab->msg_pool = cpu_to_le32(host->shm_dma + RBUF_LEN);
704 ab->n_msg = cpu_to_le32(CARM_Q_LEN);
705 ab->sg[0].start = cpu_to_le32(host->shm_dma + (PDC_SHM_SIZE >> 1));
706 ab->sg[0].len = cpu_to_le32(65536);
707
708 return sizeof(struct carm_msg_allocbuf);
709 }
710
711 static unsigned int carm_fill_scan_channels(struct carm_host *host,
712 unsigned int idx, void *mem)
713 {
714 struct carm_msg_ioctl *ioc = mem;
715 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) +
716 IOC_SCAN_CHAN_OFFSET);
717
718 memset(ioc, 0, sizeof(*ioc));
719 ioc->type = CARM_MSG_IOCTL;
720 ioc->subtype = CARM_IOC_SCAN_CHAN;
721 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
722 ioc->data_addr = cpu_to_le32(msg_data);
723
724 /* fill output data area with "no device" default values */
725 mem += IOC_SCAN_CHAN_OFFSET;
726 memset(mem, IOC_SCAN_CHAN_NODEV, CARM_MAX_PORTS);
727
728 return IOC_SCAN_CHAN_OFFSET + CARM_MAX_PORTS;
729 }
730
731 static unsigned int carm_fill_get_fw_ver(struct carm_host *host,
732 unsigned int idx, void *mem)
733 {
734 struct carm_msg_get_fw_ver *ioc = mem;
735 u32 msg_data = (u32) (carm_ref_msg_dma(host, idx) + sizeof(*ioc));
736
737 memset(ioc, 0, sizeof(*ioc));
738 ioc->type = CARM_MSG_MISC;
739 ioc->subtype = MISC_GET_FW_VER;
740 ioc->handle = cpu_to_le32(TAG_ENCODE(idx));
741 ioc->data_addr = cpu_to_le32(msg_data);
742
743 return sizeof(struct carm_msg_get_fw_ver) +
744 sizeof(struct carm_fw_ver);
745 }
746
747 static inline void carm_end_request_queued(struct carm_host *host,
748 struct carm_request *crq,
749 blk_status_t error)
750 {
751 struct request *req = crq->rq;
752 int rc;
753
754 blk_mq_end_request(req, error);
755
756 rc = carm_put_request(host, crq);
757 assert(rc == 0);
758 }
759
760 static inline void carm_push_q (struct carm_host *host, struct request_queue *q)
761 {
762 unsigned int idx = host->wait_q_prod % CARM_MAX_WAIT_Q;
763
764 blk_mq_stop_hw_queues(q);
765 VPRINTK("STOPPED QUEUE %p\n", q);
766
767 host->wait_q[idx] = q;
768 host->wait_q_prod++;
769 BUG_ON(host->wait_q_prod == host->wait_q_cons); /* overrun */
770 }
771
772 static inline struct request_queue *carm_pop_q(struct carm_host *host)
773 {
774 unsigned int idx;
775
776 if (host->wait_q_prod == host->wait_q_cons)
777 return NULL;
778
779 idx = host->wait_q_cons % CARM_MAX_WAIT_Q;
780 host->wait_q_cons++;
781
782 return host->wait_q[idx];
783 }
784
785 static inline void carm_round_robin(struct carm_host *host)
786 {
787 struct request_queue *q = carm_pop_q(host);
788 if (q) {
789 blk_mq_start_hw_queues(q);
790 VPRINTK("STARTED QUEUE %p\n", q);
791 }
792 }
793
794 static inline void carm_end_rq(struct carm_host *host, struct carm_request *crq,
795 blk_status_t error)
796 {
797 carm_end_request_queued(host, crq, error);
798 if (max_queue == 1)
799 carm_round_robin(host);
800 else if ((host->n_msgs <= CARM_MSG_LOW_WATER) &&
801 (host->hw_sg_used <= CARM_SG_LOW_WATER)) {
802 carm_round_robin(host);
803 }
804 }
805
806 static blk_status_t carm_oob_queue_rq(struct blk_mq_hw_ctx *hctx,
807 const struct blk_mq_queue_data *bd)
808 {
809 struct request_queue *q = hctx->queue;
810 struct carm_host *host = q->queuedata;
811 struct carm_request *crq;
812 int rc;
813
814 blk_mq_start_request(bd->rq);
815
816 spin_lock_irq(&host->lock);
817
818 crq = bd->rq->special;
819 assert(crq != NULL);
820 assert(crq->rq == bd->rq);
821
822 crq->n_elem = 0;
823
824 DPRINTK("send req\n");
825 rc = carm_send_msg(host, crq);
826 if (rc) {
827 carm_push_q(host, q);
828 spin_unlock_irq(&host->lock);
829 return BLK_STS_DEV_RESOURCE;
830 }
831
832 spin_unlock_irq(&host->lock);
833 return BLK_STS_OK;
834 }
835
836 static blk_status_t carm_queue_rq(struct blk_mq_hw_ctx *hctx,
837 const struct blk_mq_queue_data *bd)
838 {
839 struct request_queue *q = hctx->queue;
840 struct carm_port *port = q->queuedata;
841 struct carm_host *host = port->host;
842 struct carm_msg_rw *msg;
843 struct carm_request *crq;
844 struct request *rq = bd->rq;
845 struct scatterlist *sg;
846 int writing = 0, pci_dir, i, n_elem, rc;
847 u32 tmp;
848 unsigned int msg_size;
849
850 blk_mq_start_request(rq);
851
852 spin_lock_irq(&host->lock);
853
854 crq = carm_get_request(host);
855 if (!crq) {
856 carm_push_q(host, q);
857 spin_unlock_irq(&host->lock);
858 return BLK_STS_DEV_RESOURCE;
859 }
860 crq->rq = rq;
861
862 if (rq_data_dir(rq) == WRITE) {
863 writing = 1;
864 pci_dir = DMA_TO_DEVICE;
865 } else {
866 pci_dir = DMA_FROM_DEVICE;
867 }
868
869 /* get scatterlist from block layer */
870 sg = &crq->sg[0];
871 n_elem = blk_rq_map_sg(q, rq, sg);
872 if (n_elem <= 0) {
873 /* request with no s/g entries? */
874 carm_end_rq(host, crq, BLK_STS_IOERR);
875 spin_unlock_irq(&host->lock);
876 return BLK_STS_IOERR;
877 }
878
879 /* map scatterlist to PCI bus addresses */
880 n_elem = dma_map_sg(&host->pdev->dev, sg, n_elem, pci_dir);
881 if (n_elem <= 0) {
882 /* request with no s/g entries? */
883 carm_end_rq(host, crq, BLK_STS_IOERR);
884 spin_unlock_irq(&host->lock);
885 return BLK_STS_IOERR;
886 }
887 crq->n_elem = n_elem;
888 crq->port = port;
889 host->hw_sg_used += n_elem;
890
891 /*
892 * build read/write message
893 */
894
895 VPRINTK("build msg\n");
896 msg = (struct carm_msg_rw *) carm_ref_msg(host, crq->tag);
897
898 if (writing) {
899 msg->type = CARM_MSG_WRITE;
900 crq->msg_type = CARM_MSG_WRITE;
901 } else {
902 msg->type = CARM_MSG_READ;
903 crq->msg_type = CARM_MSG_READ;
904 }
905
906 msg->id = port->port_no;
907 msg->sg_count = n_elem;
908 msg->sg_type = SGT_32BIT;
909 msg->handle = cpu_to_le32(TAG_ENCODE(crq->tag));
910 msg->lba = cpu_to_le32(blk_rq_pos(rq) & 0xffffffff);
911 tmp = (blk_rq_pos(rq) >> 16) >> 16;
912 msg->lba_high = cpu_to_le16( (u16) tmp );
913 msg->lba_count = cpu_to_le16(blk_rq_sectors(rq));
914
915 msg_size = sizeof(struct carm_msg_rw) - sizeof(msg->sg);
916 for (i = 0; i < n_elem; i++) {
917 struct carm_msg_sg *carm_sg = &msg->sg[i];
918 carm_sg->start = cpu_to_le32(sg_dma_address(&crq->sg[i]));
919 carm_sg->len = cpu_to_le32(sg_dma_len(&crq->sg[i]));
920 msg_size += sizeof(struct carm_msg_sg);
921 }
922
923 rc = carm_lookup_bucket(msg_size);
924 BUG_ON(rc < 0);
925 crq->msg_bucket = (u32) rc;
926
927 /*
928 * queue read/write message to hardware
929 */
930
931 VPRINTK("send msg, tag == %u\n", crq->tag);
932 rc = carm_send_msg(host, crq);
933 if (rc) {
934 carm_put_request(host, crq);
935 carm_push_q(host, q);
936 spin_unlock_irq(&host->lock);
937 return BLK_STS_DEV_RESOURCE;
938 }
939
940 spin_unlock_irq(&host->lock);
941 return BLK_STS_OK;
942 }
943
944 static void carm_handle_array_info(struct carm_host *host,
945 struct carm_request *crq, u8 *mem,
946 blk_status_t error)
947 {
948 struct carm_port *port;
949 u8 *msg_data = mem + sizeof(struct carm_array_info);
950 struct carm_array_info *desc = (struct carm_array_info *) msg_data;
951 u64 lo, hi;
952 int cur_port;
953 size_t slen;
954
955 DPRINTK("ENTER\n");
956
957 carm_end_rq(host, crq, error);
958
959 if (error)
960 goto out;
961 if (le32_to_cpu(desc->array_status) & ARRAY_NO_EXIST)
962 goto out;
963
964 cur_port = host->cur_scan_dev;
965
966 /* should never occur */
967 if ((cur_port < 0) || (cur_port >= CARM_MAX_PORTS)) {
968 printk(KERN_ERR PFX "BUG: cur_scan_dev==%d, array_id==%d\n",
969 cur_port, (int) desc->array_id);
970 goto out;
971 }
972
973 port = &host->port[cur_port];
974
975 lo = (u64) le32_to_cpu(desc->size);
976 hi = (u64) le16_to_cpu(desc->size_hi);
977
978 port->capacity = lo | (hi << 32);
979 port->dev_geom_head = le16_to_cpu(desc->head);
980 port->dev_geom_sect = le16_to_cpu(desc->sect);
981 port->dev_geom_cyl = le16_to_cpu(desc->cyl);
982
983 host->dev_active |= (1 << cur_port);
984
985 strncpy(port->name, desc->name, sizeof(port->name));
986 port->name[sizeof(port->name) - 1] = 0;
987 slen = strlen(port->name);
988 while (slen && (port->name[slen - 1] == ' ')) {
989 port->name[slen - 1] = 0;
990 slen--;
991 }
992
993 printk(KERN_INFO DRV_NAME "(%s): port %u device %Lu sectors\n",
994 pci_name(host->pdev), port->port_no,
995 (unsigned long long) port->capacity);
996 printk(KERN_INFO DRV_NAME "(%s): port %u device \"%s\"\n",
997 pci_name(host->pdev), port->port_no, port->name);
998
999 out:
1000 assert(host->state == HST_DEV_SCAN);
1001 schedule_work(&host->fsm_task);
1002 }
1003
1004 static void carm_handle_scan_chan(struct carm_host *host,
1005 struct carm_request *crq, u8 *mem,
1006 blk_status_t error)
1007 {
1008 u8 *msg_data = mem + IOC_SCAN_CHAN_OFFSET;
1009 unsigned int i, dev_count = 0;
1010 int new_state = HST_DEV_SCAN_START;
1011
1012 DPRINTK("ENTER\n");
1013
1014 carm_end_rq(host, crq, error);
1015
1016 if (error) {
1017 new_state = HST_ERROR;
1018 goto out;
1019 }
1020
1021 /* TODO: scan and support non-disk devices */
1022 for (i = 0; i < 8; i++)
1023 if (msg_data[i] == 0) { /* direct-access device (disk) */
1024 host->dev_present |= (1 << i);
1025 dev_count++;
1026 }
1027
1028 printk(KERN_INFO DRV_NAME "(%s): found %u interesting devices\n",
1029 pci_name(host->pdev), dev_count);
1030
1031 out:
1032 assert(host->state == HST_PORT_SCAN);
1033 host->state = new_state;
1034 schedule_work(&host->fsm_task);
1035 }
1036
1037 static void carm_handle_generic(struct carm_host *host,
1038 struct carm_request *crq, blk_status_t error,
1039 int cur_state, int next_state)
1040 {
1041 DPRINTK("ENTER\n");
1042
1043 carm_end_rq(host, crq, error);
1044
1045 assert(host->state == cur_state);
1046 if (error)
1047 host->state = HST_ERROR;
1048 else
1049 host->state = next_state;
1050 schedule_work(&host->fsm_task);
1051 }
1052
1053 static inline void carm_handle_rw(struct carm_host *host,
1054 struct carm_request *crq, blk_status_t error)
1055 {
1056 int pci_dir;
1057
1058 VPRINTK("ENTER\n");
1059
1060 if (rq_data_dir(crq->rq) == WRITE)
1061 pci_dir = DMA_TO_DEVICE;
1062 else
1063 pci_dir = DMA_FROM_DEVICE;
1064
1065 dma_unmap_sg(&host->pdev->dev, &crq->sg[0], crq->n_elem, pci_dir);
1066
1067 carm_end_rq(host, crq, error);
1068 }
1069
1070 static inline void carm_handle_resp(struct carm_host *host,
1071 __le32 ret_handle_le, u32 status)
1072 {
1073 u32 handle = le32_to_cpu(ret_handle_le);
1074 unsigned int msg_idx;
1075 struct carm_request *crq;
1076 blk_status_t error = (status == RMSG_OK) ? 0 : BLK_STS_IOERR;
1077 u8 *mem;
1078
1079 VPRINTK("ENTER, handle == 0x%x\n", handle);
1080
1081 if (unlikely(!TAG_VALID(handle))) {
1082 printk(KERN_ERR DRV_NAME "(%s): BUG: invalid tag 0x%x\n",
1083 pci_name(host->pdev), handle);
1084 return;
1085 }
1086
1087 msg_idx = TAG_DECODE(handle);
1088 VPRINTK("tag == %u\n", msg_idx);
1089
1090 crq = &host->req[msg_idx];
1091
1092 /* fast path */
1093 if (likely(crq->msg_type == CARM_MSG_READ ||
1094 crq->msg_type == CARM_MSG_WRITE)) {
1095 carm_handle_rw(host, crq, error);
1096 return;
1097 }
1098
1099 mem = carm_ref_msg(host, msg_idx);
1100
1101 switch (crq->msg_type) {
1102 case CARM_MSG_IOCTL: {
1103 switch (crq->msg_subtype) {
1104 case CARM_IOC_SCAN_CHAN:
1105 carm_handle_scan_chan(host, crq, mem, error);
1106 break;
1107 default:
1108 /* unknown / invalid response */
1109 goto err_out;
1110 }
1111 break;
1112 }
1113
1114 case CARM_MSG_MISC: {
1115 switch (crq->msg_subtype) {
1116 case MISC_ALLOC_MEM:
1117 carm_handle_generic(host, crq, error,
1118 HST_ALLOC_BUF, HST_SYNC_TIME);
1119 break;
1120 case MISC_SET_TIME:
1121 carm_handle_generic(host, crq, error,
1122 HST_SYNC_TIME, HST_GET_FW_VER);
1123 break;
1124 case MISC_GET_FW_VER: {
1125 struct carm_fw_ver *ver = (struct carm_fw_ver *)
1126 (mem + sizeof(struct carm_msg_get_fw_ver));
1127 if (!error) {
1128 host->fw_ver = le32_to_cpu(ver->version);
1129 host->flags |= (ver->features & FL_FW_VER_MASK);
1130 }
1131 carm_handle_generic(host, crq, error,
1132 HST_GET_FW_VER, HST_PORT_SCAN);
1133 break;
1134 }
1135 default:
1136 /* unknown / invalid response */
1137 goto err_out;
1138 }
1139 break;
1140 }
1141
1142 case CARM_MSG_ARRAY: {
1143 switch (crq->msg_subtype) {
1144 case CARM_ARRAY_INFO:
1145 carm_handle_array_info(host, crq, mem, error);
1146 break;
1147 default:
1148 /* unknown / invalid response */
1149 goto err_out;
1150 }
1151 break;
1152 }
1153
1154 default:
1155 /* unknown / invalid response */
1156 goto err_out;
1157 }
1158
1159 return;
1160
1161 err_out:
1162 printk(KERN_WARNING DRV_NAME "(%s): BUG: unhandled message type %d/%d\n",
1163 pci_name(host->pdev), crq->msg_type, crq->msg_subtype);
1164 carm_end_rq(host, crq, BLK_STS_IOERR);
1165 }
1166
1167 static inline void carm_handle_responses(struct carm_host *host)
1168 {
1169 void __iomem *mmio = host->mmio;
1170 struct carm_response *resp = (struct carm_response *) host->shm;
1171 unsigned int work = 0;
1172 unsigned int idx = host->resp_idx % RMSG_Q_LEN;
1173
1174 while (1) {
1175 u32 status = le32_to_cpu(resp[idx].status);
1176
1177 if (status == 0xffffffff) {
1178 VPRINTK("ending response on index %u\n", idx);
1179 writel(idx << 3, mmio + CARM_RESP_IDX);
1180 break;
1181 }
1182
1183 /* response to a message we sent */
1184 else if ((status & (1 << 31)) == 0) {
1185 VPRINTK("handling msg response on index %u\n", idx);
1186 carm_handle_resp(host, resp[idx].ret_handle, status);
1187 resp[idx].status = cpu_to_le32(0xffffffff);
1188 }
1189
1190 /* asynchronous events the hardware throws our way */
1191 else if ((status & 0xff000000) == (1 << 31)) {
1192 u8 *evt_type_ptr = (u8 *) &resp[idx];
1193 u8 evt_type = *evt_type_ptr;
1194 printk(KERN_WARNING DRV_NAME "(%s): unhandled event type %d\n",
1195 pci_name(host->pdev), (int) evt_type);
1196 resp[idx].status = cpu_to_le32(0xffffffff);
1197 }
1198
1199 idx = NEXT_RESP(idx);
1200 work++;
1201 }
1202
1203 VPRINTK("EXIT, work==%u\n", work);
1204 host->resp_idx += work;
1205 }
1206
1207 static irqreturn_t carm_interrupt(int irq, void *__host)
1208 {
1209 struct carm_host *host = __host;
1210 void __iomem *mmio;
1211 u32 mask;
1212 int handled = 0;
1213 unsigned long flags;
1214
1215 if (!host) {
1216 VPRINTK("no host\n");
1217 return IRQ_NONE;
1218 }
1219
1220 spin_lock_irqsave(&host->lock, flags);
1221
1222 mmio = host->mmio;
1223
1224 /* reading should also clear interrupts */
1225 mask = readl(mmio + CARM_INT_STAT);
1226
1227 if (mask == 0 || mask == 0xffffffff) {
1228 VPRINTK("no work, mask == 0x%x\n", mask);
1229 goto out;
1230 }
1231
1232 if (mask & INT_ACK_MASK)
1233 writel(mask, mmio + CARM_INT_STAT);
1234
1235 if (unlikely(host->state == HST_INVALID)) {
1236 VPRINTK("not initialized yet, mask = 0x%x\n", mask);
1237 goto out;
1238 }
1239
1240 if (mask & CARM_HAVE_RESP) {
1241 handled = 1;
1242 carm_handle_responses(host);
1243 }
1244
1245 out:
1246 spin_unlock_irqrestore(&host->lock, flags);
1247 VPRINTK("EXIT\n");
1248 return IRQ_RETVAL(handled);
1249 }
1250
1251 static void carm_fsm_task (struct work_struct *work)
1252 {
1253 struct carm_host *host =
1254 container_of(work, struct carm_host, fsm_task);
1255 unsigned long flags;
1256 unsigned int state;
1257 int rc, i, next_dev;
1258 int reschedule = 0;
1259 int new_state = HST_INVALID;
1260
1261 spin_lock_irqsave(&host->lock, flags);
1262 state = host->state;
1263 spin_unlock_irqrestore(&host->lock, flags);
1264
1265 DPRINTK("ENTER, state == %s\n", state_name[state]);
1266
1267 switch (state) {
1268 case HST_PROBE_START:
1269 new_state = HST_ALLOC_BUF;
1270 reschedule = 1;
1271 break;
1272
1273 case HST_ALLOC_BUF:
1274 rc = carm_send_special(host, carm_fill_alloc_buf);
1275 if (rc) {
1276 new_state = HST_ERROR;
1277 reschedule = 1;
1278 }
1279 break;
1280
1281 case HST_SYNC_TIME:
1282 rc = carm_send_special(host, carm_fill_sync_time);
1283 if (rc) {
1284 new_state = HST_ERROR;
1285 reschedule = 1;
1286 }
1287 break;
1288
1289 case HST_GET_FW_VER:
1290 rc = carm_send_special(host, carm_fill_get_fw_ver);
1291 if (rc) {
1292 new_state = HST_ERROR;
1293 reschedule = 1;
1294 }
1295 break;
1296
1297 case HST_PORT_SCAN:
1298 rc = carm_send_special(host, carm_fill_scan_channels);
1299 if (rc) {
1300 new_state = HST_ERROR;
1301 reschedule = 1;
1302 }
1303 break;
1304
1305 case HST_DEV_SCAN_START:
1306 host->cur_scan_dev = -1;
1307 new_state = HST_DEV_SCAN;
1308 reschedule = 1;
1309 break;
1310
1311 case HST_DEV_SCAN:
1312 next_dev = -1;
1313 for (i = host->cur_scan_dev + 1; i < CARM_MAX_PORTS; i++)
1314 if (host->dev_present & (1 << i)) {
1315 next_dev = i;
1316 break;
1317 }
1318
1319 if (next_dev >= 0) {
1320 host->cur_scan_dev = next_dev;
1321 rc = carm_array_info(host, next_dev);
1322 if (rc) {
1323 new_state = HST_ERROR;
1324 reschedule = 1;
1325 }
1326 } else {
1327 new_state = HST_DEV_ACTIVATE;
1328 reschedule = 1;
1329 }
1330 break;
1331
1332 case HST_DEV_ACTIVATE: {
1333 int activated = 0;
1334 for (i = 0; i < CARM_MAX_PORTS; i++)
1335 if (host->dev_active & (1 << i)) {
1336 struct carm_port *port = &host->port[i];
1337 struct gendisk *disk = port->disk;
1338
1339 set_capacity(disk, port->capacity);
1340 add_disk(disk);
1341 activated++;
1342 }
1343
1344 printk(KERN_INFO DRV_NAME "(%s): %d ports activated\n",
1345 pci_name(host->pdev), activated);
1346
1347 new_state = HST_PROBE_FINISHED;
1348 reschedule = 1;
1349 break;
1350 }
1351
1352 case HST_PROBE_FINISHED:
1353 complete(&host->probe_comp);
1354 break;
1355
1356 case HST_ERROR:
1357 /* FIXME: TODO */
1358 break;
1359
1360 default:
1361 /* should never occur */
1362 printk(KERN_ERR PFX "BUG: unknown state %d\n", state);
1363 assert(0);
1364 break;
1365 }
1366
1367 if (new_state != HST_INVALID) {
1368 spin_lock_irqsave(&host->lock, flags);
1369 host->state = new_state;
1370 spin_unlock_irqrestore(&host->lock, flags);
1371 }
1372 if (reschedule)
1373 schedule_work(&host->fsm_task);
1374 }
1375
1376 static int carm_init_wait(void __iomem *mmio, u32 bits, unsigned int test_bit)
1377 {
1378 unsigned int i;
1379
1380 for (i = 0; i < 50000; i++) {
1381 u32 tmp = readl(mmio + CARM_LMUC);
1382 udelay(100);
1383
1384 if (test_bit) {
1385 if ((tmp & bits) == bits)
1386 return 0;
1387 } else {
1388 if ((tmp & bits) == 0)
1389 return 0;
1390 }
1391
1392 cond_resched();
1393 }
1394
1395 printk(KERN_ERR PFX "carm_init_wait timeout, bits == 0x%x, test_bit == %s\n",
1396 bits, test_bit ? "yes" : "no");
1397 return -EBUSY;
1398 }
1399
1400 static void carm_init_responses(struct carm_host *host)
1401 {
1402 void __iomem *mmio = host->mmio;
1403 unsigned int i;
1404 struct carm_response *resp = (struct carm_response *) host->shm;
1405
1406 for (i = 0; i < RMSG_Q_LEN; i++)
1407 resp[i].status = cpu_to_le32(0xffffffff);
1408
1409 writel(0, mmio + CARM_RESP_IDX);
1410 }
1411
1412 static int carm_init_host(struct carm_host *host)
1413 {
1414 void __iomem *mmio = host->mmio;
1415 u32 tmp;
1416 u8 tmp8;
1417 int rc;
1418
1419 DPRINTK("ENTER\n");
1420
1421 writel(0, mmio + CARM_INT_MASK);
1422
1423 tmp8 = readb(mmio + CARM_INITC);
1424 if (tmp8 & 0x01) {
1425 tmp8 &= ~0x01;
1426 writeb(tmp8, mmio + CARM_INITC);
1427 readb(mmio + CARM_INITC); /* flush */
1428
1429 DPRINTK("snooze...\n");
1430 msleep(5000);
1431 }
1432
1433 tmp = readl(mmio + CARM_HMUC);
1434 if (tmp & CARM_CME) {
1435 DPRINTK("CME bit present, waiting\n");
1436 rc = carm_init_wait(mmio, CARM_CME, 1);
1437 if (rc) {
1438 DPRINTK("EXIT, carm_init_wait 1 failed\n");
1439 return rc;
1440 }
1441 }
1442 if (tmp & CARM_RME) {
1443 DPRINTK("RME bit present, waiting\n");
1444 rc = carm_init_wait(mmio, CARM_RME, 1);
1445 if (rc) {
1446 DPRINTK("EXIT, carm_init_wait 2 failed\n");
1447 return rc;
1448 }
1449 }
1450
1451 tmp &= ~(CARM_RME | CARM_CME);
1452 writel(tmp, mmio + CARM_HMUC);
1453 readl(mmio + CARM_HMUC); /* flush */
1454
1455 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 0);
1456 if (rc) {
1457 DPRINTK("EXIT, carm_init_wait 3 failed\n");
1458 return rc;
1459 }
1460
1461 carm_init_buckets(mmio);
1462
1463 writel(host->shm_dma & 0xffffffff, mmio + RBUF_ADDR_LO);
1464 writel((host->shm_dma >> 16) >> 16, mmio + RBUF_ADDR_HI);
1465 writel(RBUF_LEN, mmio + RBUF_BYTE_SZ);
1466
1467 tmp = readl(mmio + CARM_HMUC);
1468 tmp |= (CARM_RME | CARM_CME | CARM_WZBC);
1469 writel(tmp, mmio + CARM_HMUC);
1470 readl(mmio + CARM_HMUC); /* flush */
1471
1472 rc = carm_init_wait(mmio, CARM_RME | CARM_CME, 1);
1473 if (rc) {
1474 DPRINTK("EXIT, carm_init_wait 4 failed\n");
1475 return rc;
1476 }
1477
1478 writel(0, mmio + CARM_HMPHA);
1479 writel(INT_DEF_MASK, mmio + CARM_INT_MASK);
1480
1481 carm_init_responses(host);
1482
1483 /* start initialization, probing state machine */
1484 spin_lock_irq(&host->lock);
1485 assert(host->state == HST_INVALID);
1486 host->state = HST_PROBE_START;
1487 spin_unlock_irq(&host->lock);
1488 schedule_work(&host->fsm_task);
1489
1490 DPRINTK("EXIT\n");
1491 return 0;
1492 }
1493
1494 static const struct blk_mq_ops carm_oob_mq_ops = {
1495 .queue_rq = carm_oob_queue_rq,
1496 };
1497
1498 static const struct blk_mq_ops carm_mq_ops = {
1499 .queue_rq = carm_queue_rq,
1500 };
1501
1502 static int carm_init_disks(struct carm_host *host)
1503 {
1504 unsigned int i;
1505 int rc = 0;
1506
1507 for (i = 0; i < CARM_MAX_PORTS; i++) {
1508 struct gendisk *disk;
1509 struct request_queue *q;
1510 struct carm_port *port;
1511
1512 port = &host->port[i];
1513 port->host = host;
1514 port->port_no = i;
1515
1516 disk = alloc_disk(CARM_MINORS_PER_MAJOR);
1517 if (!disk) {
1518 rc = -ENOMEM;
1519 break;
1520 }
1521
1522 port->disk = disk;
1523 sprintf(disk->disk_name, DRV_NAME "/%u",
1524 (unsigned int) (host->id * CARM_MAX_PORTS) + i);
1525 disk->major = host->major;
1526 disk->first_minor = i * CARM_MINORS_PER_MAJOR;
1527 disk->fops = &carm_bd_ops;
1528 disk->private_data = port;
1529
1530 q = blk_mq_init_sq_queue(&port->tag_set, &carm_mq_ops,
1531 max_queue, BLK_MQ_F_SHOULD_MERGE);
1532 if (IS_ERR(q)) {
1533 rc = PTR_ERR(q);
1534 break;
1535 }
1536 disk->queue = q;
1537 blk_queue_max_segments(q, CARM_MAX_REQ_SG);
1538 blk_queue_segment_boundary(q, CARM_SG_BOUNDARY);
1539
1540 q->queuedata = port;
1541 }
1542
1543 return rc;
1544 }
1545
1546 static void carm_free_disks(struct carm_host *host)
1547 {
1548 unsigned int i;
1549
1550 for (i = 0; i < CARM_MAX_PORTS; i++) {
1551 struct carm_port *port = &host->port[i];
1552 struct gendisk *disk = port->disk;
1553
1554 if (disk) {
1555 struct request_queue *q = disk->queue;
1556
1557 if (disk->flags & GENHD_FL_UP)
1558 del_gendisk(disk);
1559 if (q) {
1560 blk_mq_free_tag_set(&port->tag_set);
1561 blk_cleanup_queue(q);
1562 }
1563 put_disk(disk);
1564 }
1565 }
1566 }
1567
1568 static int carm_init_shm(struct carm_host *host)
1569 {
1570 host->shm = dma_alloc_coherent(&host->pdev->dev, CARM_SHM_SIZE,
1571 &host->shm_dma, GFP_KERNEL);
1572 if (!host->shm)
1573 return -ENOMEM;
1574
1575 host->msg_base = host->shm + RBUF_LEN;
1576 host->msg_dma = host->shm_dma + RBUF_LEN;
1577
1578 memset(host->shm, 0xff, RBUF_LEN);
1579 memset(host->msg_base, 0, PDC_SHM_SIZE - RBUF_LEN);
1580
1581 return 0;
1582 }
1583
1584 static int carm_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1585 {
1586 struct carm_host *host;
1587 int rc;
1588 struct request_queue *q;
1589 unsigned int i;
1590
1591 printk_once(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1592
1593 rc = pci_enable_device(pdev);
1594 if (rc)
1595 return rc;
1596
1597 rc = pci_request_regions(pdev, DRV_NAME);
1598 if (rc)
1599 goto err_out;
1600
1601 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
1602 if (rc) {
1603 printk(KERN_ERR DRV_NAME "(%s): DMA mask failure\n",
1604 pci_name(pdev));
1605 goto err_out_regions;
1606 }
1607
1608 host = kzalloc(sizeof(*host), GFP_KERNEL);
1609 if (!host) {
1610 printk(KERN_ERR DRV_NAME "(%s): memory alloc failure\n",
1611 pci_name(pdev));
1612 rc = -ENOMEM;
1613 goto err_out_regions;
1614 }
1615
1616 host->pdev = pdev;
1617 spin_lock_init(&host->lock);
1618 INIT_WORK(&host->fsm_task, carm_fsm_task);
1619 init_completion(&host->probe_comp);
1620
1621 for (i = 0; i < ARRAY_SIZE(host->req); i++)
1622 host->req[i].tag = i;
1623
1624 host->mmio = ioremap(pci_resource_start(pdev, 0),
1625 pci_resource_len(pdev, 0));
1626 if (!host->mmio) {
1627 printk(KERN_ERR DRV_NAME "(%s): MMIO alloc failure\n",
1628 pci_name(pdev));
1629 rc = -ENOMEM;
1630 goto err_out_kfree;
1631 }
1632
1633 rc = carm_init_shm(host);
1634 if (rc) {
1635 printk(KERN_ERR DRV_NAME "(%s): DMA SHM alloc failure\n",
1636 pci_name(pdev));
1637 goto err_out_iounmap;
1638 }
1639
1640 q = blk_mq_init_sq_queue(&host->tag_set, &carm_oob_mq_ops, 1,
1641 BLK_MQ_F_NO_SCHED);
1642 if (IS_ERR(q)) {
1643 printk(KERN_ERR DRV_NAME "(%s): OOB queue alloc failure\n",
1644 pci_name(pdev));
1645 rc = PTR_ERR(q);
1646 goto err_out_dma_free;
1647 }
1648 host->oob_q = q;
1649 q->queuedata = host;
1650
1651 /*
1652 * Figure out which major to use: 160, 161, or dynamic
1653 */
1654 if (!test_and_set_bit(0, &carm_major_alloc))
1655 host->major = 160;
1656 else if (!test_and_set_bit(1, &carm_major_alloc))
1657 host->major = 161;
1658 else
1659 host->flags |= FL_DYN_MAJOR;
1660
1661 host->id = carm_host_id;
1662 sprintf(host->name, DRV_NAME "%d", carm_host_id);
1663
1664 rc = register_blkdev(host->major, host->name);
1665 if (rc < 0)
1666 goto err_out_free_majors;
1667 if (host->flags & FL_DYN_MAJOR)
1668 host->major = rc;
1669
1670 rc = carm_init_disks(host);
1671 if (rc)
1672 goto err_out_blkdev_disks;
1673
1674 pci_set_master(pdev);
1675
1676 rc = request_irq(pdev->irq, carm_interrupt, IRQF_SHARED, DRV_NAME, host);
1677 if (rc) {
1678 printk(KERN_ERR DRV_NAME "(%s): irq alloc failure\n",
1679 pci_name(pdev));
1680 goto err_out_blkdev_disks;
1681 }
1682
1683 rc = carm_init_host(host);
1684 if (rc)
1685 goto err_out_free_irq;
1686
1687 DPRINTK("waiting for probe_comp\n");
1688 wait_for_completion(&host->probe_comp);
1689
1690 printk(KERN_INFO "%s: pci %s, ports %d, io %llx, irq %u, major %d\n",
1691 host->name, pci_name(pdev), (int) CARM_MAX_PORTS,
1692 (unsigned long long)pci_resource_start(pdev, 0),
1693 pdev->irq, host->major);
1694
1695 carm_host_id++;
1696 pci_set_drvdata(pdev, host);
1697 return 0;
1698
1699 err_out_free_irq:
1700 free_irq(pdev->irq, host);
1701 err_out_blkdev_disks:
1702 carm_free_disks(host);
1703 unregister_blkdev(host->major, host->name);
1704 err_out_free_majors:
1705 if (host->major == 160)
1706 clear_bit(0, &carm_major_alloc);
1707 else if (host->major == 161)
1708 clear_bit(1, &carm_major_alloc);
1709 blk_cleanup_queue(host->oob_q);
1710 blk_mq_free_tag_set(&host->tag_set);
1711 err_out_dma_free:
1712 dma_free_coherent(&pdev->dev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1713 err_out_iounmap:
1714 iounmap(host->mmio);
1715 err_out_kfree:
1716 kfree(host);
1717 err_out_regions:
1718 pci_release_regions(pdev);
1719 err_out:
1720 pci_disable_device(pdev);
1721 return rc;
1722 }
1723
1724 static void carm_remove_one (struct pci_dev *pdev)
1725 {
1726 struct carm_host *host = pci_get_drvdata(pdev);
1727
1728 if (!host) {
1729 printk(KERN_ERR PFX "BUG: no host data for PCI(%s)\n",
1730 pci_name(pdev));
1731 return;
1732 }
1733
1734 free_irq(pdev->irq, host);
1735 carm_free_disks(host);
1736 unregister_blkdev(host->major, host->name);
1737 if (host->major == 160)
1738 clear_bit(0, &carm_major_alloc);
1739 else if (host->major == 161)
1740 clear_bit(1, &carm_major_alloc);
1741 blk_cleanup_queue(host->oob_q);
1742 blk_mq_free_tag_set(&host->tag_set);
1743 dma_free_coherent(&pdev->dev, CARM_SHM_SIZE, host->shm, host->shm_dma);
1744 iounmap(host->mmio);
1745 kfree(host);
1746 pci_release_regions(pdev);
1747 pci_disable_device(pdev);
1748 }
1749
1750 module_pci_driver(carm_driver);
Linux with added FPC-III support