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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / clk / rockchip / clk-rk3399.c
blob5a628148f3f02a641970962dfc864bf8859bf33a
1 /*
2 * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
3 * Author: Xing Zheng <zhengxing@rock-chips.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16 #include <linux/clk-provider.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <dt-bindings/clock/rk3399-cru.h>
22 #include "clk.h"
23
24 enum rk3399_plls {
25 lpll, bpll, dpll, cpll, gpll, npll, vpll,
26 };
27
28 enum rk3399_pmu_plls {
29 ppll,
30 };
31
32 static struct rockchip_pll_rate_table rk3399_pll_rates[] = {
33 /* _mhz, _refdiv, _fbdiv, _postdiv1, _postdiv2, _dsmpd, _frac */
34 RK3036_PLL_RATE(2208000000, 1, 92, 1, 1, 1, 0),
35 RK3036_PLL_RATE(2184000000, 1, 91, 1, 1, 1, 0),
36 RK3036_PLL_RATE(2160000000, 1, 90, 1, 1, 1, 0),
37 RK3036_PLL_RATE(2136000000, 1, 89, 1, 1, 1, 0),
38 RK3036_PLL_RATE(2112000000, 1, 88, 1, 1, 1, 0),
39 RK3036_PLL_RATE(2088000000, 1, 87, 1, 1, 1, 0),
40 RK3036_PLL_RATE(2064000000, 1, 86, 1, 1, 1, 0),
41 RK3036_PLL_RATE(2040000000, 1, 85, 1, 1, 1, 0),
42 RK3036_PLL_RATE(2016000000, 1, 84, 1, 1, 1, 0),
43 RK3036_PLL_RATE(1992000000, 1, 83, 1, 1, 1, 0),
44 RK3036_PLL_RATE(1968000000, 1, 82, 1, 1, 1, 0),
45 RK3036_PLL_RATE(1944000000, 1, 81, 1, 1, 1, 0),
46 RK3036_PLL_RATE(1920000000, 1, 80, 1, 1, 1, 0),
47 RK3036_PLL_RATE(1896000000, 1, 79, 1, 1, 1, 0),
48 RK3036_PLL_RATE(1872000000, 1, 78, 1, 1, 1, 0),
49 RK3036_PLL_RATE(1848000000, 1, 77, 1, 1, 1, 0),
50 RK3036_PLL_RATE(1824000000, 1, 76, 1, 1, 1, 0),
51 RK3036_PLL_RATE(1800000000, 1, 75, 1, 1, 1, 0),
52 RK3036_PLL_RATE(1776000000, 1, 74, 1, 1, 1, 0),
53 RK3036_PLL_RATE(1752000000, 1, 73, 1, 1, 1, 0),
54 RK3036_PLL_RATE(1728000000, 1, 72, 1, 1, 1, 0),
55 RK3036_PLL_RATE(1704000000, 1, 71, 1, 1, 1, 0),
56 RK3036_PLL_RATE(1680000000, 1, 70, 1, 1, 1, 0),
57 RK3036_PLL_RATE(1656000000, 1, 69, 1, 1, 1, 0),
58 RK3036_PLL_RATE(1632000000, 1, 68, 1, 1, 1, 0),
59 RK3036_PLL_RATE(1608000000, 1, 67, 1, 1, 1, 0),
60 RK3036_PLL_RATE(1600000000, 3, 200, 1, 1, 1, 0),
61 RK3036_PLL_RATE(1584000000, 1, 66, 1, 1, 1, 0),
62 RK3036_PLL_RATE(1560000000, 1, 65, 1, 1, 1, 0),
63 RK3036_PLL_RATE(1536000000, 1, 64, 1, 1, 1, 0),
64 RK3036_PLL_RATE(1512000000, 1, 63, 1, 1, 1, 0),
65 RK3036_PLL_RATE(1488000000, 1, 62, 1, 1, 1, 0),
66 RK3036_PLL_RATE(1464000000, 1, 61, 1, 1, 1, 0),
67 RK3036_PLL_RATE(1440000000, 1, 60, 1, 1, 1, 0),
68 RK3036_PLL_RATE(1416000000, 1, 59, 1, 1, 1, 0),
69 RK3036_PLL_RATE(1392000000, 1, 58, 1, 1, 1, 0),
70 RK3036_PLL_RATE(1368000000, 1, 57, 1, 1, 1, 0),
71 RK3036_PLL_RATE(1344000000, 1, 56, 1, 1, 1, 0),
72 RK3036_PLL_RATE(1320000000, 1, 55, 1, 1, 1, 0),
73 RK3036_PLL_RATE(1296000000, 1, 54, 1, 1, 1, 0),
74 RK3036_PLL_RATE(1272000000, 1, 53, 1, 1, 1, 0),
75 RK3036_PLL_RATE(1248000000, 1, 52, 1, 1, 1, 0),
76 RK3036_PLL_RATE(1200000000, 1, 50, 1, 1, 1, 0),
77 RK3036_PLL_RATE(1188000000, 2, 99, 1, 1, 1, 0),
78 RK3036_PLL_RATE(1104000000, 1, 46, 1, 1, 1, 0),
79 RK3036_PLL_RATE(1100000000, 12, 550, 1, 1, 1, 0),
80 RK3036_PLL_RATE(1008000000, 1, 84, 2, 1, 1, 0),
81 RK3036_PLL_RATE(1000000000, 1, 125, 3, 1, 1, 0),
82 RK3036_PLL_RATE( 984000000, 1, 82, 2, 1, 1, 0),
83 RK3036_PLL_RATE( 960000000, 1, 80, 2, 1, 1, 0),
84 RK3036_PLL_RATE( 936000000, 1, 78, 2, 1, 1, 0),
85 RK3036_PLL_RATE( 912000000, 1, 76, 2, 1, 1, 0),
86 RK3036_PLL_RATE( 900000000, 4, 300, 2, 1, 1, 0),
87 RK3036_PLL_RATE( 888000000, 1, 74, 2, 1, 1, 0),
88 RK3036_PLL_RATE( 864000000, 1, 72, 2, 1, 1, 0),
89 RK3036_PLL_RATE( 840000000, 1, 70, 2, 1, 1, 0),
90 RK3036_PLL_RATE( 816000000, 1, 68, 2, 1, 1, 0),
91 RK3036_PLL_RATE( 800000000, 1, 100, 3, 1, 1, 0),
92 RK3036_PLL_RATE( 700000000, 6, 350, 2, 1, 1, 0),
93 RK3036_PLL_RATE( 696000000, 1, 58, 2, 1, 1, 0),
94 RK3036_PLL_RATE( 676000000, 3, 169, 2, 1, 1, 0),
95 RK3036_PLL_RATE( 600000000, 1, 75, 3, 1, 1, 0),
96 RK3036_PLL_RATE( 594000000, 1, 99, 4, 1, 1, 0),
97 RK3036_PLL_RATE( 533250000, 8, 711, 4, 1, 1, 0),
98 RK3036_PLL_RATE( 504000000, 1, 63, 3, 1, 1, 0),
99 RK3036_PLL_RATE( 500000000, 6, 250, 2, 1, 1, 0),
100 RK3036_PLL_RATE( 408000000, 1, 68, 2, 2, 1, 0),
101 RK3036_PLL_RATE( 312000000, 1, 52, 2, 2, 1, 0),
102 RK3036_PLL_RATE( 297000000, 1, 99, 4, 2, 1, 0),
103 RK3036_PLL_RATE( 216000000, 1, 72, 4, 2, 1, 0),
104 RK3036_PLL_RATE( 148500000, 1, 99, 4, 4, 1, 0),
105 RK3036_PLL_RATE( 106500000, 1, 71, 4, 4, 1, 0),
106 RK3036_PLL_RATE( 96000000, 1, 64, 4, 4, 1, 0),
107 RK3036_PLL_RATE( 74250000, 2, 99, 4, 4, 1, 0),
108 RK3036_PLL_RATE( 65000000, 1, 65, 6, 4, 1, 0),
109 RK3036_PLL_RATE( 54000000, 1, 54, 6, 4, 1, 0),
110 RK3036_PLL_RATE( 27000000, 1, 27, 6, 4, 1, 0),
111 { /* sentinel */ },
112 };
113
114 /* CRU parents */
115 PNAME(mux_pll_p) = { "xin24m", "xin32k" };
116
117 PNAME(mux_armclkl_p) = { "clk_core_l_lpll_src",
118 "clk_core_l_bpll_src",
119 "clk_core_l_dpll_src",
120 "clk_core_l_gpll_src" };
121 PNAME(mux_armclkb_p) = { "clk_core_b_lpll_src",
122 "clk_core_b_bpll_src",
123 "clk_core_b_dpll_src",
124 "clk_core_b_gpll_src" };
125 PNAME(mux_ddrclk_p) = { "clk_ddrc_lpll_src",
126 "clk_ddrc_bpll_src",
127 "clk_ddrc_dpll_src",
128 "clk_ddrc_gpll_src" };
129 PNAME(mux_aclk_cci_p) = { "cpll_aclk_cci_src",
130 "gpll_aclk_cci_src",
131 "npll_aclk_cci_src",
132 "vpll_aclk_cci_src" };
133 PNAME(mux_cci_trace_p) = { "cpll_cci_trace",
134 "gpll_cci_trace" };
135 PNAME(mux_cs_p) = { "cpll_cs", "gpll_cs",
136 "npll_cs"};
137 PNAME(mux_aclk_perihp_p) = { "cpll_aclk_perihp_src",
138 "gpll_aclk_perihp_src" };
139
140 PNAME(mux_pll_src_cpll_gpll_p) = { "cpll", "gpll" };
141 PNAME(mux_pll_src_cpll_gpll_npll_p) = { "cpll", "gpll", "npll" };
142 PNAME(mux_pll_src_cpll_gpll_ppll_p) = { "cpll", "gpll", "ppll" };
143 PNAME(mux_pll_src_cpll_gpll_upll_p) = { "cpll", "gpll", "upll" };
144 PNAME(mux_pll_src_npll_cpll_gpll_p) = { "npll", "cpll", "gpll" };
145 PNAME(mux_pll_src_cpll_gpll_npll_ppll_p) = { "cpll", "gpll", "npll",
146 "ppll" };
147 PNAME(mux_pll_src_cpll_gpll_npll_24m_p) = { "cpll", "gpll", "npll",
148 "xin24m" };
149 PNAME(mux_pll_src_cpll_gpll_npll_usbphy480m_p) = { "cpll", "gpll", "npll",
150 "clk_usbphy_480m" };
151 PNAME(mux_pll_src_ppll_cpll_gpll_npll_p) = { "ppll", "cpll", "gpll",
152 "npll", "upll" };
153 PNAME(mux_pll_src_cpll_gpll_npll_upll_24m_p) = { "cpll", "gpll", "npll",
154 "upll", "xin24m" };
155 PNAME(mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p) = { "cpll", "gpll", "npll",
156 "ppll", "upll", "xin24m" };
157
158 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
159 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
160 "npll" };
161 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
162 "xin24m" };
163
164 PNAME(mux_dclk_vop0_p) = { "dclk_vop0_div",
165 "dclk_vop0_frac" };
166 PNAME(mux_dclk_vop1_p) = { "dclk_vop1_div",
167 "dclk_vop1_frac" };
168
169 PNAME(mux_clk_cif_p) = { "clk_cifout_src", "xin24m" };
170
171 PNAME(mux_pll_src_24m_usbphy480m_p) = { "xin24m", "clk_usbphy_480m" };
172 PNAME(mux_pll_src_24m_pciephy_p) = { "xin24m", "clk_pciephy_ref100m" };
173 PNAME(mux_pll_src_24m_32k_cpll_gpll_p) = { "xin24m", "xin32k",
174 "cpll", "gpll" };
175 PNAME(mux_pciecore_cru_phy_p) = { "clk_pcie_core_cru",
176 "clk_pcie_core_phy" };
177
178 PNAME(mux_aclk_emmc_p) = { "cpll_aclk_emmc_src",
179 "gpll_aclk_emmc_src" };
180
181 PNAME(mux_aclk_perilp0_p) = { "cpll_aclk_perilp0_src",
182 "gpll_aclk_perilp0_src" };
183
184 PNAME(mux_fclk_cm0s_p) = { "cpll_fclk_cm0s_src",
185 "gpll_fclk_cm0s_src" };
186
187 PNAME(mux_hclk_perilp1_p) = { "cpll_hclk_perilp1_src",
188 "gpll_hclk_perilp1_src" };
189
190 PNAME(mux_clk_testout1_p) = { "clk_testout1_pll_src", "xin24m" };
191 PNAME(mux_clk_testout2_p) = { "clk_testout2_pll_src", "xin24m" };
192
193 PNAME(mux_usbphy_480m_p) = { "clk_usbphy0_480m_src",
194 "clk_usbphy1_480m_src" };
195 PNAME(mux_aclk_gmac_p) = { "cpll_aclk_gmac_src",
196 "gpll_aclk_gmac_src" };
197 PNAME(mux_rmii_p) = { "clk_gmac", "clkin_gmac" };
198 PNAME(mux_spdif_p) = { "clk_spdif_div", "clk_spdif_frac",
199 "clkin_i2s", "xin12m" };
200 PNAME(mux_i2s0_p) = { "clk_i2s0_div", "clk_i2s0_frac",
201 "clkin_i2s", "xin12m" };
202 PNAME(mux_i2s1_p) = { "clk_i2s1_div", "clk_i2s1_frac",
203 "clkin_i2s", "xin12m" };
204 PNAME(mux_i2s2_p) = { "clk_i2s2_div", "clk_i2s2_frac",
205 "clkin_i2s", "xin12m" };
206 PNAME(mux_i2sch_p) = { "clk_i2s0", "clk_i2s1",
207 "clk_i2s2" };
208 PNAME(mux_i2sout_p) = { "clk_i2sout_src", "xin12m" };
209
210 PNAME(mux_uart0_p) = { "clk_uart0_div", "clk_uart0_frac", "xin24m" };
211 PNAME(mux_uart1_p) = { "clk_uart1_div", "clk_uart1_frac", "xin24m" };
212 PNAME(mux_uart2_p) = { "clk_uart2_div", "clk_uart2_frac", "xin24m" };
213 PNAME(mux_uart3_p) = { "clk_uart3_div", "clk_uart3_frac", "xin24m" };
214
215 /* PMU CRU parents */
216 PNAME(mux_ppll_24m_p) = { "ppll", "xin24m" };
217 PNAME(mux_24m_ppll_p) = { "xin24m", "ppll" };
218 PNAME(mux_fclk_cm0s_pmu_ppll_p) = { "fclk_cm0s_pmu_ppll_src", "xin24m" };
219 PNAME(mux_wifi_pmu_p) = { "clk_wifi_div", "clk_wifi_frac" };
220 PNAME(mux_uart4_pmu_p) = { "clk_uart4_div", "clk_uart4_frac",
221 "xin24m" };
222 PNAME(mux_clk_testout2_2io_p) = { "clk_testout2", "clk_32k_suspend_pmu" };
223
224 static struct rockchip_pll_clock rk3399_pll_clks[] __initdata = {
225 [lpll] = PLL(pll_rk3399, PLL_APLLL, "lpll", mux_pll_p, 0, RK3399_PLL_CON(0),
226 RK3399_PLL_CON(3), 8, 31, 0, rk3399_pll_rates),
227 [bpll] = PLL(pll_rk3399, PLL_APLLB, "bpll", mux_pll_p, 0, RK3399_PLL_CON(8),
228 RK3399_PLL_CON(11), 8, 31, 0, rk3399_pll_rates),
229 [dpll] = PLL(pll_rk3399, PLL_DPLL, "dpll", mux_pll_p, 0, RK3399_PLL_CON(16),
230 RK3399_PLL_CON(19), 8, 31, 0, NULL),
231 [cpll] = PLL(pll_rk3399, PLL_CPLL, "cpll", mux_pll_p, 0, RK3399_PLL_CON(24),
232 RK3399_PLL_CON(27), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
233 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RK3399_PLL_CON(32),
234 RK3399_PLL_CON(35), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
235 [npll] = PLL(pll_rk3399, PLL_NPLL, "npll", mux_pll_p, 0, RK3399_PLL_CON(40),
236 RK3399_PLL_CON(43), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
237 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
238 RK3399_PLL_CON(51), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
239 };
240
241 static struct rockchip_pll_clock rk3399_pmu_pll_clks[] __initdata = {
242 [ppll] = PLL(pll_rk3399, PLL_PPLL, "ppll", mux_pll_p, 0, RK3399_PMU_PLL_CON(0),
243 RK3399_PMU_PLL_CON(3), 8, 31, ROCKCHIP_PLL_SYNC_RATE, rk3399_pll_rates),
244 };
245
246 #define MFLAGS CLK_MUX_HIWORD_MASK
247 #define DFLAGS CLK_DIVIDER_HIWORD_MASK
248 #define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
249 #define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
250
251 static struct rockchip_clk_branch rk3399_spdif_fracmux __initdata =
252 MUX(0, "clk_spdif_mux", mux_spdif_p, CLK_SET_RATE_PARENT,
253 RK3399_CLKSEL_CON(32), 13, 2, MFLAGS);
254
255 static struct rockchip_clk_branch rk3399_i2s0_fracmux __initdata =
256 MUX(0, "clk_i2s0_mux", mux_i2s0_p, CLK_SET_RATE_PARENT,
257 RK3399_CLKSEL_CON(28), 8, 2, MFLAGS);
258
259 static struct rockchip_clk_branch rk3399_i2s1_fracmux __initdata =
260 MUX(0, "clk_i2s1_mux", mux_i2s1_p, CLK_SET_RATE_PARENT,
261 RK3399_CLKSEL_CON(29), 8, 2, MFLAGS);
262
263 static struct rockchip_clk_branch rk3399_i2s2_fracmux __initdata =
264 MUX(0, "clk_i2s2_mux", mux_i2s2_p, CLK_SET_RATE_PARENT,
265 RK3399_CLKSEL_CON(30), 8, 2, MFLAGS);
266
267 static struct rockchip_clk_branch rk3399_uart0_fracmux __initdata =
268 MUX(SCLK_UART0, "clk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
269 RK3399_CLKSEL_CON(33), 8, 2, MFLAGS);
270
271 static struct rockchip_clk_branch rk3399_uart1_fracmux __initdata =
272 MUX(SCLK_UART1, "clk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
273 RK3399_CLKSEL_CON(34), 8, 2, MFLAGS);
274
275 static struct rockchip_clk_branch rk3399_uart2_fracmux __initdata =
276 MUX(SCLK_UART2, "clk_uart2", mux_uart2_p, CLK_SET_RATE_PARENT,
277 RK3399_CLKSEL_CON(35), 8, 2, MFLAGS);
278
279 static struct rockchip_clk_branch rk3399_uart3_fracmux __initdata =
280 MUX(SCLK_UART3, "clk_uart3", mux_uart3_p, CLK_SET_RATE_PARENT,
281 RK3399_CLKSEL_CON(36), 8, 2, MFLAGS);
282
283 static struct rockchip_clk_branch rk3399_uart4_pmu_fracmux __initdata =
284 MUX(SCLK_UART4_PMU, "clk_uart4_pmu", mux_uart4_pmu_p, CLK_SET_RATE_PARENT,
285 RK3399_PMU_CLKSEL_CON(5), 8, 2, MFLAGS);
286
287 static struct rockchip_clk_branch rk3399_dclk_vop0_fracmux __initdata =
288 MUX(DCLK_VOP0, "dclk_vop0", mux_dclk_vop0_p, CLK_SET_RATE_PARENT,
289 RK3399_CLKSEL_CON(49), 11, 1, MFLAGS);
290
291 static struct rockchip_clk_branch rk3399_dclk_vop1_fracmux __initdata =
292 MUX(DCLK_VOP1, "dclk_vop1", mux_dclk_vop1_p, CLK_SET_RATE_PARENT,
293 RK3399_CLKSEL_CON(50), 11, 1, MFLAGS);
294
295 static struct rockchip_clk_branch rk3399_pmuclk_wifi_fracmux __initdata =
296 MUX(SCLK_WIFI_PMU, "clk_wifi_pmu", mux_wifi_pmu_p, CLK_SET_RATE_PARENT,
297 RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
298
299 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
300 .core_reg = RK3399_CLKSEL_CON(0),
301 .div_core_shift = 0,
302 .div_core_mask = 0x1f,
303 .mux_core_alt = 3,
304 .mux_core_main = 0,
305 .mux_core_shift = 6,
306 .mux_core_mask = 0x3,
307 };
308
309 static const struct rockchip_cpuclk_reg_data rk3399_cpuclkb_data = {
310 .core_reg = RK3399_CLKSEL_CON(2),
311 .div_core_shift = 0,
312 .div_core_mask = 0x1f,
313 .mux_core_alt = 3,
314 .mux_core_main = 1,
315 .mux_core_shift = 6,
316 .mux_core_mask = 0x3,
317 };
318
319 #define RK3399_DIV_ACLKM_MASK 0x1f
320 #define RK3399_DIV_ACLKM_SHIFT 8
321 #define RK3399_DIV_ATCLK_MASK 0x1f
322 #define RK3399_DIV_ATCLK_SHIFT 0
323 #define RK3399_DIV_PCLK_DBG_MASK 0x1f
324 #define RK3399_DIV_PCLK_DBG_SHIFT 8
325
326 #define RK3399_CLKSEL0(_offs, _aclkm) \
327 { \
328 .reg = RK3399_CLKSEL_CON(0 + _offs), \
329 .val = HIWORD_UPDATE(_aclkm, RK3399_DIV_ACLKM_MASK, \
330 RK3399_DIV_ACLKM_SHIFT), \
331 }
332 #define RK3399_CLKSEL1(_offs, _atclk, _pdbg) \
333 { \
334 .reg = RK3399_CLKSEL_CON(1 + _offs), \
335 .val = HIWORD_UPDATE(_atclk, RK3399_DIV_ATCLK_MASK, \
336 RK3399_DIV_ATCLK_SHIFT) | \
337 HIWORD_UPDATE(_pdbg, RK3399_DIV_PCLK_DBG_MASK, \
338 RK3399_DIV_PCLK_DBG_SHIFT), \
339 }
340
341 /* cluster_l: aclkm in clksel0, rest in clksel1 */
342 #define RK3399_CPUCLKL_RATE(_prate, _aclkm, _atclk, _pdbg) \
343 { \
344 .prate = _prate##U, \
345 .divs = { \
346 RK3399_CLKSEL0(0, _aclkm), \
347 RK3399_CLKSEL1(0, _atclk, _pdbg), \
348 }, \
349 }
350
351 /* cluster_b: aclkm in clksel2, rest in clksel3 */
352 #define RK3399_CPUCLKB_RATE(_prate, _aclkm, _atclk, _pdbg) \
353 { \
354 .prate = _prate##U, \
355 .divs = { \
356 RK3399_CLKSEL0(2, _aclkm), \
357 RK3399_CLKSEL1(2, _atclk, _pdbg), \
358 }, \
359 }
360
361 static struct rockchip_cpuclk_rate_table rk3399_cpuclkl_rates[] __initdata = {
362 RK3399_CPUCLKL_RATE(1800000000, 1, 8, 8),
363 RK3399_CPUCLKL_RATE(1704000000, 1, 8, 8),
364 RK3399_CPUCLKL_RATE(1608000000, 1, 7, 7),
365 RK3399_CPUCLKL_RATE(1512000000, 1, 7, 7),
366 RK3399_CPUCLKL_RATE(1488000000, 1, 6, 6),
367 RK3399_CPUCLKL_RATE(1416000000, 1, 6, 6),
368 RK3399_CPUCLKL_RATE(1200000000, 1, 5, 5),
369 RK3399_CPUCLKL_RATE(1008000000, 1, 5, 5),
370 RK3399_CPUCLKL_RATE( 816000000, 1, 4, 4),
371 RK3399_CPUCLKL_RATE( 696000000, 1, 3, 3),
372 RK3399_CPUCLKL_RATE( 600000000, 1, 3, 3),
373 RK3399_CPUCLKL_RATE( 408000000, 1, 2, 2),
374 RK3399_CPUCLKL_RATE( 312000000, 1, 1, 1),
375 RK3399_CPUCLKL_RATE( 216000000, 1, 1, 1),
376 RK3399_CPUCLKL_RATE( 96000000, 1, 1, 1),
377 };
378
379 static struct rockchip_cpuclk_rate_table rk3399_cpuclkb_rates[] __initdata = {
380 RK3399_CPUCLKB_RATE(2208000000, 1, 11, 11),
381 RK3399_CPUCLKB_RATE(2184000000, 1, 11, 11),
382 RK3399_CPUCLKB_RATE(2088000000, 1, 10, 10),
383 RK3399_CPUCLKB_RATE(2040000000, 1, 10, 10),
384 RK3399_CPUCLKB_RATE(2016000000, 1, 9, 9),
385 RK3399_CPUCLKB_RATE(1992000000, 1, 9, 9),
386 RK3399_CPUCLKB_RATE(1896000000, 1, 9, 9),
387 RK3399_CPUCLKB_RATE(1800000000, 1, 8, 8),
388 RK3399_CPUCLKB_RATE(1704000000, 1, 8, 8),
389 RK3399_CPUCLKB_RATE(1608000000, 1, 7, 7),
390 RK3399_CPUCLKB_RATE(1512000000, 1, 7, 7),
391 RK3399_CPUCLKB_RATE(1488000000, 1, 6, 6),
392 RK3399_CPUCLKB_RATE(1416000000, 1, 6, 6),
393 RK3399_CPUCLKB_RATE(1200000000, 1, 5, 5),
394 RK3399_CPUCLKB_RATE(1008000000, 1, 5, 5),
395 RK3399_CPUCLKB_RATE( 816000000, 1, 4, 4),
396 RK3399_CPUCLKB_RATE( 696000000, 1, 3, 3),
397 RK3399_CPUCLKB_RATE( 600000000, 1, 3, 3),
398 RK3399_CPUCLKB_RATE( 408000000, 1, 2, 2),
399 RK3399_CPUCLKB_RATE( 312000000, 1, 1, 1),
400 RK3399_CPUCLKB_RATE( 216000000, 1, 1, 1),
401 RK3399_CPUCLKB_RATE( 96000000, 1, 1, 1),
402 };
403
404 static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
405 /*
406 * CRU Clock-Architecture
407 */
408
409 /* usbphy */
410 GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", CLK_IGNORE_UNUSED,
411 RK3399_CLKGATE_CON(6), 5, GFLAGS),
412 GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", CLK_IGNORE_UNUSED,
413 RK3399_CLKGATE_CON(6), 6, GFLAGS),
414
415 GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 0,
416 RK3399_CLKGATE_CON(13), 12, GFLAGS),
417 GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 0,
418 RK3399_CLKGATE_CON(13), 12, GFLAGS),
419 MUX(0, "clk_usbphy_480m", mux_usbphy_480m_p, 0,
420 RK3399_CLKSEL_CON(14), 6, 1, MFLAGS),
421
422 MUX(0, "upll", mux_pll_src_24m_usbphy480m_p, 0,
423 RK3399_CLKSEL_CON(14), 15, 1, MFLAGS),
424
425 COMPOSITE_NODIV(SCLK_HSICPHY, "clk_hsicphy", mux_pll_src_cpll_gpll_npll_usbphy480m_p, 0,
426 RK3399_CLKSEL_CON(19), 0, 2, MFLAGS,
427 RK3399_CLKGATE_CON(6), 4, GFLAGS),
428
429 COMPOSITE(ACLK_USB3, "aclk_usb3", mux_pll_src_cpll_gpll_npll_p, 0,
430 RK3399_CLKSEL_CON(39), 6, 2, MFLAGS, 0, 5, DFLAGS,
431 RK3399_CLKGATE_CON(12), 0, GFLAGS),
432 GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", CLK_IGNORE_UNUSED,
433 RK3399_CLKGATE_CON(30), 0, GFLAGS),
434 GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0,
435 RK3399_CLKGATE_CON(30), 1, GFLAGS),
436 GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0,
437 RK3399_CLKGATE_CON(30), 2, GFLAGS),
438 GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0,
439 RK3399_CLKGATE_CON(30), 3, GFLAGS),
440 GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0,
441 RK3399_CLKGATE_CON(30), 4, GFLAGS),
442
443 GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 0,
444 RK3399_CLKGATE_CON(12), 1, GFLAGS),
445 GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 0,
446 RK3399_CLKGATE_CON(12), 2, GFLAGS),
447
448 COMPOSITE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", mux_pll_p, 0,
449 RK3399_CLKSEL_CON(40), 15, 1, MFLAGS, 0, 10, DFLAGS,
450 RK3399_CLKGATE_CON(12), 3, GFLAGS),
451
452 COMPOSITE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", mux_pll_p, 0,
453 RK3399_CLKSEL_CON(41), 15, 1, MFLAGS, 0, 10, DFLAGS,
454 RK3399_CLKGATE_CON(12), 4, GFLAGS),
455
456 COMPOSITE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", mux_pll_p, 0,
457 RK3399_CLKSEL_CON(64), 15, 1, MFLAGS, 8, 5, DFLAGS,
458 RK3399_CLKGATE_CON(13), 4, GFLAGS),
459
460 COMPOSITE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
461 RK3399_CLKSEL_CON(64), 6, 2, MFLAGS, 0, 5, DFLAGS,
462 RK3399_CLKGATE_CON(13), 5, GFLAGS),
463
464 COMPOSITE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", mux_pll_p, 0,
465 RK3399_CLKSEL_CON(65), 15, 1, MFLAGS, 8, 5, DFLAGS,
466 RK3399_CLKGATE_CON(13), 6, GFLAGS),
467
468 COMPOSITE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", mux_pll_src_24m_32k_cpll_gpll_p, 0,
469 RK3399_CLKSEL_CON(65), 6, 2, MFLAGS, 0, 5, DFLAGS,
470 RK3399_CLKGATE_CON(13), 7, GFLAGS),
471
472 /* little core */
473 GATE(0, "clk_core_l_lpll_src", "lpll", CLK_IGNORE_UNUSED,
474 RK3399_CLKGATE_CON(0), 0, GFLAGS),
475 GATE(0, "clk_core_l_bpll_src", "bpll", CLK_IGNORE_UNUSED,
476 RK3399_CLKGATE_CON(0), 1, GFLAGS),
477 GATE(0, "clk_core_l_dpll_src", "dpll", CLK_IGNORE_UNUSED,
478 RK3399_CLKGATE_CON(0), 2, GFLAGS),
479 GATE(0, "clk_core_l_gpll_src", "gpll", CLK_IGNORE_UNUSED,
480 RK3399_CLKGATE_CON(0), 3, GFLAGS),
481
482 COMPOSITE_NOMUX(0, "aclkm_core_l", "armclkl", CLK_IGNORE_UNUSED,
483 RK3399_CLKSEL_CON(0), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
484 RK3399_CLKGATE_CON(0), 4, GFLAGS),
485 COMPOSITE_NOMUX(0, "atclk_core_l", "armclkl", CLK_IGNORE_UNUSED,
486 RK3399_CLKSEL_CON(1), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
487 RK3399_CLKGATE_CON(0), 5, GFLAGS),
488 COMPOSITE_NOMUX(0, "pclk_dbg_core_l", "armclkl", CLK_IGNORE_UNUSED,
489 RK3399_CLKSEL_CON(1), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
490 RK3399_CLKGATE_CON(0), 6, GFLAGS),
491
492 GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", CLK_IGNORE_UNUSED,
493 RK3399_CLKGATE_CON(14), 12, GFLAGS),
494 GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", CLK_IGNORE_UNUSED,
495 RK3399_CLKGATE_CON(14), 13, GFLAGS),
496
497 GATE(0, "clk_dbg_pd_core_l", "armclkl", CLK_IGNORE_UNUSED,
498 RK3399_CLKGATE_CON(14), 9, GFLAGS),
499 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", CLK_IGNORE_UNUSED,
500 RK3399_CLKGATE_CON(14), 10, GFLAGS),
501 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", CLK_IGNORE_UNUSED,
502 RK3399_CLKGATE_CON(14), 11, GFLAGS),
503 GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0,
504 RK3399_CLKGATE_CON(0), 7, GFLAGS),
505
506 /* big core */
507 GATE(0, "clk_core_b_lpll_src", "lpll", CLK_IGNORE_UNUSED,
508 RK3399_CLKGATE_CON(1), 0, GFLAGS),
509 GATE(0, "clk_core_b_bpll_src", "bpll", CLK_IGNORE_UNUSED,
510 RK3399_CLKGATE_CON(1), 1, GFLAGS),
511 GATE(0, "clk_core_b_dpll_src", "dpll", CLK_IGNORE_UNUSED,
512 RK3399_CLKGATE_CON(1), 2, GFLAGS),
513 GATE(0, "clk_core_b_gpll_src", "gpll", CLK_IGNORE_UNUSED,
514 RK3399_CLKGATE_CON(1), 3, GFLAGS),
515
516 COMPOSITE_NOMUX(0, "aclkm_core_b", "armclkb", CLK_IGNORE_UNUSED,
517 RK3399_CLKSEL_CON(2), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
518 RK3399_CLKGATE_CON(1), 4, GFLAGS),
519 COMPOSITE_NOMUX(0, "atclk_core_b", "armclkb", CLK_IGNORE_UNUSED,
520 RK3399_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
521 RK3399_CLKGATE_CON(1), 5, GFLAGS),
522 COMPOSITE_NOMUX(0, "pclk_dbg_core_b", "armclkb", CLK_IGNORE_UNUSED,
523 RK3399_CLKSEL_CON(3), 8, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
524 RK3399_CLKGATE_CON(1), 6, GFLAGS),
525
526 GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", CLK_IGNORE_UNUSED,
527 RK3399_CLKGATE_CON(14), 5, GFLAGS),
528 GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", CLK_IGNORE_UNUSED,
529 RK3399_CLKGATE_CON(14), 6, GFLAGS),
530
531 GATE(0, "clk_dbg_pd_core_b", "armclkb", CLK_IGNORE_UNUSED,
532 RK3399_CLKGATE_CON(14), 1, GFLAGS),
533 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", CLK_IGNORE_UNUSED,
534 RK3399_CLKGATE_CON(14), 3, GFLAGS),
535 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", CLK_IGNORE_UNUSED,
536 RK3399_CLKGATE_CON(14), 4, GFLAGS),
537
538 DIV(0, "pclken_dbg_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
539 RK3399_CLKSEL_CON(3), 13, 2, DFLAGS | CLK_DIVIDER_READ_ONLY),
540
541 GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", CLK_IGNORE_UNUSED,
542 RK3399_CLKGATE_CON(14), 2, GFLAGS),
543
544 GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 0,
545 RK3399_CLKGATE_CON(1), 7, GFLAGS),
546
547 /* gmac */
548 GATE(0, "cpll_aclk_gmac_src", "cpll", CLK_IGNORE_UNUSED,
549 RK3399_CLKGATE_CON(6), 9, GFLAGS),
550 GATE(0, "gpll_aclk_gmac_src", "gpll", CLK_IGNORE_UNUSED,
551 RK3399_CLKGATE_CON(6), 8, GFLAGS),
552 COMPOSITE(0, "aclk_gmac_pre", mux_aclk_gmac_p, 0,
553 RK3399_CLKSEL_CON(20), 7, 1, MFLAGS, 0, 5, DFLAGS,
554 RK3399_CLKGATE_CON(6), 10, GFLAGS),
555
556 GATE(ACLK_GMAC, "aclk_gmac", "aclk_gmac_pre", 0,
557 RK3399_CLKGATE_CON(32), 0, GFLAGS),
558 GATE(ACLK_GMAC_NOC, "aclk_gmac_noc", "aclk_gmac_pre", CLK_IGNORE_UNUSED,
559 RK3399_CLKGATE_CON(32), 1, GFLAGS),
560 GATE(ACLK_PERF_GMAC, "aclk_perf_gmac", "aclk_gmac_pre", 0,
561 RK3399_CLKGATE_CON(32), 4, GFLAGS),
562
563 COMPOSITE_NOMUX(0, "pclk_gmac_pre", "aclk_gmac_pre", 0,
564 RK3399_CLKSEL_CON(19), 8, 3, DFLAGS,
565 RK3399_CLKGATE_CON(6), 11, GFLAGS),
566 GATE(PCLK_GMAC, "pclk_gmac", "pclk_gmac_pre", 0,
567 RK3399_CLKGATE_CON(32), 2, GFLAGS),
568 GATE(PCLK_GMAC_NOC, "pclk_gmac_noc", "pclk_gmac_pre", CLK_IGNORE_UNUSED,
569 RK3399_CLKGATE_CON(32), 3, GFLAGS),
570
571 COMPOSITE(SCLK_MAC, "clk_gmac", mux_pll_src_cpll_gpll_npll_p, 0,
572 RK3399_CLKSEL_CON(20), 14, 2, MFLAGS, 8, 5, DFLAGS,
573 RK3399_CLKGATE_CON(5), 5, GFLAGS),
574
575 MUX(SCLK_RMII_SRC, "clk_rmii_src", mux_rmii_p, CLK_SET_RATE_PARENT,
576 RK3399_CLKSEL_CON(19), 4, 1, MFLAGS),
577 GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 0,
578 RK3399_CLKGATE_CON(5), 6, GFLAGS),
579 GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 0,
580 RK3399_CLKGATE_CON(5), 7, GFLAGS),
581 GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 0,
582 RK3399_CLKGATE_CON(5), 8, GFLAGS),
583 GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 0,
584 RK3399_CLKGATE_CON(5), 9, GFLAGS),
585
586 /* spdif */
587 COMPOSITE(0, "clk_spdif_div", mux_pll_src_cpll_gpll_p, 0,
588 RK3399_CLKSEL_CON(32), 7, 1, MFLAGS, 0, 7, DFLAGS,
589 RK3399_CLKGATE_CON(8), 13, GFLAGS),
590 COMPOSITE_FRACMUX(0, "clk_spdif_frac", "clk_spdif_div", 0,
591 RK3399_CLKSEL_CON(99), 0,
592 RK3399_CLKGATE_CON(8), 14, GFLAGS,
593 &rk3399_spdif_fracmux),
594 GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", CLK_SET_RATE_PARENT,
595 RK3399_CLKGATE_CON(8), 15, GFLAGS),
596
597 COMPOSITE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", mux_pll_src_cpll_gpll_p, 0,
598 RK3399_CLKSEL_CON(32), 15, 1, MFLAGS, 8, 5, DFLAGS,
599 RK3399_CLKGATE_CON(10), 6, GFLAGS),
600 /* i2s */
601 COMPOSITE(0, "clk_i2s0_div", mux_pll_src_cpll_gpll_p, 0,
602 RK3399_CLKSEL_CON(28), 7, 1, MFLAGS, 0, 7, DFLAGS,
603 RK3399_CLKGATE_CON(8), 3, GFLAGS),
604 COMPOSITE_FRACMUX(0, "clk_i2s0_frac", "clk_i2s0_div", 0,
605 RK3399_CLKSEL_CON(96), 0,
606 RK3399_CLKGATE_CON(8), 4, GFLAGS,
607 &rk3399_i2s0_fracmux),
608 GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", CLK_SET_RATE_PARENT,
609 RK3399_CLKGATE_CON(8), 5, GFLAGS),
610
611 COMPOSITE(0, "clk_i2s1_div", mux_pll_src_cpll_gpll_p, 0,
612 RK3399_CLKSEL_CON(29), 7, 1, MFLAGS, 0, 7, DFLAGS,
613 RK3399_CLKGATE_CON(8), 6, GFLAGS),
614 COMPOSITE_FRACMUX(0, "clk_i2s1_frac", "clk_i2s1_div", 0,
615 RK3399_CLKSEL_CON(97), 0,
616 RK3399_CLKGATE_CON(8), 7, GFLAGS,
617 &rk3399_i2s1_fracmux),
618 GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", CLK_SET_RATE_PARENT,
619 RK3399_CLKGATE_CON(8), 8, GFLAGS),
620
621 COMPOSITE(0, "clk_i2s2_div", mux_pll_src_cpll_gpll_p, 0,
622 RK3399_CLKSEL_CON(30), 7, 1, MFLAGS, 0, 7, DFLAGS,
623 RK3399_CLKGATE_CON(8), 9, GFLAGS),
624 COMPOSITE_FRACMUX(0, "clk_i2s2_frac", "clk_i2s2_div", 0,
625 RK3399_CLKSEL_CON(98), 0,
626 RK3399_CLKGATE_CON(8), 10, GFLAGS,
627 &rk3399_i2s2_fracmux),
628 GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", CLK_SET_RATE_PARENT,
629 RK3399_CLKGATE_CON(8), 11, GFLAGS),
630
631 MUX(0, "clk_i2sout_src", mux_i2sch_p, CLK_SET_RATE_PARENT,
632 RK3399_CLKSEL_CON(31), 0, 2, MFLAGS),
633 COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "clk_i2sout", mux_i2sout_p, CLK_SET_RATE_PARENT,
634 RK3399_CLKSEL_CON(31), 2, 1, MFLAGS,
635 RK3399_CLKGATE_CON(8), 12, GFLAGS),
636
637 /* uart */
638 MUX(0, "clk_uart0_src", mux_pll_src_cpll_gpll_upll_p, 0,
639 RK3399_CLKSEL_CON(33), 12, 2, MFLAGS),
640 COMPOSITE_NOMUX(0, "clk_uart0_div", "clk_uart0_src", 0,
641 RK3399_CLKSEL_CON(33), 0, 7, DFLAGS,
642 RK3399_CLKGATE_CON(9), 0, GFLAGS),
643 COMPOSITE_FRACMUX(0, "clk_uart0_frac", "clk_uart0_div", 0,
644 RK3399_CLKSEL_CON(100), 0,
645 RK3399_CLKGATE_CON(9), 1, GFLAGS,
646 &rk3399_uart0_fracmux),
647
648 MUX(0, "clk_uart_src", mux_pll_src_cpll_gpll_p, 0,
649 RK3399_CLKSEL_CON(33), 15, 1, MFLAGS),
650 COMPOSITE_NOMUX(0, "clk_uart1_div", "clk_uart_src", 0,
651 RK3399_CLKSEL_CON(34), 0, 7, DFLAGS,
652 RK3399_CLKGATE_CON(9), 2, GFLAGS),
653 COMPOSITE_FRACMUX(0, "clk_uart1_frac", "clk_uart1_div", 0,
654 RK3399_CLKSEL_CON(101), 0,
655 RK3399_CLKGATE_CON(9), 3, GFLAGS,
656 &rk3399_uart1_fracmux),
657
658 COMPOSITE_NOMUX(0, "clk_uart2_div", "clk_uart_src", 0,
659 RK3399_CLKSEL_CON(35), 0, 7, DFLAGS,
660 RK3399_CLKGATE_CON(9), 4, GFLAGS),
661 COMPOSITE_FRACMUX(0, "clk_uart2_frac", "clk_uart2_div", 0,
662 RK3399_CLKSEL_CON(102), 0,
663 RK3399_CLKGATE_CON(9), 5, GFLAGS,
664 &rk3399_uart2_fracmux),
665
666 COMPOSITE_NOMUX(0, "clk_uart3_div", "clk_uart_src", 0,
667 RK3399_CLKSEL_CON(36), 0, 7, DFLAGS,
668 RK3399_CLKGATE_CON(9), 6, GFLAGS),
669 COMPOSITE_FRACMUX(0, "clk_uart3_frac", "clk_uart3_div", 0,
670 RK3399_CLKSEL_CON(103), 0,
671 RK3399_CLKGATE_CON(9), 7, GFLAGS,
672 &rk3399_uart3_fracmux),
673
674 COMPOSITE(PCLK_DDR, "pclk_ddr", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
675 RK3399_CLKSEL_CON(6), 15, 1, MFLAGS, 8, 5, DFLAGS,
676 RK3399_CLKGATE_CON(3), 4, GFLAGS),
677
678 GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", CLK_IGNORE_UNUSED,
679 RK3399_CLKGATE_CON(18), 10, GFLAGS),
680 GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 0,
681 RK3399_CLKGATE_CON(18), 12, GFLAGS),
682 GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", CLK_IGNORE_UNUSED,
683 RK3399_CLKGATE_CON(18), 15, GFLAGS),
684 GATE(PCLK_DDR_SGRF, "pclk_ddr_sgrf", "pclk_ddr", CLK_IGNORE_UNUSED,
685 RK3399_CLKGATE_CON(19), 2, GFLAGS),
686
687 GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 0,
688 RK3399_CLKGATE_CON(4), 11, GFLAGS),
689 GATE(SCLK_DFIMON0_TIMER, "clk_dfimon0_timer", "xin24m", 0,
690 RK3399_CLKGATE_CON(3), 5, GFLAGS),
691 GATE(SCLK_DFIMON1_TIMER, "clk_dfimon1_timer", "xin24m", 0,
692 RK3399_CLKGATE_CON(3), 6, GFLAGS),
693
694 /* cci */
695 GATE(0, "cpll_aclk_cci_src", "cpll", CLK_IGNORE_UNUSED,
696 RK3399_CLKGATE_CON(2), 0, GFLAGS),
697 GATE(0, "gpll_aclk_cci_src", "gpll", CLK_IGNORE_UNUSED,
698 RK3399_CLKGATE_CON(2), 1, GFLAGS),
699 GATE(0, "npll_aclk_cci_src", "npll", CLK_IGNORE_UNUSED,
700 RK3399_CLKGATE_CON(2), 2, GFLAGS),
701 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
702 RK3399_CLKGATE_CON(2), 3, GFLAGS),
703
704 COMPOSITE(0, "aclk_cci_pre", mux_aclk_cci_p, CLK_IGNORE_UNUSED,
705 RK3399_CLKSEL_CON(5), 6, 2, MFLAGS, 0, 5, DFLAGS,
706 RK3399_CLKGATE_CON(2), 4, GFLAGS),
707
708 GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", CLK_IGNORE_UNUSED,
709 RK3399_CLKGATE_CON(15), 0, GFLAGS),
710 GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", CLK_IGNORE_UNUSED,
711 RK3399_CLKGATE_CON(15), 1, GFLAGS),
712 GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", CLK_IGNORE_UNUSED,
713 RK3399_CLKGATE_CON(15), 2, GFLAGS),
714 GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", CLK_IGNORE_UNUSED,
715 RK3399_CLKGATE_CON(15), 3, GFLAGS),
716 GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", CLK_IGNORE_UNUSED,
717 RK3399_CLKGATE_CON(15), 4, GFLAGS),
718 GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", CLK_IGNORE_UNUSED,
719 RK3399_CLKGATE_CON(15), 7, GFLAGS),
720
721 GATE(0, "cpll_cci_trace", "cpll", CLK_IGNORE_UNUSED,
722 RK3399_CLKGATE_CON(2), 5, GFLAGS),
723 GATE(0, "gpll_cci_trace", "gpll", CLK_IGNORE_UNUSED,
724 RK3399_CLKGATE_CON(2), 6, GFLAGS),
725 COMPOSITE(SCLK_CCI_TRACE, "clk_cci_trace", mux_cci_trace_p, CLK_IGNORE_UNUSED,
726 RK3399_CLKSEL_CON(5), 15, 2, MFLAGS, 8, 5, DFLAGS,
727 RK3399_CLKGATE_CON(2), 7, GFLAGS),
728
729 GATE(0, "cpll_cs", "cpll", CLK_IGNORE_UNUSED,
730 RK3399_CLKGATE_CON(2), 8, GFLAGS),
731 GATE(0, "gpll_cs", "gpll", CLK_IGNORE_UNUSED,
732 RK3399_CLKGATE_CON(2), 9, GFLAGS),
733 GATE(0, "npll_cs", "npll", CLK_IGNORE_UNUSED,
734 RK3399_CLKGATE_CON(2), 10, GFLAGS),
735 COMPOSITE_NOGATE(0, "clk_cs", mux_cs_p, CLK_IGNORE_UNUSED,
736 RK3399_CLKSEL_CON(4), 6, 2, MFLAGS, 0, 5, DFLAGS),
737 GATE(0, "clk_dbg_cxcs", "clk_cs", CLK_IGNORE_UNUSED,
738 RK3399_CLKGATE_CON(15), 5, GFLAGS),
739 GATE(0, "clk_dbg_noc", "clk_cs", CLK_IGNORE_UNUSED,
740 RK3399_CLKGATE_CON(15), 6, GFLAGS),
741
742 /* vcodec */
743 COMPOSITE(0, "aclk_vcodec_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
744 RK3399_CLKSEL_CON(7), 6, 2, MFLAGS, 0, 5, DFLAGS,
745 RK3399_CLKGATE_CON(4), 0, GFLAGS),
746 COMPOSITE_NOMUX(0, "hclk_vcodec_pre", "aclk_vcodec_pre", 0,
747 RK3399_CLKSEL_CON(7), 8, 5, DFLAGS,
748 RK3399_CLKGATE_CON(4), 1, GFLAGS),
749 GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 0,
750 RK3399_CLKGATE_CON(17), 2, GFLAGS),
751 GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", CLK_IGNORE_UNUSED,
752 RK3399_CLKGATE_CON(17), 3, GFLAGS),
753
754 GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 0,
755 RK3399_CLKGATE_CON(17), 0, GFLAGS),
756 GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", CLK_IGNORE_UNUSED,
757 RK3399_CLKGATE_CON(17), 1, GFLAGS),
758
759 /* vdu */
760 COMPOSITE(SCLK_VDU_CORE, "clk_vdu_core", mux_pll_src_cpll_gpll_npll_p, 0,
761 RK3399_CLKSEL_CON(9), 6, 2, MFLAGS, 0, 5, DFLAGS,
762 RK3399_CLKGATE_CON(4), 4, GFLAGS),
763 COMPOSITE(SCLK_VDU_CA, "clk_vdu_ca", mux_pll_src_cpll_gpll_npll_p, 0,
764 RK3399_CLKSEL_CON(9), 14, 2, MFLAGS, 8, 5, DFLAGS,
765 RK3399_CLKGATE_CON(4), 5, GFLAGS),
766
767 COMPOSITE(0, "aclk_vdu_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
768 RK3399_CLKSEL_CON(8), 6, 2, MFLAGS, 0, 5, DFLAGS,
769 RK3399_CLKGATE_CON(4), 2, GFLAGS),
770 COMPOSITE_NOMUX(0, "hclk_vdu_pre", "aclk_vdu_pre", 0,
771 RK3399_CLKSEL_CON(8), 8, 5, DFLAGS,
772 RK3399_CLKGATE_CON(4), 3, GFLAGS),
773 GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 0,
774 RK3399_CLKGATE_CON(17), 10, GFLAGS),
775 GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", CLK_IGNORE_UNUSED,
776 RK3399_CLKGATE_CON(17), 11, GFLAGS),
777
778 GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 0,
779 RK3399_CLKGATE_CON(17), 8, GFLAGS),
780 GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", CLK_IGNORE_UNUSED,
781 RK3399_CLKGATE_CON(17), 9, GFLAGS),
782
783 /* iep */
784 COMPOSITE(0, "aclk_iep_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
785 RK3399_CLKSEL_CON(10), 6, 2, MFLAGS, 0, 5, DFLAGS,
786 RK3399_CLKGATE_CON(4), 6, GFLAGS),
787 COMPOSITE_NOMUX(0, "hclk_iep_pre", "aclk_iep_pre", 0,
788 RK3399_CLKSEL_CON(10), 8, 5, DFLAGS,
789 RK3399_CLKGATE_CON(4), 7, GFLAGS),
790 GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 0,
791 RK3399_CLKGATE_CON(16), 2, GFLAGS),
792 GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", CLK_IGNORE_UNUSED,
793 RK3399_CLKGATE_CON(16), 3, GFLAGS),
794
795 GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0,
796 RK3399_CLKGATE_CON(16), 0, GFLAGS),
797 GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", CLK_IGNORE_UNUSED,
798 RK3399_CLKGATE_CON(16), 1, GFLAGS),
799
800 /* rga */
801 COMPOSITE(SCLK_RGA_CORE, "clk_rga_core", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
802 RK3399_CLKSEL_CON(12), 6, 2, MFLAGS, 0, 5, DFLAGS,
803 RK3399_CLKGATE_CON(4), 10, GFLAGS),
804
805 COMPOSITE(0, "aclk_rga_pre", mux_pll_src_cpll_gpll_npll_ppll_p, 0,
806 RK3399_CLKSEL_CON(11), 6, 2, MFLAGS, 0, 5, DFLAGS,
807 RK3399_CLKGATE_CON(4), 8, GFLAGS),
808 COMPOSITE_NOMUX(0, "hclk_rga_pre", "aclk_rga_pre", 0,
809 RK3399_CLKSEL_CON(11), 8, 5, DFLAGS,
810 RK3399_CLKGATE_CON(4), 9, GFLAGS),
811 GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 0,
812 RK3399_CLKGATE_CON(16), 10, GFLAGS),
813 GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", CLK_IGNORE_UNUSED,
814 RK3399_CLKGATE_CON(16), 11, GFLAGS),
815
816 GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0,
817 RK3399_CLKGATE_CON(16), 8, GFLAGS),
818 GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", CLK_IGNORE_UNUSED,
819 RK3399_CLKGATE_CON(16), 9, GFLAGS),
820
821 /* center */
822 COMPOSITE(0, "aclk_center", mux_pll_src_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
823 RK3399_CLKSEL_CON(12), 14, 2, MFLAGS, 8, 5, DFLAGS,
824 RK3399_CLKGATE_CON(3), 7, GFLAGS),
825 GATE(ACLK_CENTER_MAIN_NOC, "aclk_center_main_noc", "aclk_center", CLK_IGNORE_UNUSED,
826 RK3399_CLKGATE_CON(19), 0, GFLAGS),
827 GATE(ACLK_CENTER_PERI_NOC, "aclk_center_peri_noc", "aclk_center", CLK_IGNORE_UNUSED,
828 RK3399_CLKGATE_CON(19), 1, GFLAGS),
829
830 /* gpu */
831 COMPOSITE(0, "aclk_gpu_pre", mux_pll_src_ppll_cpll_gpll_npll_p, CLK_IGNORE_UNUSED,
832 RK3399_CLKSEL_CON(13), 5, 3, MFLAGS, 0, 5, DFLAGS,
833 RK3399_CLKGATE_CON(13), 0, GFLAGS),
834 GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0,
835 RK3399_CLKGATE_CON(30), 8, GFLAGS),
836 GATE(ACLK_PERF_GPU, "aclk_perf_gpu", "aclk_gpu_pre", 0,
837 RK3399_CLKGATE_CON(30), 10, GFLAGS),
838 GATE(ACLK_GPU_GRF, "aclk_gpu_grf", "aclk_gpu_pre", 0,
839 RK3399_CLKGATE_CON(30), 11, GFLAGS),
840 GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 0,
841 RK3399_CLKGATE_CON(13), 1, GFLAGS),
842
843 /* perihp */
844 GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
845 RK3399_CLKGATE_CON(5), 1, GFLAGS),
846 GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
847 RK3399_CLKGATE_CON(5), 0, GFLAGS),
848 COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
849 RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,
850 RK3399_CLKGATE_CON(5), 2, GFLAGS),
851 COMPOSITE_NOMUX(HCLK_PERIHP, "hclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
852 RK3399_CLKSEL_CON(14), 8, 2, DFLAGS,
853 RK3399_CLKGATE_CON(5), 3, GFLAGS),
854 COMPOSITE_NOMUX(PCLK_PERIHP, "pclk_perihp", "aclk_perihp", CLK_IGNORE_UNUSED,
855 RK3399_CLKSEL_CON(14), 12, 2, DFLAGS,
856 RK3399_CLKGATE_CON(5), 4, GFLAGS),
857
858 GATE(ACLK_PERF_PCIE, "aclk_perf_pcie", "aclk_perihp", 0,
859 RK3399_CLKGATE_CON(20), 2, GFLAGS),
860 GATE(ACLK_PCIE, "aclk_pcie", "aclk_perihp", 0,
861 RK3399_CLKGATE_CON(20), 10, GFLAGS),
862 GATE(0, "aclk_perihp_noc", "aclk_perihp", CLK_IGNORE_UNUSED,
863 RK3399_CLKGATE_CON(20), 12, GFLAGS),
864
865 GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0,
866 RK3399_CLKGATE_CON(20), 5, GFLAGS),
867 GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0,
868 RK3399_CLKGATE_CON(20), 6, GFLAGS),
869 GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0,
870 RK3399_CLKGATE_CON(20), 7, GFLAGS),
871 GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0,
872 RK3399_CLKGATE_CON(20), 8, GFLAGS),
873 GATE(HCLK_HSIC, "hclk_hsic", "hclk_perihp", 0,
874 RK3399_CLKGATE_CON(20), 9, GFLAGS),
875 GATE(0, "hclk_perihp_noc", "hclk_perihp", CLK_IGNORE_UNUSED,
876 RK3399_CLKGATE_CON(20), 13, GFLAGS),
877 GATE(0, "hclk_ahb1tom", "hclk_perihp", CLK_IGNORE_UNUSED,
878 RK3399_CLKGATE_CON(20), 15, GFLAGS),
879
880 GATE(PCLK_PERIHP_GRF, "pclk_perihp_grf", "pclk_perihp", CLK_IGNORE_UNUSED,
881 RK3399_CLKGATE_CON(20), 4, GFLAGS),
882 GATE(PCLK_PCIE, "pclk_pcie", "pclk_perihp", 0,
883 RK3399_CLKGATE_CON(20), 11, GFLAGS),
884 GATE(0, "pclk_perihp_noc", "pclk_perihp", CLK_IGNORE_UNUSED,
885 RK3399_CLKGATE_CON(20), 14, GFLAGS),
886 GATE(PCLK_HSICPHY, "pclk_hsicphy", "pclk_perihp", 0,
887 RK3399_CLKGATE_CON(31), 8, GFLAGS),
888
889 /* sdio & sdmmc */
890 COMPOSITE(HCLK_SD, "hclk_sd", mux_pll_src_cpll_gpll_p, 0,
891 RK3399_CLKSEL_CON(13), 15, 1, MFLAGS, 8, 5, DFLAGS,
892 RK3399_CLKGATE_CON(12), 13, GFLAGS),
893 GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0,
894 RK3399_CLKGATE_CON(33), 8, GFLAGS),
895 GATE(0, "hclk_sdmmc_noc", "hclk_sd", CLK_IGNORE_UNUSED,
896 RK3399_CLKGATE_CON(33), 9, GFLAGS),
897
898 COMPOSITE(SCLK_SDIO, "clk_sdio", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
899 RK3399_CLKSEL_CON(15), 8, 3, MFLAGS, 0, 7, DFLAGS,
900 RK3399_CLKGATE_CON(6), 0, GFLAGS),
901
902 COMPOSITE(SCLK_SDMMC, "clk_sdmmc", mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p, 0,
903 RK3399_CLKSEL_CON(16), 8, 3, MFLAGS, 0, 7, DFLAGS,
904 RK3399_CLKGATE_CON(6), 1, GFLAGS),
905
906 MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "clk_sdmmc", RK3399_SDMMC_CON0, 1),
907 MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "clk_sdmmc", RK3399_SDMMC_CON1, 1),
908
909 MMC(SCLK_SDIO_DRV, "sdio_drv", "clk_sdio", RK3399_SDIO_CON0, 1),
910 MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "clk_sdio", RK3399_SDIO_CON1, 1),
911
912 /* pcie */
913 COMPOSITE(SCLK_PCIE_PM, "clk_pcie_pm", mux_pll_src_cpll_gpll_npll_24m_p, 0,
914 RK3399_CLKSEL_CON(17), 8, 3, MFLAGS, 0, 7, DFLAGS,
915 RK3399_CLKGATE_CON(6), 2, GFLAGS),
916
917 COMPOSITE_NOMUX(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "npll", 0,
918 RK3399_CLKSEL_CON(18), 11, 5, DFLAGS,
919 RK3399_CLKGATE_CON(12), 6, GFLAGS),
920 MUX(SCLK_PCIEPHY_REF, "clk_pciephy_ref", mux_pll_src_24m_pciephy_p, CLK_SET_RATE_PARENT,
921 RK3399_CLKSEL_CON(18), 10, 1, MFLAGS),
922
923 COMPOSITE(0, "clk_pcie_core_cru", mux_pll_src_cpll_gpll_npll_p, 0,
924 RK3399_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 7, DFLAGS,
925 RK3399_CLKGATE_CON(6), 3, GFLAGS),
926 MUX(SCLK_PCIE_CORE, "clk_pcie_core", mux_pciecore_cru_phy_p, CLK_SET_RATE_PARENT,
927 RK3399_CLKSEL_CON(18), 7, 1, MFLAGS),
928
929 /* emmc */
930 COMPOSITE(SCLK_EMMC, "clk_emmc", mux_pll_src_cpll_gpll_npll_upll_24m_p, 0,
931 RK3399_CLKSEL_CON(22), 8, 3, MFLAGS, 0, 7, DFLAGS,
932 RK3399_CLKGATE_CON(6), 14, GFLAGS),
933
934 GATE(0, "cpll_aclk_emmc_src", "cpll", CLK_IGNORE_UNUSED,
935 RK3399_CLKGATE_CON(6), 13, GFLAGS),
936 GATE(0, "gpll_aclk_emmc_src", "gpll", CLK_IGNORE_UNUSED,
937 RK3399_CLKGATE_CON(6), 12, GFLAGS),
938 COMPOSITE_NOGATE(ACLK_EMMC, "aclk_emmc", mux_aclk_emmc_p, CLK_IGNORE_UNUSED,
939 RK3399_CLKSEL_CON(21), 7, 1, MFLAGS, 0, 5, DFLAGS),
940 GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", CLK_IGNORE_UNUSED,
941 RK3399_CLKGATE_CON(32), 8, GFLAGS),
942 GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", CLK_IGNORE_UNUSED,
943 RK3399_CLKGATE_CON(32), 9, GFLAGS),
944 GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", CLK_IGNORE_UNUSED,
945 RK3399_CLKGATE_CON(32), 10, GFLAGS),
946
947 /* perilp0 */
948 GATE(0, "cpll_aclk_perilp0_src", "cpll", CLK_IGNORE_UNUSED,
949 RK3399_CLKGATE_CON(7), 1, GFLAGS),
950 GATE(0, "gpll_aclk_perilp0_src", "gpll", CLK_IGNORE_UNUSED,
951 RK3399_CLKGATE_CON(7), 0, GFLAGS),
952 COMPOSITE(ACLK_PERILP0, "aclk_perilp0", mux_aclk_perilp0_p, CLK_IGNORE_UNUSED,
953 RK3399_CLKSEL_CON(23), 7, 1, MFLAGS, 0, 5, DFLAGS,
954 RK3399_CLKGATE_CON(7), 2, GFLAGS),
955 COMPOSITE_NOMUX(HCLK_PERILP0, "hclk_perilp0", "aclk_perilp0", CLK_IGNORE_UNUSED,
956 RK3399_CLKSEL_CON(23), 8, 2, DFLAGS,
957 RK3399_CLKGATE_CON(7), 3, GFLAGS),
958 COMPOSITE_NOMUX(PCLK_PERILP0, "pclk_perilp0", "aclk_perilp0", 0,
959 RK3399_CLKSEL_CON(23), 12, 3, DFLAGS,
960 RK3399_CLKGATE_CON(7), 4, GFLAGS),
961
962 /* aclk_perilp0 gates */
963 GATE(ACLK_INTMEM, "aclk_intmem", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 0, GFLAGS),
964 GATE(ACLK_TZMA, "aclk_tzma", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 1, GFLAGS),
965 GATE(SCLK_INTMEM0, "clk_intmem0", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 2, GFLAGS),
966 GATE(SCLK_INTMEM1, "clk_intmem1", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 3, GFLAGS),
967 GATE(SCLK_INTMEM2, "clk_intmem2", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 4, GFLAGS),
968 GATE(SCLK_INTMEM3, "clk_intmem3", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 5, GFLAGS),
969 GATE(SCLK_INTMEM4, "clk_intmem4", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 6, GFLAGS),
970 GATE(SCLK_INTMEM5, "clk_intmem5", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(23), 7, GFLAGS),
971 GATE(ACLK_DCF, "aclk_dcf", "aclk_perilp0", 0, RK3399_CLKGATE_CON(23), 8, GFLAGS),
972 GATE(ACLK_DMAC0_PERILP, "aclk_dmac0_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 5, GFLAGS),
973 GATE(ACLK_DMAC1_PERILP, "aclk_dmac1_perilp", "aclk_perilp0", 0, RK3399_CLKGATE_CON(25), 6, GFLAGS),
974 GATE(ACLK_PERILP0_NOC, "aclk_perilp0_noc", "aclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 7, GFLAGS),
975
976 /* hclk_perilp0 gates */
977 GATE(HCLK_ROM, "hclk_rom", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(24), 4, GFLAGS),
978 GATE(HCLK_M_CRYPTO0, "hclk_m_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 5, GFLAGS),
979 GATE(HCLK_S_CRYPTO0, "hclk_s_crypto0", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 6, GFLAGS),
980 GATE(HCLK_M_CRYPTO1, "hclk_m_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 14, GFLAGS),
981 GATE(HCLK_S_CRYPTO1, "hclk_s_crypto1", "hclk_perilp0", 0, RK3399_CLKGATE_CON(24), 15, GFLAGS),
982 GATE(HCLK_PERILP0_NOC, "hclk_perilp0_noc", "hclk_perilp0", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 8, GFLAGS),
983
984 /* pclk_perilp0 gates */
985 GATE(PCLK_DCF, "pclk_dcf", "pclk_perilp0", 0, RK3399_CLKGATE_CON(23), 9, GFLAGS),
986
987 /* crypto */
988 COMPOSITE(SCLK_CRYPTO0, "clk_crypto0", mux_pll_src_cpll_gpll_ppll_p, 0,
989 RK3399_CLKSEL_CON(24), 6, 2, MFLAGS, 0, 5, DFLAGS,
990 RK3399_CLKGATE_CON(7), 7, GFLAGS),
991
992 COMPOSITE(SCLK_CRYPTO1, "clk_crypto1", mux_pll_src_cpll_gpll_ppll_p, 0,
993 RK3399_CLKSEL_CON(26), 6, 2, MFLAGS, 0, 5, DFLAGS,
994 RK3399_CLKGATE_CON(7), 8, GFLAGS),
995
996 /* cm0s_perilp */
997 GATE(0, "cpll_fclk_cm0s_src", "cpll", 0,
998 RK3399_CLKGATE_CON(7), 6, GFLAGS),
999 GATE(0, "gpll_fclk_cm0s_src", "gpll", 0,
1000 RK3399_CLKGATE_CON(7), 5, GFLAGS),
1001 COMPOSITE(FCLK_CM0S, "fclk_cm0s", mux_fclk_cm0s_p, 0,
1002 RK3399_CLKSEL_CON(24), 15, 1, MFLAGS, 8, 5, DFLAGS,
1003 RK3399_CLKGATE_CON(7), 9, GFLAGS),
1004
1005 /* fclk_cm0s gates */
1006 GATE(SCLK_M0_PERILP, "sclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 8, GFLAGS),
1007 GATE(HCLK_M0_PERILP, "hclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 9, GFLAGS),
1008 GATE(DCLK_M0_PERILP, "dclk_m0_perilp", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 10, GFLAGS),
1009 GATE(SCLK_M0_PERILP_DEC, "clk_m0_perilp_dec", "fclk_cm0s", 0, RK3399_CLKGATE_CON(24), 11, GFLAGS),
1010 GATE(HCLK_M0_PERILP_NOC, "hclk_m0_perilp_noc", "fclk_cm0s", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 11, GFLAGS),
1011
1012 /* perilp1 */
1013 GATE(0, "cpll_hclk_perilp1_src", "cpll", CLK_IGNORE_UNUSED,
1014 RK3399_CLKGATE_CON(8), 1, GFLAGS),
1015 GATE(0, "gpll_hclk_perilp1_src", "gpll", CLK_IGNORE_UNUSED,
1016 RK3399_CLKGATE_CON(8), 0, GFLAGS),
1017 COMPOSITE_NOGATE(HCLK_PERILP1, "hclk_perilp1", mux_hclk_perilp1_p, CLK_IGNORE_UNUSED,
1018 RK3399_CLKSEL_CON(25), 7, 1, MFLAGS, 0, 5, DFLAGS),
1019 COMPOSITE_NOMUX(PCLK_PERILP1, "pclk_perilp1", "hclk_perilp1", CLK_IGNORE_UNUSED,
1020 RK3399_CLKSEL_CON(25), 8, 3, DFLAGS,
1021 RK3399_CLKGATE_CON(8), 2, GFLAGS),
1022
1023 /* hclk_perilp1 gates */
1024 GATE(0, "hclk_perilp1_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 9, GFLAGS),
1025 GATE(0, "hclk_sdio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(25), 12, GFLAGS),
1026 GATE(HCLK_I2S0_8CH, "hclk_i2s0", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 0, GFLAGS),
1027 GATE(HCLK_I2S1_8CH, "hclk_i2s1", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 1, GFLAGS),
1028 GATE(HCLK_I2S2_8CH, "hclk_i2s2", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 2, GFLAGS),
1029 GATE(HCLK_SPDIF, "hclk_spdif", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 3, GFLAGS),
1030 GATE(HCLK_SDIO, "hclk_sdio", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 4, GFLAGS),
1031 GATE(PCLK_SPI5, "pclk_spi5", "hclk_perilp1", 0, RK3399_CLKGATE_CON(34), 5, GFLAGS),
1032 GATE(0, "hclk_sdioaudio_noc", "hclk_perilp1", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(34), 6, GFLAGS),
1033
1034 /* pclk_perilp1 gates */
1035 GATE(PCLK_UART0, "pclk_uart0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 0, GFLAGS),
1036 GATE(PCLK_UART1, "pclk_uart1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 1, GFLAGS),
1037 GATE(PCLK_UART2, "pclk_uart2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 2, GFLAGS),
1038 GATE(PCLK_UART3, "pclk_uart3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 3, GFLAGS),
1039 GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 5, GFLAGS),
1040 GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 6, GFLAGS),
1041 GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 7, GFLAGS),
1042 GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 8, GFLAGS),
1043 GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 9, GFLAGS),
1044 GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 10, GFLAGS),
1045 GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 11, GFLAGS),
1046 GATE(PCLK_SARADC, "pclk_saradc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 12, GFLAGS),
1047 GATE(PCLK_TSADC, "pclk_tsadc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 13, GFLAGS),
1048 GATE(PCLK_EFUSE1024NS, "pclk_efuse1024ns", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 14, GFLAGS),
1049 GATE(PCLK_EFUSE1024S, "pclk_efuse1024s", "pclk_perilp1", 0, RK3399_CLKGATE_CON(22), 15, GFLAGS),
1050 GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 10, GFLAGS),
1051 GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 11, GFLAGS),
1052 GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 12, GFLAGS),
1053 GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0, RK3399_CLKGATE_CON(23), 13, GFLAGS),
1054 GATE(PCLK_PERIHP_GRF, "pclk_perilp_sgrf", "pclk_perilp1", 0, RK3399_CLKGATE_CON(24), 13, GFLAGS),
1055 GATE(0, "pclk_perilp1_noc", "pclk_perilp1", 0, RK3399_CLKGATE_CON(25), 10, GFLAGS),
1056
1057 /* saradc */
1058 COMPOSITE_NOMUX(SCLK_SARADC, "clk_saradc", "xin24m", 0,
1059 RK3399_CLKSEL_CON(26), 8, 8, DFLAGS,
1060 RK3399_CLKGATE_CON(9), 11, GFLAGS),
1061
1062 /* tsadc */
1063 COMPOSITE(SCLK_TSADC, "clk_tsadc", mux_pll_p, 0,
1064 RK3399_CLKSEL_CON(27), 15, 1, MFLAGS, 0, 10, DFLAGS,
1065 RK3399_CLKGATE_CON(9), 10, GFLAGS),
1066
1067 /* cif_testout */
1068 MUX(0, "clk_testout1_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1069 RK3399_CLKSEL_CON(38), 6, 2, MFLAGS),
1070 COMPOSITE(SCLK_TESTCLKOUT1, "clk_testout1", mux_clk_testout1_p, 0,
1071 RK3399_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
1072 RK3399_CLKGATE_CON(13), 14, GFLAGS),
1073
1074 MUX(0, "clk_testout2_pll_src", mux_pll_src_cpll_gpll_npll_p, 0,
1075 RK3399_CLKSEL_CON(38), 14, 2, MFLAGS),
1076 COMPOSITE(SCLK_TESTCLKOUT2, "clk_testout2", mux_clk_testout2_p, 0,
1077 RK3399_CLKSEL_CON(38), 13, 1, MFLAGS, 8, 5, DFLAGS,
1078 RK3399_CLKGATE_CON(13), 15, GFLAGS),
1079
1080 /* vio */
1081 COMPOSITE(ACLK_VIO, "aclk_vio", mux_pll_src_cpll_gpll_ppll_p, CLK_IGNORE_UNUSED,
1082 RK3399_CLKSEL_CON(42), 6, 2, MFLAGS, 0, 5, DFLAGS,
1083 RK3399_CLKGATE_CON(11), 0, GFLAGS),
1084 COMPOSITE_NOMUX(PCLK_VIO, "pclk_vio", "aclk_vio", 0,
1085 RK3399_CLKSEL_CON(43), 0, 5, DFLAGS,
1086 RK3399_CLKGATE_CON(11), 1, GFLAGS),
1087
1088 GATE(ACLK_VIO_NOC, "aclk_vio_noc", "aclk_vio", CLK_IGNORE_UNUSED,
1089 RK3399_CLKGATE_CON(29), 0, GFLAGS),
1090
1091 GATE(PCLK_MIPI_DSI0, "pclk_mipi_dsi0", "pclk_vio", 0,
1092 RK3399_CLKGATE_CON(29), 1, GFLAGS),
1093 GATE(PCLK_MIPI_DSI1, "pclk_mipi_dsi1", "pclk_vio", 0,
1094 RK3399_CLKGATE_CON(29), 2, GFLAGS),
1095 GATE(PCLK_VIO_GRF, "pclk_vio_grf", "pclk_vio", CLK_IGNORE_UNUSED,
1096 RK3399_CLKGATE_CON(29), 12, GFLAGS),
1097
1098 /* hdcp */
1099 COMPOSITE(ACLK_HDCP, "aclk_hdcp", mux_pll_src_cpll_gpll_ppll_p, 0,
1100 RK3399_CLKSEL_CON(42), 14, 2, MFLAGS, 8, 5, DFLAGS,
1101 RK3399_CLKGATE_CON(11), 12, GFLAGS),
1102 COMPOSITE_NOMUX(HCLK_HDCP, "hclk_hdcp", "aclk_hdcp", 0,
1103 RK3399_CLKSEL_CON(43), 5, 5, DFLAGS,
1104 RK3399_CLKGATE_CON(11), 3, GFLAGS),
1105 COMPOSITE_NOMUX(PCLK_HDCP, "pclk_hdcp", "aclk_hdcp", 0,
1106 RK3399_CLKSEL_CON(43), 10, 5, DFLAGS,
1107 RK3399_CLKGATE_CON(11), 10, GFLAGS),
1108
1109 GATE(ACLK_HDCP_NOC, "aclk_hdcp_noc", "aclk_hdcp", CLK_IGNORE_UNUSED,
1110 RK3399_CLKGATE_CON(29), 4, GFLAGS),
1111 GATE(ACLK_HDCP22, "aclk_hdcp22", "aclk_hdcp", 0,
1112 RK3399_CLKGATE_CON(29), 10, GFLAGS),
1113
1114 GATE(HCLK_HDCP_NOC, "hclk_hdcp_noc", "hclk_hdcp", CLK_IGNORE_UNUSED,
1115 RK3399_CLKGATE_CON(29), 5, GFLAGS),
1116 GATE(HCLK_HDCP22, "hclk_hdcp22", "hclk_hdcp", 0,
1117 RK3399_CLKGATE_CON(29), 9, GFLAGS),
1118
1119 GATE(PCLK_HDCP_NOC, "pclk_hdcp_noc", "pclk_hdcp", CLK_IGNORE_UNUSED,
1120 RK3399_CLKGATE_CON(29), 3, GFLAGS),
1121 GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "pclk_hdcp", 0,
1122 RK3399_CLKGATE_CON(29), 6, GFLAGS),
1123 GATE(PCLK_DP_CTRL, "pclk_dp_ctrl", "pclk_hdcp", 0,
1124 RK3399_CLKGATE_CON(29), 7, GFLAGS),
1125 GATE(PCLK_HDCP22, "pclk_hdcp22", "pclk_hdcp", 0,
1126 RK3399_CLKGATE_CON(29), 8, GFLAGS),
1127 GATE(PCLK_GASKET, "pclk_gasket", "pclk_hdcp", 0,
1128 RK3399_CLKGATE_CON(29), 11, GFLAGS),
1129
1130 /* edp */
1131 COMPOSITE(SCLK_DP_CORE, "clk_dp_core", mux_pll_src_npll_cpll_gpll_p, 0,
1132 RK3399_CLKSEL_CON(46), 6, 2, MFLAGS, 0, 5, DFLAGS,
1133 RK3399_CLKGATE_CON(11), 8, GFLAGS),
1134
1135 COMPOSITE(PCLK_EDP, "pclk_edp", mux_pll_src_cpll_gpll_p, 0,
1136 RK3399_CLKSEL_CON(44), 15, 1, MFLAGS, 8, 6, DFLAGS,
1137 RK3399_CLKGATE_CON(11), 11, GFLAGS),
1138 GATE(PCLK_EDP_NOC, "pclk_edp_noc", "pclk_edp", CLK_IGNORE_UNUSED,
1139 RK3399_CLKGATE_CON(32), 12, GFLAGS),
1140 GATE(PCLK_EDP_CTRL, "pclk_edp_ctrl", "pclk_edp", 0,
1141 RK3399_CLKGATE_CON(32), 13, GFLAGS),
1142
1143 /* hdmi */
1144 GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 0,
1145 RK3399_CLKGATE_CON(11), 6, GFLAGS),
1146
1147 COMPOSITE(SCLK_HDMI_CEC, "clk_hdmi_cec", mux_pll_p, 0,
1148 RK3399_CLKSEL_CON(45), 15, 1, MFLAGS, 0, 10, DFLAGS,
1149 RK3399_CLKGATE_CON(11), 7, GFLAGS),
1150
1151 /* vop0 */
1152 COMPOSITE(ACLK_VOP0_PRE, "aclk_vop0_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
1153 RK3399_CLKSEL_CON(47), 6, 2, MFLAGS, 0, 5, DFLAGS,
1154 RK3399_CLKGATE_CON(10), 8, GFLAGS),
1155 COMPOSITE_NOMUX(0, "hclk_vop0_pre", "aclk_vop0_pre", 0,
1156 RK3399_CLKSEL_CON(47), 8, 5, DFLAGS,
1157 RK3399_CLKGATE_CON(10), 9, GFLAGS),
1158
1159 GATE(ACLK_VOP0, "aclk_vop0", "aclk_vop0_pre", 0,
1160 RK3399_CLKGATE_CON(28), 3, GFLAGS),
1161 GATE(ACLK_VOP0_NOC, "aclk_vop0_noc", "aclk_vop0_pre", CLK_IGNORE_UNUSED,
1162 RK3399_CLKGATE_CON(28), 1, GFLAGS),
1163
1164 GATE(HCLK_VOP0, "hclk_vop0", "hclk_vop0_pre", 0,
1165 RK3399_CLKGATE_CON(28), 2, GFLAGS),
1166 GATE(HCLK_VOP0_NOC, "hclk_vop0_noc", "hclk_vop0_pre", CLK_IGNORE_UNUSED,
1167 RK3399_CLKGATE_CON(28), 0, GFLAGS),
1168
1169 COMPOSITE(DCLK_VOP0_DIV, "dclk_vop0_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1170 RK3399_CLKSEL_CON(49), 8, 2, MFLAGS, 0, 8, DFLAGS,
1171 RK3399_CLKGATE_CON(10), 12, GFLAGS),
1172
1173 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP0_FRAC, "dclk_vop0_frac", "dclk_vop0_div", 0,
1174 RK3399_CLKSEL_CON(106), 0,
1175 &rk3399_dclk_vop0_fracmux),
1176
1177 COMPOSITE(SCLK_VOP0_PWM, "clk_vop0_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, 0,
1178 RK3399_CLKSEL_CON(51), 6, 2, MFLAGS, 0, 5, DFLAGS,
1179 RK3399_CLKGATE_CON(10), 14, GFLAGS),
1180
1181 /* vop1 */
1182 COMPOSITE(ACLK_VOP1_PRE, "aclk_vop1_pre", mux_pll_src_vpll_cpll_gpll_npll_p, 0,
1183 RK3399_CLKSEL_CON(48), 6, 2, MFLAGS, 0, 5, DFLAGS,
1184 RK3399_CLKGATE_CON(10), 10, GFLAGS),
1185 COMPOSITE_NOMUX(0, "hclk_vop1_pre", "aclk_vop1_pre", 0,
1186 RK3399_CLKSEL_CON(48), 8, 5, DFLAGS,
1187 RK3399_CLKGATE_CON(10), 11, GFLAGS),
1188
1189 GATE(ACLK_VOP1, "aclk_vop1", "aclk_vop1_pre", 0,
1190 RK3399_CLKGATE_CON(28), 7, GFLAGS),
1191 GATE(ACLK_VOP1_NOC, "aclk_vop1_noc", "aclk_vop1_pre", CLK_IGNORE_UNUSED,
1192 RK3399_CLKGATE_CON(28), 5, GFLAGS),
1193
1194 GATE(HCLK_VOP1, "hclk_vop1", "hclk_vop1_pre", 0,
1195 RK3399_CLKGATE_CON(28), 6, GFLAGS),
1196 GATE(HCLK_VOP1_NOC, "hclk_vop1_noc", "hclk_vop1_pre", CLK_IGNORE_UNUSED,
1197 RK3399_CLKGATE_CON(28), 4, GFLAGS),
1198
1199 COMPOSITE(DCLK_VOP1_DIV, "dclk_vop1_div", mux_pll_src_vpll_cpll_gpll_p, 0,
1200 RK3399_CLKSEL_CON(50), 8, 2, MFLAGS, 0, 8, DFLAGS,
1201 RK3399_CLKGATE_CON(10), 13, GFLAGS),
1202
1203 COMPOSITE_FRACMUX_NOGATE(DCLK_VOP1_FRAC, "dclk_vop1_frac", "dclk_vop1_div", 0,
1204 RK3399_CLKSEL_CON(107), 0,
1205 &rk3399_dclk_vop1_fracmux),
1206
1207 COMPOSITE(SCLK_VOP1_PWM, "clk_vop1_pwm", mux_pll_src_vpll_cpll_gpll_24m_p, CLK_IGNORE_UNUSED,
1208 RK3399_CLKSEL_CON(52), 6, 2, MFLAGS, 0, 5, DFLAGS,
1209 RK3399_CLKGATE_CON(10), 15, GFLAGS),
1210
1211 /* isp */
1212 COMPOSITE(ACLK_ISP0, "aclk_isp0", mux_pll_src_cpll_gpll_ppll_p, 0,
1213 RK3399_CLKSEL_CON(53), 6, 2, MFLAGS, 0, 5, DFLAGS,
1214 RK3399_CLKGATE_CON(12), 8, GFLAGS),
1215 COMPOSITE_NOMUX(HCLK_ISP0, "hclk_isp0", "aclk_isp0", 0,
1216 RK3399_CLKSEL_CON(53), 8, 5, DFLAGS,
1217 RK3399_CLKGATE_CON(12), 9, GFLAGS),
1218
1219 GATE(ACLK_ISP0_NOC, "aclk_isp0_noc", "aclk_isp0", CLK_IGNORE_UNUSED,
1220 RK3399_CLKGATE_CON(27), 1, GFLAGS),
1221 GATE(ACLK_ISP0_WRAPPER, "aclk_isp0_wrapper", "aclk_isp0", 0,
1222 RK3399_CLKGATE_CON(27), 5, GFLAGS),
1223 GATE(HCLK_ISP1_WRAPPER, "hclk_isp1_wrapper", "aclk_isp0", 0,
1224 RK3399_CLKGATE_CON(27), 7, GFLAGS),
1225
1226 GATE(HCLK_ISP0_NOC, "hclk_isp0_noc", "hclk_isp0", CLK_IGNORE_UNUSED,
1227 RK3399_CLKGATE_CON(27), 0, GFLAGS),
1228 GATE(HCLK_ISP0_WRAPPER, "hclk_isp0_wrapper", "hclk_isp0", 0,
1229 RK3399_CLKGATE_CON(27), 4, GFLAGS),
1230
1231 COMPOSITE(SCLK_ISP0, "clk_isp0", mux_pll_src_cpll_gpll_npll_p, 0,
1232 RK3399_CLKSEL_CON(55), 6, 2, MFLAGS, 0, 5, DFLAGS,
1233 RK3399_CLKGATE_CON(11), 4, GFLAGS),
1234
1235 COMPOSITE(ACLK_ISP1, "aclk_isp1", mux_pll_src_cpll_gpll_ppll_p, 0,
1236 RK3399_CLKSEL_CON(54), 6, 2, MFLAGS, 0, 5, DFLAGS,
1237 RK3399_CLKGATE_CON(12), 10, GFLAGS),
1238 COMPOSITE_NOMUX(HCLK_ISP1, "hclk_isp1", "aclk_isp1", 0,
1239 RK3399_CLKSEL_CON(54), 8, 5, DFLAGS,
1240 RK3399_CLKGATE_CON(12), 11, GFLAGS),
1241
1242 GATE(ACLK_ISP1_NOC, "aclk_isp1_noc", "aclk_isp1", CLK_IGNORE_UNUSED,
1243 RK3399_CLKGATE_CON(27), 3, GFLAGS),
1244
1245 GATE(HCLK_ISP1_NOC, "hclk_isp1_noc", "hclk_isp1", CLK_IGNORE_UNUSED,
1246 RK3399_CLKGATE_CON(27), 2, GFLAGS),
1247 GATE(ACLK_ISP1_WRAPPER, "aclk_isp1_wrapper", "hclk_isp1", 0,
1248 RK3399_CLKGATE_CON(27), 8, GFLAGS),
1249
1250 COMPOSITE(SCLK_ISP1, "clk_isp1", mux_pll_src_cpll_gpll_npll_p, 0,
1251 RK3399_CLKSEL_CON(55), 14, 2, MFLAGS, 8, 5, DFLAGS,
1252 RK3399_CLKGATE_CON(11), 5, GFLAGS),
1253
1254 /*
1255 * We use pclkin_cifinv by default GRF_SOC_CON20[9] (GSC20_9) setting in system,
1256 * so we ignore the mux and make clocks nodes as following,
1257 *
1258 * pclkin_cifinv --|-------\
1259 * |GSC20_9|-- pclkin_cifmux -- |G27_6| -- pclkin_isp1_wrapper
1260 * pclkin_cif --|-------/
1261 */
1262 GATE(PCLK_ISP1_WRAPPER, "pclkin_isp1_wrapper", "pclkin_cif", 0,
1263 RK3399_CLKGATE_CON(27), 6, GFLAGS),
1264
1265 /* cif */
1266 COMPOSITE_NODIV(0, "clk_cifout_src", mux_pll_src_cpll_gpll_npll_p, 0,
1267 RK3399_CLKSEL_CON(56), 6, 2, MFLAGS,
1268 RK3399_CLKGATE_CON(10), 7, GFLAGS),
1269
1270 COMPOSITE_NOGATE(SCLK_CIF_OUT, "clk_cifout", mux_clk_cif_p, 0,
1271 RK3399_CLKSEL_CON(56), 5, 1, MFLAGS, 0, 5, DFLAGS),
1272
1273 /* gic */
1274 COMPOSITE(ACLK_GIC_PRE, "aclk_gic_pre", mux_pll_src_cpll_gpll_p, CLK_IGNORE_UNUSED,
1275 RK3399_CLKSEL_CON(56), 15, 1, MFLAGS, 8, 5, DFLAGS,
1276 RK3399_CLKGATE_CON(12), 12, GFLAGS),
1277
1278 GATE(ACLK_GIC, "aclk_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 0, GFLAGS),
1279 GATE(ACLK_GIC_NOC, "aclk_gic_noc", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 1, GFLAGS),
1280 GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_gic_adb400_core_l_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 2, GFLAGS),
1281 GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_gic_adb400_core_b_2_gic", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 3, GFLAGS),
1282 GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_gic_adb400_gic_2_core_l", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 4, GFLAGS),
1283 GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_gic_adb400_gic_2_core_b", "aclk_gic_pre", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(33), 5, GFLAGS),
1284
1285 /* alive */
1286 /* pclk_alive_gpll_src is controlled by PMUGRF_SOC_CON0[6] */
1287 DIV(PCLK_ALIVE, "pclk_alive", "gpll", 0,
1288 RK3399_CLKSEL_CON(57), 0, 5, DFLAGS),
1289
1290 GATE(PCLK_USBPHY_MUX_G, "pclk_usbphy_mux_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 4, GFLAGS),
1291 GATE(PCLK_UPHY0_TCPHY_G, "pclk_uphy0_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 5, GFLAGS),
1292 GATE(PCLK_UPHY0_TCPD_G, "pclk_uphy0_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 6, GFLAGS),
1293 GATE(PCLK_UPHY1_TCPHY_G, "pclk_uphy1_tcphy_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 8, GFLAGS),
1294 GATE(PCLK_UPHY1_TCPD_G, "pclk_uphy1_tcpd_g", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 9, GFLAGS),
1295
1296 GATE(PCLK_GRF, "pclk_grf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 1, GFLAGS),
1297 GATE(PCLK_INTR_ARB, "pclk_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 2, GFLAGS),
1298 GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 3, GFLAGS),
1299 GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 4, GFLAGS),
1300 GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 5, GFLAGS),
1301 GATE(PCLK_TIMER0, "pclk_timer0", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 6, GFLAGS),
1302 GATE(PCLK_TIMER1, "pclk_timer1", "pclk_alive", 0, RK3399_CLKGATE_CON(31), 7, GFLAGS),
1303 GATE(PCLK_PMU_INTR_ARB, "pclk_pmu_intr_arb", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 9, GFLAGS),
1304 GATE(PCLK_SGRF, "pclk_sgrf", "pclk_alive", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(31), 10, GFLAGS),
1305
1306 GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 0, RK3399_CLKGATE_CON(11), 14, GFLAGS),
1307 GATE(SCLK_DPHY_PLL, "clk_dphy_pll", "clk_mipidphy_ref", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 0, GFLAGS),
1308
1309 GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 0, RK3399_CLKGATE_CON(11), 15, GFLAGS),
1310 GATE(SCLK_DPHY_TX0_CFG, "clk_dphy_tx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 1, GFLAGS),
1311 GATE(SCLK_DPHY_TX1RX1_CFG, "clk_dphy_tx1rx1_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 2, GFLAGS),
1312 GATE(SCLK_DPHY_RX0_CFG, "clk_dphy_rx0_cfg", "clk_mipidphy_cfg", CLK_IGNORE_UNUSED, RK3399_CLKGATE_CON(21), 3, GFLAGS),
1313
1314 /* testout */
1315 MUX(0, "clk_test_pre", mux_pll_src_cpll_gpll_p, CLK_SET_RATE_PARENT,
1316 RK3399_CLKSEL_CON(58), 7, 1, MFLAGS),
1317 COMPOSITE_FRAC(0, "clk_test_frac", "clk_test_pre", 0,
1318 RK3399_CLKSEL_CON(105), 0,
1319 RK3399_CLKGATE_CON(13), 9, GFLAGS),
1320
1321 DIV(0, "clk_test_24m", "xin24m", 0,
1322 RK3399_CLKSEL_CON(57), 6, 10, DFLAGS),
1323
1324 /* spi */
1325 COMPOSITE(SCLK_SPI0, "clk_spi0", mux_pll_src_cpll_gpll_p, 0,
1326 RK3399_CLKSEL_CON(59), 7, 1, MFLAGS, 0, 7, DFLAGS,
1327 RK3399_CLKGATE_CON(9), 12, GFLAGS),
1328
1329 COMPOSITE(SCLK_SPI1, "clk_spi1", mux_pll_src_cpll_gpll_p, 0,
1330 RK3399_CLKSEL_CON(59), 15, 1, MFLAGS, 8, 7, DFLAGS,
1331 RK3399_CLKGATE_CON(9), 13, GFLAGS),
1332
1333 COMPOSITE(SCLK_SPI2, "clk_spi2", mux_pll_src_cpll_gpll_p, 0,
1334 RK3399_CLKSEL_CON(60), 7, 1, MFLAGS, 0, 7, DFLAGS,
1335 RK3399_CLKGATE_CON(9), 14, GFLAGS),
1336
1337 COMPOSITE(SCLK_SPI4, "clk_spi4", mux_pll_src_cpll_gpll_p, 0,
1338 RK3399_CLKSEL_CON(60), 15, 1, MFLAGS, 8, 7, DFLAGS,
1339 RK3399_CLKGATE_CON(9), 15, GFLAGS),
1340
1341 COMPOSITE(SCLK_SPI5, "clk_spi5", mux_pll_src_cpll_gpll_p, 0,
1342 RK3399_CLKSEL_CON(58), 15, 1, MFLAGS, 8, 7, DFLAGS,
1343 RK3399_CLKGATE_CON(13), 13, GFLAGS),
1344
1345 /* i2c */
1346 COMPOSITE(SCLK_I2C1, "clk_i2c1", mux_pll_src_cpll_gpll_p, 0,
1347 RK3399_CLKSEL_CON(61), 7, 1, MFLAGS, 0, 7, DFLAGS,
1348 RK3399_CLKGATE_CON(10), 0, GFLAGS),
1349
1350 COMPOSITE(SCLK_I2C2, "clk_i2c2", mux_pll_src_cpll_gpll_p, 0,
1351 RK3399_CLKSEL_CON(62), 7, 1, MFLAGS, 0, 7, DFLAGS,
1352 RK3399_CLKGATE_CON(10), 2, GFLAGS),
1353
1354 COMPOSITE(SCLK_I2C3, "clk_i2c3", mux_pll_src_cpll_gpll_p, 0,
1355 RK3399_CLKSEL_CON(63), 7, 1, MFLAGS, 0, 7, DFLAGS,
1356 RK3399_CLKGATE_CON(10), 4, GFLAGS),
1357
1358 COMPOSITE(SCLK_I2C5, "clk_i2c5", mux_pll_src_cpll_gpll_p, 0,
1359 RK3399_CLKSEL_CON(61), 15, 1, MFLAGS, 8, 7, DFLAGS,
1360 RK3399_CLKGATE_CON(10), 1, GFLAGS),
1361
1362 COMPOSITE(SCLK_I2C6, "clk_i2c6", mux_pll_src_cpll_gpll_p, 0,
1363 RK3399_CLKSEL_CON(62), 15, 1, MFLAGS, 8, 7, DFLAGS,
1364 RK3399_CLKGATE_CON(10), 3, GFLAGS),
1365
1366 COMPOSITE(SCLK_I2C7, "clk_i2c7", mux_pll_src_cpll_gpll_p, 0,
1367 RK3399_CLKSEL_CON(63), 15, 1, MFLAGS, 8, 7, DFLAGS,
1368 RK3399_CLKGATE_CON(10), 5, GFLAGS),
1369
1370 /* timer */
1371 GATE(SCLK_TIMER00, "clk_timer00", "xin24m", 0, RK3399_CLKGATE_CON(26), 0, GFLAGS),
1372 GATE(SCLK_TIMER01, "clk_timer01", "xin24m", 0, RK3399_CLKGATE_CON(26), 1, GFLAGS),
1373 GATE(SCLK_TIMER02, "clk_timer02", "xin24m", 0, RK3399_CLKGATE_CON(26), 2, GFLAGS),
1374 GATE(SCLK_TIMER03, "clk_timer03", "xin24m", 0, RK3399_CLKGATE_CON(26), 3, GFLAGS),
1375 GATE(SCLK_TIMER04, "clk_timer04", "xin24m", 0, RK3399_CLKGATE_CON(26), 4, GFLAGS),
1376 GATE(SCLK_TIMER05, "clk_timer05", "xin24m", 0, RK3399_CLKGATE_CON(26), 5, GFLAGS),
1377 GATE(SCLK_TIMER06, "clk_timer06", "xin24m", 0, RK3399_CLKGATE_CON(26), 6, GFLAGS),
1378 GATE(SCLK_TIMER07, "clk_timer07", "xin24m", 0, RK3399_CLKGATE_CON(26), 7, GFLAGS),
1379 GATE(SCLK_TIMER08, "clk_timer08", "xin24m", 0, RK3399_CLKGATE_CON(26), 8, GFLAGS),
1380 GATE(SCLK_TIMER09, "clk_timer09", "xin24m", 0, RK3399_CLKGATE_CON(26), 9, GFLAGS),
1381 GATE(SCLK_TIMER10, "clk_timer10", "xin24m", 0, RK3399_CLKGATE_CON(26), 10, GFLAGS),
1382 GATE(SCLK_TIMER11, "clk_timer11", "xin24m", 0, RK3399_CLKGATE_CON(26), 11, GFLAGS),
1383
1384 /* clk_test */
1385 /* clk_test_pre is controlled by CRU_MISC_CON[3] */
1386 COMPOSITE_NOMUX(0, "clk_test", "clk_test_pre", CLK_IGNORE_UNUSED,
1387 RK3399_CLKSEL_CON(58), 0, 5, DFLAGS,
1388 RK3399_CLKGATE_CON(13), 11, GFLAGS),
1389
1390 /* ddrc */
1391 GATE(0, "clk_ddrc_lpll_src", "lpll", 0, RK3399_CLKGATE_CON(3),
1392 0, GFLAGS),
1393 GATE(0, "clk_ddrc_bpll_src", "bpll", 0, RK3399_CLKGATE_CON(3),
1394 1, GFLAGS),
1395 GATE(0, "clk_ddrc_dpll_src", "dpll", 0, RK3399_CLKGATE_CON(3),
1396 2, GFLAGS),
1397 GATE(0, "clk_ddrc_gpll_src", "gpll", 0, RK3399_CLKGATE_CON(3),
1398 3, GFLAGS),
1399 COMPOSITE_DDRCLK(SCLK_DDRC, "sclk_ddrc", mux_ddrclk_p, 0,
1400 RK3399_CLKSEL_CON(6), 4, 2, 0, 0, ROCKCHIP_DDRCLK_SIP),
1401 };
1402
1403 static struct rockchip_clk_branch rk3399_clk_pmu_branches[] __initdata = {
1404 /*
1405 * PMU CRU Clock-Architecture
1406 */
1407
1408 GATE(0, "fclk_cm0s_pmu_ppll_src", "ppll", 0,
1409 RK3399_PMU_CLKGATE_CON(0), 1, GFLAGS),
1410
1411 COMPOSITE_NOGATE(FCLK_CM0S_SRC_PMU, "fclk_cm0s_src_pmu", mux_fclk_cm0s_pmu_ppll_p, 0,
1412 RK3399_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 8, 5, DFLAGS),
1413
1414 COMPOSITE(SCLK_SPI3_PMU, "clk_spi3_pmu", mux_24m_ppll_p, 0,
1415 RK3399_PMU_CLKSEL_CON(1), 7, 1, MFLAGS, 0, 7, DFLAGS,
1416 RK3399_PMU_CLKGATE_CON(0), 2, GFLAGS),
1417
1418 COMPOSITE(0, "clk_wifi_div", mux_ppll_24m_p, CLK_IGNORE_UNUSED,
1419 RK3399_PMU_CLKSEL_CON(1), 13, 1, MFLAGS, 8, 5, DFLAGS,
1420 RK3399_PMU_CLKGATE_CON(0), 8, GFLAGS),
1421
1422 COMPOSITE_FRACMUX_NOGATE(0, "clk_wifi_frac", "clk_wifi_div", 0,
1423 RK3399_PMU_CLKSEL_CON(7), 0,
1424 &rk3399_pmuclk_wifi_fracmux),
1425
1426 MUX(0, "clk_timer_src_pmu", mux_pll_p, CLK_IGNORE_UNUSED,
1427 RK3399_PMU_CLKSEL_CON(1), 15, 1, MFLAGS),
1428
1429 COMPOSITE_NOMUX(SCLK_I2C0_PMU, "clk_i2c0_pmu", "ppll", 0,
1430 RK3399_PMU_CLKSEL_CON(2), 0, 7, DFLAGS,
1431 RK3399_PMU_CLKGATE_CON(0), 9, GFLAGS),
1432
1433 COMPOSITE_NOMUX(SCLK_I2C4_PMU, "clk_i2c4_pmu", "ppll", 0,
1434 RK3399_PMU_CLKSEL_CON(3), 0, 7, DFLAGS,
1435 RK3399_PMU_CLKGATE_CON(0), 10, GFLAGS),
1436
1437 COMPOSITE_NOMUX(SCLK_I2C8_PMU, "clk_i2c8_pmu", "ppll", 0,
1438 RK3399_PMU_CLKSEL_CON(2), 8, 7, DFLAGS,
1439 RK3399_PMU_CLKGATE_CON(0), 11, GFLAGS),
1440
1441 DIV(0, "clk_32k_suspend_pmu", "xin24m", CLK_IGNORE_UNUSED,
1442 RK3399_PMU_CLKSEL_CON(4), 0, 10, DFLAGS),
1443 MUX(0, "clk_testout_2io", mux_clk_testout2_2io_p, CLK_IGNORE_UNUSED,
1444 RK3399_PMU_CLKSEL_CON(4), 15, 1, MFLAGS),
1445
1446 COMPOSITE(0, "clk_uart4_div", mux_24m_ppll_p, 0,
1447 RK3399_PMU_CLKSEL_CON(5), 10, 1, MFLAGS, 0, 7, DFLAGS,
1448 RK3399_PMU_CLKGATE_CON(0), 5, GFLAGS),
1449
1450 COMPOSITE_FRACMUX(0, "clk_uart4_frac", "clk_uart4_div", 0,
1451 RK3399_PMU_CLKSEL_CON(6), 0,
1452 RK3399_PMU_CLKGATE_CON(0), 6, GFLAGS,
1453 &rk3399_uart4_pmu_fracmux),
1454
1455 DIV(PCLK_SRC_PMU, "pclk_pmu_src", "ppll", CLK_IGNORE_UNUSED,
1456 RK3399_PMU_CLKSEL_CON(0), 0, 5, DFLAGS),
1457
1458 /* pmu clock gates */
1459 GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 3, GFLAGS),
1460 GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_src_pmu", 0, RK3399_PMU_CLKGATE_CON(0), 4, GFLAGS),
1461
1462 GATE(SCLK_PVTM_PMU, "clk_pvtm_pmu", "xin24m", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(0), 7, GFLAGS),
1463
1464 GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 0, GFLAGS),
1465 GATE(PCLK_PMUGRF_PMU, "pclk_pmugrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 1, GFLAGS),
1466 GATE(PCLK_INTMEM1_PMU, "pclk_intmem1_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 2, GFLAGS),
1467 GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 3, GFLAGS),
1468 GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 4, GFLAGS),
1469 GATE(PCLK_SGRF_PMU, "pclk_sgrf_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 5, GFLAGS),
1470 GATE(PCLK_NOC_PMU, "pclk_noc_pmu", "pclk_pmu_src", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(1), 6, GFLAGS),
1471 GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 7, GFLAGS),
1472 GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 8, GFLAGS),
1473 GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 9, GFLAGS),
1474 GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 10, GFLAGS),
1475 GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 11, GFLAGS),
1476 GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 12, GFLAGS),
1477 GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 13, GFLAGS),
1478 GATE(PCLK_UART4_PMU, "pclk_uart4_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 14, GFLAGS),
1479 GATE(PCLK_WDT_M0_PMU, "pclk_wdt_m0_pmu", "pclk_pmu_src", 0, RK3399_PMU_CLKGATE_CON(1), 15, GFLAGS),
1480
1481 GATE(FCLK_CM0S_PMU, "fclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 0, GFLAGS),
1482 GATE(SCLK_CM0S_PMU, "sclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 1, GFLAGS),
1483 GATE(HCLK_CM0S_PMU, "hclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 2, GFLAGS),
1484 GATE(DCLK_CM0S_PMU, "dclk_cm0s_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 3, GFLAGS),
1485 GATE(HCLK_NOC_PMU, "hclk_noc_pmu", "fclk_cm0s_src_pmu", CLK_IGNORE_UNUSED, RK3399_PMU_CLKGATE_CON(2), 5, GFLAGS),
1486 };
1487
1488 static const char *const rk3399_cru_critical_clocks[] __initconst = {
1489 "aclk_cci_pre",
1490 "aclk_gic",
1491 "aclk_gic_noc",
1492 "aclk_hdcp_noc",
1493 "hclk_hdcp_noc",
1494 "pclk_hdcp_noc",
1495 "pclk_perilp0",
1496 "pclk_perilp0",
1497 "hclk_perilp0",
1498 "hclk_perilp0_noc",
1499 "pclk_perilp1",
1500 "pclk_perilp1_noc",
1501 "pclk_perihp",
1502 "pclk_perihp_noc",
1503 "hclk_perihp",
1504 "aclk_perihp",
1505 "aclk_perihp_noc",
1506 "aclk_perilp0",
1507 "aclk_perilp0_noc",
1508 "hclk_perilp1",
1509 "hclk_perilp1_noc",
1510 "aclk_dmac0_perilp",
1511 "aclk_emmc_noc",
1512 "gpll_hclk_perilp1_src",
1513 "gpll_aclk_perilp0_src",
1514 "gpll_aclk_perihp_src",
1515 "aclk_vio_noc",
1516
1517 /* ddrc */
1518 "sclk_ddrc"
1519 };
1520
1521 static const char *const rk3399_pmucru_critical_clocks[] __initconst = {
1522 "ppll",
1523 "pclk_pmu_src",
1524 "fclk_cm0s_src_pmu",
1525 "clk_timer_src_pmu",
1526 "pclk_rkpwm_pmu",
1527 };
1528
1529 static void __init rk3399_clk_init(struct device_node *np)
1530 {
1531 struct rockchip_clk_provider *ctx;
1532 void __iomem *reg_base;
1533 struct clk *clk;
1534
1535 reg_base = of_iomap(np, 0);
1536 if (!reg_base) {
1537 pr_err("%s: could not map cru region\n", __func__);
1538 return;
1539 }
1540
1541 ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
1542 if (IS_ERR(ctx)) {
1543 pr_err("%s: rockchip clk init failed\n", __func__);
1544 iounmap(reg_base);
1545 return;
1546 }
1547
1548 /* Watchdog pclk is controlled by RK3399 SECURE_GRF_SOC_CON3[8]. */
1549 clk = clk_register_fixed_factor(NULL, "pclk_wdt", "pclk_alive", 0, 1, 1);
1550 if (IS_ERR(clk))
1551 pr_warn("%s: could not register clock pclk_wdt: %ld\n",
1552 __func__, PTR_ERR(clk));
1553 else
1554 rockchip_clk_add_lookup(ctx, clk, PCLK_WDT);
1555
1556 rockchip_clk_register_plls(ctx, rk3399_pll_clks,
1557 ARRAY_SIZE(rk3399_pll_clks), -1);
1558
1559 rockchip_clk_register_branches(ctx, rk3399_clk_branches,
1560 ARRAY_SIZE(rk3399_clk_branches));
1561
1562 rockchip_clk_protect_critical(rk3399_cru_critical_clocks,
1563 ARRAY_SIZE(rk3399_cru_critical_clocks));
1564
1565 rockchip_clk_register_armclk(ctx, ARMCLKL, "armclkl",
1566 mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
1567 &rk3399_cpuclkl_data, rk3399_cpuclkl_rates,
1568 ARRAY_SIZE(rk3399_cpuclkl_rates));
1569
1570 rockchip_clk_register_armclk(ctx, ARMCLKB, "armclkb",
1571 mux_armclkb_p, ARRAY_SIZE(mux_armclkb_p),
1572 &rk3399_cpuclkb_data, rk3399_cpuclkb_rates,
1573 ARRAY_SIZE(rk3399_cpuclkb_rates));
1574
1575 rockchip_register_softrst(np, 21, reg_base + RK3399_SOFTRST_CON(0),
1576 ROCKCHIP_SOFTRST_HIWORD_MASK);
1577
1578 rockchip_register_restart_notifier(ctx, RK3399_GLB_SRST_FST, NULL);
1579
1580 rockchip_clk_of_add_provider(np, ctx);
1581 }
1582 CLK_OF_DECLARE(rk3399_cru, "rockchip,rk3399-cru", rk3399_clk_init);
1583
1584 static void __init rk3399_pmu_clk_init(struct device_node *np)
1585 {
1586 struct rockchip_clk_provider *ctx;
1587 void __iomem *reg_base;
1588
1589 reg_base = of_iomap(np, 0);
1590 if (!reg_base) {
1591 pr_err("%s: could not map cru pmu region\n", __func__);
1592 return;
1593 }
1594
1595 ctx = rockchip_clk_init(np, reg_base, CLKPMU_NR_CLKS);
1596 if (IS_ERR(ctx)) {
1597 pr_err("%s: rockchip pmu clk init failed\n", __func__);
1598 iounmap(reg_base);
1599 return;
1600 }
1601
1602 rockchip_clk_register_plls(ctx, rk3399_pmu_pll_clks,
1603 ARRAY_SIZE(rk3399_pmu_pll_clks), -1);
1604
1605 rockchip_clk_register_branches(ctx, rk3399_clk_pmu_branches,
1606 ARRAY_SIZE(rk3399_clk_pmu_branches));
1607
1608 rockchip_clk_protect_critical(rk3399_pmucru_critical_clocks,
1609 ARRAY_SIZE(rk3399_pmucru_critical_clocks));
1610
1611 rockchip_register_softrst(np, 2, reg_base + RK3399_PMU_SOFTRST_CON(0),
1612 ROCKCHIP_SOFTRST_HIWORD_MASK);
1613
1614 rockchip_clk_of_add_provider(np, ctx);
1615 }
1616 CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
Linux with added FPC-III support