drivers/gpio/gpio-eic-sprd.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2018 Spreadtrum Communications Inc.
   4  * Copyright (C) 2018 Linaro Ltd.
   5  */
   6
   7 #include <linux/bitops.h>
   8 #include <linux/gpio/driver.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/spinlock.h>
  15
  16 /* EIC registers definition */
  17 #define SPRD_EIC_DBNC_DATA              0x0
  18 #define SPRD_EIC_DBNC_DMSK              0x4
  19 #define SPRD_EIC_DBNC_IEV               0x14
  20 #define SPRD_EIC_DBNC_IE                0x18
  21 #define SPRD_EIC_DBNC_RIS               0x1c
  22 #define SPRD_EIC_DBNC_MIS               0x20
  23 #define SPRD_EIC_DBNC_IC                0x24
  24 #define SPRD_EIC_DBNC_TRIG              0x28
  25 #define SPRD_EIC_DBNC_CTRL0             0x40
  26
  27 #define SPRD_EIC_LATCH_INTEN            0x0
  28 #define SPRD_EIC_LATCH_INTRAW           0x4
  29 #define SPRD_EIC_LATCH_INTMSK           0x8
  30 #define SPRD_EIC_LATCH_INTCLR           0xc
  31 #define SPRD_EIC_LATCH_INTPOL           0x10
  32 #define SPRD_EIC_LATCH_INTMODE          0x14
  33
  34 #define SPRD_EIC_ASYNC_INTIE            0x0
  35 #define SPRD_EIC_ASYNC_INTRAW           0x4
  36 #define SPRD_EIC_ASYNC_INTMSK           0x8
  37 #define SPRD_EIC_ASYNC_INTCLR           0xc
  38 #define SPRD_EIC_ASYNC_INTMODE          0x10
  39 #define SPRD_EIC_ASYNC_INTBOTH          0x14
  40 #define SPRD_EIC_ASYNC_INTPOL           0x18
  41 #define SPRD_EIC_ASYNC_DATA             0x1c
  42
  43 #define SPRD_EIC_SYNC_INTIE             0x0
  44 #define SPRD_EIC_SYNC_INTRAW            0x4
  45 #define SPRD_EIC_SYNC_INTMSK            0x8
  46 #define SPRD_EIC_SYNC_INTCLR            0xc
  47 #define SPRD_EIC_SYNC_INTMODE           0x10
  48 #define SPRD_EIC_SYNC_INTBOTH           0x14
  49 #define SPRD_EIC_SYNC_INTPOL            0x18
  50 #define SPRD_EIC_SYNC_DATA              0x1c
  51
  52 /*
  53  * The digital-chip EIC controller can support maximum 3 banks, and each bank
  54  * contains 8 EICs.
  55  */
  56 #define SPRD_EIC_MAX_BANK               3
  57 #define SPRD_EIC_PER_BANK_NR            8
  58 #define SPRD_EIC_DATA_MASK              GENMASK(7, 0)
  59 #define SPRD_EIC_BIT(x)                 ((x) & (SPRD_EIC_PER_BANK_NR - 1))
  60 #define SPRD_EIC_DBNC_MASK              GENMASK(11, 0)
  61
  62 /*
  63  * The Spreadtrum EIC (external interrupt controller) can be used only in
  64  * input mode to generate interrupts if detecting input signals.
  65  *
  66  * The Spreadtrum digital-chip EIC controller contains 4 sub-modules:
  67  * debounce EIC, latch EIC, async EIC and sync EIC,
  68  *
  69  * The debounce EIC is used to capture the input signals' stable status
  70  * (millisecond resolution) and a single-trigger mechanism is introduced
  71  * into this sub-module to enhance the input event detection reliability.
  72  * The debounce range is from 1ms to 4s with a step size of 1ms.
  73  *
  74  * The latch EIC is used to latch some special power down signals and
  75  * generate interrupts, since the latch EIC does not depend on the APB clock
  76  * to capture signals.
  77  *
  78  * The async EIC uses a 32k clock to capture the short signals (microsecond
  79  * resolution) to generate interrupts by level or edge trigger.
  80  *
  81  * The EIC-sync is similar with GPIO's input function, which is a synchronized
  82  * signal input register.
  83  */
  84 enum sprd_eic_type {
  85         SPRD_EIC_DEBOUNCE,
  86         SPRD_EIC_LATCH,
  87         SPRD_EIC_ASYNC,
  88         SPRD_EIC_SYNC,
  89         SPRD_EIC_MAX,
  90 };
  91
  92 struct sprd_eic {
  93         struct gpio_chip chip;
  94         struct irq_chip intc;
  95         void __iomem *base[SPRD_EIC_MAX_BANK];
  96         enum sprd_eic_type type;
  97         spinlock_t lock;
  98         int irq;
  99 };
 100
 101 struct sprd_eic_variant_data {
 102         enum sprd_eic_type type;
 103         u32 num_eics;
 104 };
 105
 106 static const char *sprd_eic_label_name[SPRD_EIC_MAX] = {
 107         "eic-debounce", "eic-latch", "eic-async",
 108         "eic-sync",
 109 };
 110
 111 static const struct sprd_eic_variant_data sc9860_eic_dbnc_data = {
 112         .type = SPRD_EIC_DEBOUNCE,
 113         .num_eics = 8,
 114 };
 115
 116 static const struct sprd_eic_variant_data sc9860_eic_latch_data = {
 117         .type = SPRD_EIC_LATCH,
 118         .num_eics = 8,
 119 };
 120
 121 static const struct sprd_eic_variant_data sc9860_eic_async_data = {
 122         .type = SPRD_EIC_ASYNC,
 123         .num_eics = 8,
 124 };
 125
 126 static const struct sprd_eic_variant_data sc9860_eic_sync_data = {
 127         .type = SPRD_EIC_SYNC,
 128         .num_eics = 8,
 129 };
 130
 131 static inline void __iomem *sprd_eic_offset_base(struct sprd_eic *sprd_eic,
 132                                                  unsigned int bank)
 133 {
 134         if (bank >= SPRD_EIC_MAX_BANK)
 135                 return NULL;
 136
 137         return sprd_eic->base[bank];
 138 }
 139
 140 static void sprd_eic_update(struct gpio_chip *chip, unsigned int offset,
 141                             u16 reg, unsigned int val)
 142 {
 143         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 144         void __iomem *base =
 145                 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
 146         unsigned long flags;
 147         u32 tmp;
 148
 149         spin_lock_irqsave(&sprd_eic->lock, flags);
 150         tmp = readl_relaxed(base + reg);
 151
 152         if (val)
 153                 tmp |= BIT(SPRD_EIC_BIT(offset));
 154         else
 155                 tmp &= ~BIT(SPRD_EIC_BIT(offset));
 156
 157         writel_relaxed(tmp, base + reg);
 158         spin_unlock_irqrestore(&sprd_eic->lock, flags);
 159 }
 160
 161 static int sprd_eic_read(struct gpio_chip *chip, unsigned int offset, u16 reg)
 162 {
 163         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 164         void __iomem *base =
 165                 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
 166
 167         return !!(readl_relaxed(base + reg) & BIT(SPRD_EIC_BIT(offset)));
 168 }
 169
 170 static int sprd_eic_request(struct gpio_chip *chip, unsigned int offset)
 171 {
 172         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 1);
 173         return 0;
 174 }
 175
 176 static void sprd_eic_free(struct gpio_chip *chip, unsigned int offset)
 177 {
 178         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_DMSK, 0);
 179 }
 180
 181 static int sprd_eic_get(struct gpio_chip *chip, unsigned int offset)
 182 {
 183         return sprd_eic_read(chip, offset, SPRD_EIC_DBNC_DATA);
 184 }
 185
 186 static int sprd_eic_direction_input(struct gpio_chip *chip, unsigned int offset)
 187 {
 188         /* EICs are always input, nothing need to do here. */
 189         return 0;
 190 }
 191
 192 static void sprd_eic_set(struct gpio_chip *chip, unsigned int offset, int value)
 193 {
 194         /* EICs are always input, nothing need to do here. */
 195 }
 196
 197 static int sprd_eic_set_debounce(struct gpio_chip *chip, unsigned int offset,
 198                                  unsigned int debounce)
 199 {
 200         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 201         void __iomem *base =
 202                 sprd_eic_offset_base(sprd_eic, offset / SPRD_EIC_PER_BANK_NR);
 203         u32 reg = SPRD_EIC_DBNC_CTRL0 + SPRD_EIC_BIT(offset) * 0x4;
 204         u32 value = readl_relaxed(base + reg) & ~SPRD_EIC_DBNC_MASK;
 205
 206         value |= (debounce / 1000) & SPRD_EIC_DBNC_MASK;
 207         writel_relaxed(value, base + reg);
 208
 209         return 0;
 210 }
 211
 212 static int sprd_eic_set_config(struct gpio_chip *chip, unsigned int offset,
 213                                unsigned long config)
 214 {
 215         unsigned long param = pinconf_to_config_param(config);
 216         u32 arg = pinconf_to_config_argument(config);
 217
 218         if (param == PIN_CONFIG_INPUT_DEBOUNCE)
 219                 return sprd_eic_set_debounce(chip, offset, arg);
 220
 221         return -ENOTSUPP;
 222 }
 223
 224 static void sprd_eic_irq_mask(struct irq_data *data)
 225 {
 226         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 227         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 228         u32 offset = irqd_to_hwirq(data);
 229
 230         switch (sprd_eic->type) {
 231         case SPRD_EIC_DEBOUNCE:
 232                 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 0);
 233                 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 0);
 234                 break;
 235         case SPRD_EIC_LATCH:
 236                 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 0);
 237                 break;
 238         case SPRD_EIC_ASYNC:
 239                 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 0);
 240                 break;
 241         case SPRD_EIC_SYNC:
 242                 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 0);
 243                 break;
 244         default:
 245                 dev_err(chip->parent, "Unsupported EIC type.\n");
 246         }
 247 }
 248
 249 static void sprd_eic_irq_unmask(struct irq_data *data)
 250 {
 251         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 252         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 253         u32 offset = irqd_to_hwirq(data);
 254
 255         switch (sprd_eic->type) {
 256         case SPRD_EIC_DEBOUNCE:
 257                 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IE, 1);
 258                 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_TRIG, 1);
 259                 break;
 260         case SPRD_EIC_LATCH:
 261                 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTEN, 1);
 262                 break;
 263         case SPRD_EIC_ASYNC:
 264                 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTIE, 1);
 265                 break;
 266         case SPRD_EIC_SYNC:
 267                 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTIE, 1);
 268                 break;
 269         default:
 270                 dev_err(chip->parent, "Unsupported EIC type.\n");
 271         }
 272 }
 273
 274 static void sprd_eic_irq_ack(struct irq_data *data)
 275 {
 276         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 277         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 278         u32 offset = irqd_to_hwirq(data);
 279
 280         switch (sprd_eic->type) {
 281         case SPRD_EIC_DEBOUNCE:
 282                 sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IC, 1);
 283                 break;
 284         case SPRD_EIC_LATCH:
 285                 sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTCLR, 1);
 286                 break;
 287         case SPRD_EIC_ASYNC:
 288                 sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTCLR, 1);
 289                 break;
 290         case SPRD_EIC_SYNC:
 291                 sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTCLR, 1);
 292                 break;
 293         default:
 294                 dev_err(chip->parent, "Unsupported EIC type.\n");
 295         }
 296 }
 297
 298 static int sprd_eic_irq_set_type(struct irq_data *data, unsigned int flow_type)
 299 {
 300         struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 301         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 302         u32 offset = irqd_to_hwirq(data);
 303         int state;
 304
 305         switch (sprd_eic->type) {
 306         case SPRD_EIC_DEBOUNCE:
 307                 switch (flow_type) {
 308                 case IRQ_TYPE_LEVEL_HIGH:
 309                         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
 310                         break;
 311                 case IRQ_TYPE_LEVEL_LOW:
 312                         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
 313                         break;
 314                 case IRQ_TYPE_EDGE_RISING:
 315                 case IRQ_TYPE_EDGE_FALLING:
 316                 case IRQ_TYPE_EDGE_BOTH:
 317                         state = sprd_eic_get(chip, offset);
 318                         if (state)
 319                                 sprd_eic_update(chip, offset,
 320                                                 SPRD_EIC_DBNC_IEV, 0);
 321                         else
 322                                 sprd_eic_update(chip, offset,
 323                                                 SPRD_EIC_DBNC_IEV, 1);
 324                         break;
 325                 default:
 326                         return -ENOTSUPP;
 327                 }
 328
 329                 irq_set_handler_locked(data, handle_level_irq);
 330                 break;
 331         case SPRD_EIC_LATCH:
 332                 switch (flow_type) {
 333                 case IRQ_TYPE_LEVEL_HIGH:
 334                         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
 335                         break;
 336                 case IRQ_TYPE_LEVEL_LOW:
 337                         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
 338                         break;
 339                 case IRQ_TYPE_EDGE_RISING:
 340                 case IRQ_TYPE_EDGE_FALLING:
 341                 case IRQ_TYPE_EDGE_BOTH:
 342                         state = sprd_eic_get(chip, offset);
 343                         if (state)
 344                                 sprd_eic_update(chip, offset,
 345                                                 SPRD_EIC_LATCH_INTPOL, 0);
 346                         else
 347                                 sprd_eic_update(chip, offset,
 348                                                 SPRD_EIC_LATCH_INTPOL, 1);
 349                         break;
 350                 default:
 351                         return -ENOTSUPP;
 352                 }
 353
 354                 irq_set_handler_locked(data, handle_level_irq);
 355                 break;
 356         case SPRD_EIC_ASYNC:
 357                 switch (flow_type) {
 358                 case IRQ_TYPE_EDGE_RISING:
 359                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
 360                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
 361                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
 362                         irq_set_handler_locked(data, handle_edge_irq);
 363                         break;
 364                 case IRQ_TYPE_EDGE_FALLING:
 365                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
 366                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 0);
 367                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
 368                         irq_set_handler_locked(data, handle_edge_irq);
 369                         break;
 370                 case IRQ_TYPE_EDGE_BOTH:
 371                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 1);
 372                         irq_set_handler_locked(data, handle_edge_irq);
 373                         break;
 374                 case IRQ_TYPE_LEVEL_HIGH:
 375                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
 376                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
 377                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 1);
 378                         irq_set_handler_locked(data, handle_level_irq);
 379                         break;
 380                 case IRQ_TYPE_LEVEL_LOW:
 381                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTBOTH, 0);
 382                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTMODE, 1);
 383                         sprd_eic_update(chip, offset, SPRD_EIC_ASYNC_INTPOL, 0);
 384                         irq_set_handler_locked(data, handle_level_irq);
 385                         break;
 386                 default:
 387                         return -ENOTSUPP;
 388                 }
 389                 break;
 390         case SPRD_EIC_SYNC:
 391                 switch (flow_type) {
 392                 case IRQ_TYPE_EDGE_RISING:
 393                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
 394                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
 395                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
 396                         irq_set_handler_locked(data, handle_edge_irq);
 397                         break;
 398                 case IRQ_TYPE_EDGE_FALLING:
 399                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
 400                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 0);
 401                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
 402                         irq_set_handler_locked(data, handle_edge_irq);
 403                         break;
 404                 case IRQ_TYPE_EDGE_BOTH:
 405                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 1);
 406                         irq_set_handler_locked(data, handle_edge_irq);
 407                         break;
 408                 case IRQ_TYPE_LEVEL_HIGH:
 409                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
 410                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
 411                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 1);
 412                         irq_set_handler_locked(data, handle_level_irq);
 413                         break;
 414                 case IRQ_TYPE_LEVEL_LOW:
 415                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTBOTH, 0);
 416                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTMODE, 1);
 417                         sprd_eic_update(chip, offset, SPRD_EIC_SYNC_INTPOL, 0);
 418                         irq_set_handler_locked(data, handle_level_irq);
 419                         break;
 420                 default:
 421                         return -ENOTSUPP;
 422                 }
 423         default:
 424                 dev_err(chip->parent, "Unsupported EIC type.\n");
 425                 return -ENOTSUPP;
 426         }
 427
 428         return 0;
 429 }
 430
 431 static void sprd_eic_toggle_trigger(struct gpio_chip *chip, unsigned int irq,
 432                                     unsigned int offset)
 433 {
 434         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 435         struct irq_data *data = irq_get_irq_data(irq);
 436         u32 trigger = irqd_get_trigger_type(data);
 437         int state, post_state;
 438
 439         /*
 440          * The debounce EIC and latch EIC can only support level trigger, so we
 441          * can toggle the level trigger to emulate the edge trigger.
 442          */
 443         if ((sprd_eic->type != SPRD_EIC_DEBOUNCE &&
 444              sprd_eic->type != SPRD_EIC_LATCH) ||
 445             !(trigger & IRQ_TYPE_EDGE_BOTH))
 446                 return;
 447
 448         sprd_eic_irq_mask(data);
 449         state = sprd_eic_get(chip, offset);
 450
 451 retry:
 452         switch (sprd_eic->type) {
 453         case SPRD_EIC_DEBOUNCE:
 454                 if (state)
 455                         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 0);
 456                 else
 457                         sprd_eic_update(chip, offset, SPRD_EIC_DBNC_IEV, 1);
 458                 break;
 459         case SPRD_EIC_LATCH:
 460                 if (state)
 461                         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 0);
 462                 else
 463                         sprd_eic_update(chip, offset, SPRD_EIC_LATCH_INTPOL, 1);
 464                 break;
 465         default:
 466                 sprd_eic_irq_unmask(data);
 467                 return;
 468         }
 469
 470         post_state = sprd_eic_get(chip, offset);
 471         if (state != post_state) {
 472                 dev_warn(chip->parent, "EIC level was changed.\n");
 473                 state = post_state;
 474                 goto retry;
 475         }
 476
 477         sprd_eic_irq_unmask(data);
 478 }
 479
 480 static int sprd_eic_match_chip_by_type(struct gpio_chip *chip, void *data)
 481 {
 482         enum sprd_eic_type type = *(enum sprd_eic_type *)data;
 483
 484         return !strcmp(chip->label, sprd_eic_label_name[type]);
 485 }
 486
 487 static void sprd_eic_handle_one_type(struct gpio_chip *chip)
 488 {
 489         struct sprd_eic *sprd_eic = gpiochip_get_data(chip);
 490         u32 bank, n, girq;
 491
 492         for (bank = 0; bank * SPRD_EIC_PER_BANK_NR < chip->ngpio; bank++) {
 493                 void __iomem *base = sprd_eic_offset_base(sprd_eic, bank);
 494                 unsigned long reg;
 495
 496                 switch (sprd_eic->type) {
 497                 case SPRD_EIC_DEBOUNCE:
 498                         reg = readl_relaxed(base + SPRD_EIC_DBNC_MIS) &
 499                                 SPRD_EIC_DATA_MASK;
 500                         break;
 501                 case SPRD_EIC_LATCH:
 502                         reg = readl_relaxed(base + SPRD_EIC_LATCH_INTMSK) &
 503                                 SPRD_EIC_DATA_MASK;
 504                         break;
 505                 case SPRD_EIC_ASYNC:
 506                         reg = readl_relaxed(base + SPRD_EIC_ASYNC_INTMSK) &
 507                                 SPRD_EIC_DATA_MASK;
 508                         break;
 509                 case SPRD_EIC_SYNC:
 510                         reg = readl_relaxed(base + SPRD_EIC_SYNC_INTMSK) &
 511                                 SPRD_EIC_DATA_MASK;
 512                         break;
 513                 default:
 514                         dev_err(chip->parent, "Unsupported EIC type.\n");
 515                         return;
 516                 }
 517
 518                 for_each_set_bit(n, &reg, SPRD_EIC_PER_BANK_NR) {
 519                         girq = irq_find_mapping(chip->irq.domain,
 520                                         bank * SPRD_EIC_PER_BANK_NR + n);
 521
 522                         generic_handle_irq(girq);
 523                         sprd_eic_toggle_trigger(chip, girq, n);
 524                 }
 525         }
 526 }
 527
 528 static void sprd_eic_irq_handler(struct irq_desc *desc)
 529 {
 530         struct irq_chip *ic = irq_desc_get_chip(desc);
 531         struct gpio_chip *chip;
 532         enum sprd_eic_type type;
 533
 534         chained_irq_enter(ic, desc);
 535
 536         /*
 537          * Since the digital-chip EIC 4 sub-modules (debounce, latch, async
 538          * and sync) share one same interrupt line, we should iterate each
 539          * EIC module to check if there are EIC interrupts were triggered.
 540          */
 541         for (type = SPRD_EIC_DEBOUNCE; type < SPRD_EIC_MAX; type++) {
 542                 chip = gpiochip_find(&type, sprd_eic_match_chip_by_type);
 543                 if (!chip)
 544                         continue;
 545
 546                 sprd_eic_handle_one_type(chip);
 547         }
 548
 549         chained_irq_exit(ic, desc);
 550 }
 551
 552 static int sprd_eic_probe(struct platform_device *pdev)
 553 {
 554         const struct sprd_eic_variant_data *pdata;
 555         struct gpio_irq_chip *irq;
 556         struct sprd_eic *sprd_eic;
 557         struct resource *res;
 558         int ret, i;
 559
 560         pdata = of_device_get_match_data(&pdev->dev);
 561         if (!pdata) {
 562                 dev_err(&pdev->dev, "No matching driver data found.\n");
 563                 return -EINVAL;
 564         }
 565
 566         sprd_eic = devm_kzalloc(&pdev->dev, sizeof(*sprd_eic), GFP_KERNEL);
 567         if (!sprd_eic)
 568                 return -ENOMEM;
 569
 570         spin_lock_init(&sprd_eic->lock);
 571         sprd_eic->type = pdata->type;
 572
 573         sprd_eic->irq = platform_get_irq(pdev, 0);
 574         if (sprd_eic->irq < 0) {
 575                 dev_err(&pdev->dev, "Failed to get EIC interrupt.\n");
 576                 return sprd_eic->irq;
 577         }
 578
 579         for (i = 0; i < SPRD_EIC_MAX_BANK; i++) {
 580                 /*
 581                  * We can have maximum 3 banks EICs, and each EIC has
 582                  * its own base address. But some platform maybe only
 583                  * have one bank EIC, thus base[1] and base[2] can be
 584                  * optional.
 585                  */
 586                 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
 587                 if (!res)
 588                         continue;
 589
 590                 sprd_eic->base[i] = devm_ioremap_resource(&pdev->dev, res);
 591                 if (IS_ERR(sprd_eic->base[i]))
 592                         return PTR_ERR(sprd_eic->base[i]);
 593         }
 594
 595         sprd_eic->chip.label = sprd_eic_label_name[sprd_eic->type];
 596         sprd_eic->chip.ngpio = pdata->num_eics;
 597         sprd_eic->chip.base = -1;
 598         sprd_eic->chip.parent = &pdev->dev;
 599         sprd_eic->chip.of_node = pdev->dev.of_node;
 600         sprd_eic->chip.direction_input = sprd_eic_direction_input;
 601         switch (sprd_eic->type) {
 602         case SPRD_EIC_DEBOUNCE:
 603                 sprd_eic->chip.request = sprd_eic_request;
 604                 sprd_eic->chip.free = sprd_eic_free;
 605                 sprd_eic->chip.set_config = sprd_eic_set_config;
 606                 sprd_eic->chip.set = sprd_eic_set;
 607                 /* fall-through */
 608         case SPRD_EIC_ASYNC:
 609                 /* fall-through */
 610         case SPRD_EIC_SYNC:
 611                 sprd_eic->chip.get = sprd_eic_get;
 612                 break;
 613         case SPRD_EIC_LATCH:
 614                 /* fall-through */
 615         default:
 616                 break;
 617         }
 618
 619         sprd_eic->intc.name = dev_name(&pdev->dev);
 620         sprd_eic->intc.irq_ack = sprd_eic_irq_ack;
 621         sprd_eic->intc.irq_mask = sprd_eic_irq_mask;
 622         sprd_eic->intc.irq_unmask = sprd_eic_irq_unmask;
 623         sprd_eic->intc.irq_set_type = sprd_eic_irq_set_type;
 624         sprd_eic->intc.flags = IRQCHIP_SKIP_SET_WAKE;
 625
 626         irq = &sprd_eic->chip.irq;
 627         irq->chip = &sprd_eic->intc;
 628         irq->handler = handle_bad_irq;
 629         irq->default_type = IRQ_TYPE_NONE;
 630         irq->parent_handler = sprd_eic_irq_handler;
 631         irq->parent_handler_data = sprd_eic;
 632         irq->num_parents = 1;
 633         irq->parents = &sprd_eic->irq;
 634
 635         ret = devm_gpiochip_add_data(&pdev->dev, &sprd_eic->chip, sprd_eic);
 636         if (ret < 0) {
 637                 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret);
 638                 return ret;
 639         }
 640
 641         platform_set_drvdata(pdev, sprd_eic);
 642         return 0;
 643 }
 644
 645 static const struct of_device_id sprd_eic_of_match[] = {
 646         {
 647                 .compatible = "sprd,sc9860-eic-debounce",
 648                 .data = &sc9860_eic_dbnc_data,
 649         },
 650         {
 651                 .compatible = "sprd,sc9860-eic-latch",
 652                 .data = &sc9860_eic_latch_data,
 653         },
 654         {
 655                 .compatible = "sprd,sc9860-eic-async",
 656                 .data = &sc9860_eic_async_data,
 657         },
 658         {
 659                 .compatible = "sprd,sc9860-eic-sync",
 660                 .data = &sc9860_eic_sync_data,
 661         },
 662         {
 663                 /* end of list */
 664         }
 665 };
 666 MODULE_DEVICE_TABLE(of, sprd_eic_of_match);
 667
 668 static struct platform_driver sprd_eic_driver = {
 669         .probe = sprd_eic_probe,
 670         .driver = {
 671                 .name = "sprd-eic",
 672                 .of_match_table = sprd_eic_of_match,
 673         },
 674 };
 675
 676 module_platform_driver(sprd_eic_driver);
 677
 678 MODULE_DESCRIPTION("Spreadtrum EIC driver");
 679 MODULE_LICENSE("GPL v2");