drivers/media/i2c/adv748x/adv748x.h

   1 /*
   2  * Driver for Analog Devices ADV748X video decoder and HDMI receiver
   3  *
   4  * Copyright (C) 2017 Renesas Electronics Corp.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  *
  11  * Authors:
  12  *      Koji Matsuoka <koji.matsuoka.xm@renesas.com>
  13  *      Niklas Söderlund <niklas.soderlund@ragnatech.se>
  14  *      Kieran Bingham <kieran.bingham@ideasonboard.com>
  15  *
  16  * The ADV748x range of receivers have the following configurations:
  17  *
  18  *                  Analog   HDMI  MHL  4-Lane  1-Lane
  19  *                    In      In         CSI     CSI
  20  *       ADV7480               X    X     X
  21  *       ADV7481      X        X    X     X       X
  22  *       ADV7482      X        X          X       X
  23  */
  24
  25 #include <linux/i2c.h>
  26
  27 #ifndef _ADV748X_H_
  28 #define _ADV748X_H_
  29
  30 enum adv748x_page {
  31         ADV748X_PAGE_IO,
  32         ADV748X_PAGE_DPLL,
  33         ADV748X_PAGE_CP,
  34         ADV748X_PAGE_HDMI,
  35         ADV748X_PAGE_EDID,
  36         ADV748X_PAGE_REPEATER,
  37         ADV748X_PAGE_INFOFRAME,
  38         ADV748X_PAGE_CBUS,
  39         ADV748X_PAGE_CEC,
  40         ADV748X_PAGE_SDP,
  41         ADV748X_PAGE_TXB,
  42         ADV748X_PAGE_TXA,
  43         ADV748X_PAGE_MAX,
  44
  45         /* Fake pages for register sequences */
  46         ADV748X_PAGE_WAIT,              /* Wait x msec */
  47         ADV748X_PAGE_EOR,               /* End Mark */
  48 };
  49
  50 /**
  51  * enum adv748x_ports - Device tree port number definitions
  52  *
  53  * The ADV748X ports define the mapping between subdevices
  54  * and the device tree specification
  55  */
  56 enum adv748x_ports {
  57         ADV748X_PORT_AIN0 = 0,
  58         ADV748X_PORT_AIN1 = 1,
  59         ADV748X_PORT_AIN2 = 2,
  60         ADV748X_PORT_AIN3 = 3,
  61         ADV748X_PORT_AIN4 = 4,
  62         ADV748X_PORT_AIN5 = 5,
  63         ADV748X_PORT_AIN6 = 6,
  64         ADV748X_PORT_AIN7 = 7,
  65         ADV748X_PORT_HDMI = 8,
  66         ADV748X_PORT_TTL = 9,
  67         ADV748X_PORT_TXA = 10,
  68         ADV748X_PORT_TXB = 11,
  69         ADV748X_PORT_MAX = 12,
  70 };
  71
  72 enum adv748x_csi2_pads {
  73         ADV748X_CSI2_SINK,
  74         ADV748X_CSI2_SOURCE,
  75         ADV748X_CSI2_NR_PADS,
  76 };
  77
  78 /* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
  79 #define ADV748X_CSI2_MAX_SUBDEVS 2
  80
  81 struct adv748x_csi2 {
  82         struct adv748x_state *state;
  83         struct v4l2_mbus_framefmt format;
  84         unsigned int page;
  85
  86         struct media_pad pads[ADV748X_CSI2_NR_PADS];
  87         struct v4l2_ctrl_handler ctrl_hdl;
  88         struct v4l2_ctrl *pixel_rate;
  89         struct v4l2_subdev sd;
  90 };
  91
  92 #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
  93 #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
  94
  95 enum adv748x_hdmi_pads {
  96         ADV748X_HDMI_SINK,
  97         ADV748X_HDMI_SOURCE,
  98         ADV748X_HDMI_NR_PADS,
  99 };
 100
 101 struct adv748x_hdmi {
 102         struct media_pad pads[ADV748X_HDMI_NR_PADS];
 103         struct v4l2_ctrl_handler ctrl_hdl;
 104         struct v4l2_subdev sd;
 105         struct v4l2_mbus_framefmt format;
 106
 107         struct v4l2_dv_timings timings;
 108         struct v4l2_fract aspect_ratio;
 109
 110         struct {
 111                 u8 edid[512];
 112                 u32 present;
 113                 unsigned int blocks;
 114         } edid;
 115 };
 116
 117 #define adv748x_ctrl_to_hdmi(ctrl) \
 118         container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
 119 #define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
 120
 121 enum adv748x_afe_pads {
 122         ADV748X_AFE_SINK_AIN0,
 123         ADV748X_AFE_SINK_AIN1,
 124         ADV748X_AFE_SINK_AIN2,
 125         ADV748X_AFE_SINK_AIN3,
 126         ADV748X_AFE_SINK_AIN4,
 127         ADV748X_AFE_SINK_AIN5,
 128         ADV748X_AFE_SINK_AIN6,
 129         ADV748X_AFE_SINK_AIN7,
 130         ADV748X_AFE_SOURCE,
 131         ADV748X_AFE_NR_PADS,
 132 };
 133
 134 struct adv748x_afe {
 135         struct media_pad pads[ADV748X_AFE_NR_PADS];
 136         struct v4l2_ctrl_handler ctrl_hdl;
 137         struct v4l2_subdev sd;
 138         struct v4l2_mbus_framefmt format;
 139
 140         bool streaming;
 141         v4l2_std_id curr_norm;
 142         unsigned int input;
 143 };
 144
 145 #define adv748x_ctrl_to_afe(ctrl) \
 146         container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
 147 #define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
 148
 149 /**
 150  * struct adv748x_state - State of ADV748X
 151  * @dev:                (OF) device
 152  * @client:             I2C client
 153  * @mutex:              protect global state
 154  *
 155  * @endpoints:          parsed device node endpoints for each port
 156  *
 157  * @i2c_addresses       I2C Page addresses
 158  * @i2c_clients         I2C clients for the page accesses
 159  * @regmap              regmap configuration pages.
 160  *
 161  * @hdmi:               state of HDMI receiver context
 162  * @afe:                state of AFE receiver context
 163  * @txa:                state of TXA transmitter context
 164  * @txb:                state of TXB transmitter context
 165  */
 166 struct adv748x_state {
 167         struct device *dev;
 168         struct i2c_client *client;
 169         struct mutex mutex;
 170
 171         struct device_node *endpoints[ADV748X_PORT_MAX];
 172
 173         struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
 174         struct regmap *regmap[ADV748X_PAGE_MAX];
 175
 176         struct adv748x_hdmi hdmi;
 177         struct adv748x_afe afe;
 178         struct adv748x_csi2 txa;
 179         struct adv748x_csi2 txb;
 180 };
 181
 182 #define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
 183 #define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
 184
 185 #define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
 186 #define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
 187 #define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
 188
 189 /* Register Mappings */
 190
 191 /* IO Map */
 192 #define ADV748X_IO_PD                   0x00    /* power down controls */
 193 #define ADV748X_IO_PD_RX_EN             BIT(6)
 194
 195 #define ADV748X_IO_REG_04               0x04
 196 #define ADV748X_IO_REG_04_FORCE_FR      BIT(0)  /* Force CP free-run */
 197
 198 #define ADV748X_IO_DATAPATH             0x03    /* datapath cntrl */
 199 #define ADV748X_IO_DATAPATH_VFREQ_M     0x70
 200 #define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
 201
 202 #define ADV748X_IO_VID_STD              0x05
 203
 204 #define ADV748X_IO_10                   0x10    /* io_reg_10 */
 205 #define ADV748X_IO_10_CSI4_EN           BIT(7)
 206 #define ADV748X_IO_10_CSI1_EN           BIT(6)
 207 #define ADV748X_IO_10_PIX_OUT_EN        BIT(5)
 208
 209 #define ADV748X_IO_CHIP_REV_ID_1        0xdf
 210 #define ADV748X_IO_CHIP_REV_ID_2        0xe0
 211
 212 #define ADV748X_IO_SLAVE_ADDR_BASE      0xf2
 213
 214 /* HDMI RX Map */
 215 #define ADV748X_HDMI_LW1                0x07    /* line width_1 */
 216 #define ADV748X_HDMI_LW1_VERT_FILTER    BIT(7)
 217 #define ADV748X_HDMI_LW1_DE_REGEN       BIT(5)
 218 #define ADV748X_HDMI_LW1_WIDTH_MASK     0x1fff
 219
 220 #define ADV748X_HDMI_F0H1               0x09    /* field0 height_1 */
 221 #define ADV748X_HDMI_F0H1_HEIGHT_MASK   0x1fff
 222
 223 #define ADV748X_HDMI_F1H1               0x0b    /* field1 height_1 */
 224 #define ADV748X_HDMI_F1H1_INTERLACED    BIT(5)
 225
 226 #define ADV748X_HDMI_HFRONT_PORCH       0x20    /* hsync_front_porch_1 */
 227 #define ADV748X_HDMI_HFRONT_PORCH_MASK  0x1fff
 228
 229 #define ADV748X_HDMI_HSYNC_WIDTH        0x22    /* hsync_pulse_width_1 */
 230 #define ADV748X_HDMI_HSYNC_WIDTH_MASK   0x1fff
 231
 232 #define ADV748X_HDMI_HBACK_PORCH        0x24    /* hsync_back_porch_1 */
 233 #define ADV748X_HDMI_HBACK_PORCH_MASK   0x1fff
 234
 235 #define ADV748X_HDMI_VFRONT_PORCH       0x2a    /* field0_vs_front_porch_1 */
 236 #define ADV748X_HDMI_VFRONT_PORCH_MASK  0x3fff
 237
 238 #define ADV748X_HDMI_VSYNC_WIDTH        0x2e    /* field0_vs_pulse_width_1 */
 239 #define ADV748X_HDMI_VSYNC_WIDTH_MASK   0x3fff
 240
 241 #define ADV748X_HDMI_VBACK_PORCH        0x32    /* field0_vs_back_porch_1 */
 242 #define ADV748X_HDMI_VBACK_PORCH_MASK   0x3fff
 243
 244 #define ADV748X_HDMI_TMDS_1             0x51    /* hdmi_reg_51 */
 245 #define ADV748X_HDMI_TMDS_2             0x52    /* hdmi_reg_52 */
 246
 247 /* HDMI RX Repeater Map */
 248 #define ADV748X_REPEATER_EDID_SZ        0x70    /* primary_edid_size */
 249 #define ADV748X_REPEATER_EDID_SZ_SHIFT  4
 250
 251 #define ADV748X_REPEATER_EDID_CTL       0x74    /* hdcp edid controls */
 252 #define ADV748X_REPEATER_EDID_CTL_EN    BIT(0)  /* man_edid_a_enable */
 253
 254 /* SDP Main Map */
 255 #define ADV748X_SDP_INSEL               0x00    /* user_map_rw_reg_00 */
 256
 257 #define ADV748X_SDP_VID_SEL             0x02    /* user_map_rw_reg_02 */
 258 #define ADV748X_SDP_VID_SEL_MASK        0xf0
 259 #define ADV748X_SDP_VID_SEL_SHIFT       4
 260
 261 /* Contrast - Unsigned*/
 262 #define ADV748X_SDP_CON                 0x08    /* user_map_rw_reg_08 */
 263 #define ADV748X_SDP_CON_MIN             0
 264 #define ADV748X_SDP_CON_DEF             128
 265 #define ADV748X_SDP_CON_MAX             255
 266
 267 /* Brightness - Signed */
 268 #define ADV748X_SDP_BRI                 0x0a    /* user_map_rw_reg_0a */
 269 #define ADV748X_SDP_BRI_MIN             -128
 270 #define ADV748X_SDP_BRI_DEF             0
 271 #define ADV748X_SDP_BRI_MAX             127
 272
 273 /* Hue - Signed, inverted*/
 274 #define ADV748X_SDP_HUE                 0x0b    /* user_map_rw_reg_0b */
 275 #define ADV748X_SDP_HUE_MIN             -127
 276 #define ADV748X_SDP_HUE_DEF             0
 277 #define ADV748X_SDP_HUE_MAX             128
 278
 279 /* Test Patterns / Default Values */
 280 #define ADV748X_SDP_DEF                 0x0c    /* user_map_rw_reg_0c */
 281 #define ADV748X_SDP_DEF_VAL_EN          BIT(0)  /* Force free run mode */
 282 #define ADV748X_SDP_DEF_VAL_AUTO_EN     BIT(1)  /* Free run when no signal */
 283
 284 #define ADV748X_SDP_MAP_SEL             0x0e    /* user_map_rw_reg_0e */
 285 #define ADV748X_SDP_MAP_SEL_RO_MAIN     1
 286
 287 /* Free run pattern select */
 288 #define ADV748X_SDP_FRP                 0x14
 289 #define ADV748X_SDP_FRP_MASK            GENMASK(3, 1)
 290
 291 /* Saturation */
 292 #define ADV748X_SDP_SD_SAT_U            0xe3    /* user_map_rw_reg_e3 */
 293 #define ADV748X_SDP_SD_SAT_V            0xe4    /* user_map_rw_reg_e4 */
 294 #define ADV748X_SDP_SAT_MIN             0
 295 #define ADV748X_SDP_SAT_DEF             128
 296 #define ADV748X_SDP_SAT_MAX             255
 297
 298 /* SDP RO Main Map */
 299 #define ADV748X_SDP_RO_10               0x10
 300 #define ADV748X_SDP_RO_10_IN_LOCK       BIT(0)
 301
 302 /* CP Map */
 303 #define ADV748X_CP_PAT_GEN              0x37    /* int_pat_gen_1 */
 304 #define ADV748X_CP_PAT_GEN_EN           BIT(7)
 305
 306 /* Contrast Control - Unsigned */
 307 #define ADV748X_CP_CON                  0x3a    /* contrast_cntrl */
 308 #define ADV748X_CP_CON_MIN              0       /* Minimum contrast */
 309 #define ADV748X_CP_CON_DEF              128     /* Default */
 310 #define ADV748X_CP_CON_MAX              255     /* Maximum contrast */
 311
 312 /* Saturation Control - Unsigned */
 313 #define ADV748X_CP_SAT                  0x3b    /* saturation_cntrl */
 314 #define ADV748X_CP_SAT_MIN              0       /* Minimum saturation */
 315 #define ADV748X_CP_SAT_DEF              128     /* Default */
 316 #define ADV748X_CP_SAT_MAX              255     /* Maximum saturation */
 317
 318 /* Brightness Control - Signed */
 319 #define ADV748X_CP_BRI                  0x3c    /* brightness_cntrl */
 320 #define ADV748X_CP_BRI_MIN              -128    /* Luma is -512d */
 321 #define ADV748X_CP_BRI_DEF              0       /* Luma is 0 */
 322 #define ADV748X_CP_BRI_MAX              127     /* Luma is 508d */
 323
 324 /* Hue Control */
 325 #define ADV748X_CP_HUE                  0x3d    /* hue_cntrl */
 326 #define ADV748X_CP_HUE_MIN              0       /* -90 degree */
 327 #define ADV748X_CP_HUE_DEF              0       /* -90 degree */
 328 #define ADV748X_CP_HUE_MAX              255     /* +90 degree */
 329
 330 #define ADV748X_CP_VID_ADJ              0x3e    /* vid_adj_0 */
 331 #define ADV748X_CP_VID_ADJ_ENABLE       BIT(7)  /* Enable colour controls */
 332
 333 #define ADV748X_CP_DE_POS_HIGH          0x8b    /* de_pos_adj_6 */
 334 #define ADV748X_CP_DE_POS_HIGH_SET      BIT(6)
 335 #define ADV748X_CP_DE_POS_END_LOW       0x8c    /* de_pos_adj_7 */
 336 #define ADV748X_CP_DE_POS_START_LOW     0x8d    /* de_pos_adj_8 */
 337
 338 #define ADV748X_CP_VID_ADJ_2                    0x91
 339 #define ADV748X_CP_VID_ADJ_2_INTERLACED         BIT(6)
 340 #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D      BIT(4)
 341
 342 #define ADV748X_CP_CLMP_POS             0xc9    /* clmp_pos_cntrl_4 */
 343 #define ADV748X_CP_CLMP_POS_DIS_AUTO    BIT(0)  /* dis_auto_param_buff */
 344
 345 /* CSI : TXA/TXB Maps */
 346 #define ADV748X_CSI_VC_REF              0x0d    /* csi_tx_top_reg_0d */
 347 #define ADV748X_CSI_VC_REF_SHIFT        6
 348
 349 #define ADV748X_CSI_FS_AS_LS            0x1e    /* csi_tx_top_reg_1e */
 350 #define ADV748X_CSI_FS_AS_LS_UNKNOWN    BIT(6)  /* Undocumented bit */
 351
 352 /* Register handling */
 353
 354 int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
 355 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
 356 int adv748x_write_block(struct adv748x_state *state, int client_page,
 357                         unsigned int init_reg, const void *val,
 358                         size_t val_len);
 359
 360 #define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
 361 #define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
 362 #define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~m) | v)
 363
 364 #define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
 365 #define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, r+1)) & m)
 366 #define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
 367
 368 #define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
 369 #define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
 370
 371 #define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
 372 #define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
 373 #define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~m) | v)
 374
 375 #define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
 376 #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
 377 #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~m) | v)
 378
 379 #define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r)
 380 #define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r)
 381
 382 #define tx_read(t, r) adv748x_read(t->state, t->page, r)
 383 #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
 384
 385 static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
 386 {
 387         pad = media_entity_remote_pad(pad);
 388         if (!pad)
 389                 return NULL;
 390
 391         return media_entity_to_v4l2_subdev(pad->entity);
 392 }
 393
 394 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
 395                          const struct v4l2_subdev_ops *ops, u32 function,
 396                          const char *ident);
 397
 398 int adv748x_register_subdevs(struct adv748x_state *state,
 399                              struct v4l2_device *v4l2_dev);
 400
 401 int adv748x_txa_power(struct adv748x_state *state, bool on);
 402 int adv748x_txb_power(struct adv748x_state *state, bool on);
 403
 404 int adv748x_afe_init(struct adv748x_afe *afe);
 405 void adv748x_afe_cleanup(struct adv748x_afe *afe);
 406
 407 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
 408 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
 409 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
 410
 411 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
 412 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
 413
 414 #endif /* _ADV748X_H_ */