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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / media / i2c / mt9v032.c
blobf74730d24d8fe38bf049fb3020fa5493c2f64a49
1 /*
2 * Driver for MT9V022, MT9V024, MT9V032, and MT9V034 CMOS Image Sensors
3 *
4 * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
5 *
6 * Based on the MT9M001 driver,
7 *
8 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/i2c.h>
19 #include <linux/log2.h>
20 #include <linux/mutex.h>
21 #include <linux/of.h>
22 #include <linux/of_graph.h>
23 #include <linux/regmap.h>
24 #include <linux/slab.h>
25 #include <linux/videodev2.h>
26 #include <linux/v4l2-mediabus.h>
27 #include <linux/module.h>
28
29 #include <media/i2c/mt9v032.h>
30 #include <media/v4l2-ctrls.h>
31 #include <media/v4l2-device.h>
32 #include <media/v4l2-fwnode.h>
33 #include <media/v4l2-subdev.h>
34
35 /* The first four rows are black rows. The active area spans 753x481 pixels. */
36 #define MT9V032_PIXEL_ARRAY_HEIGHT 485
37 #define MT9V032_PIXEL_ARRAY_WIDTH 753
38
39 #define MT9V032_SYSCLK_FREQ_DEF 26600000
40
41 #define MT9V032_CHIP_VERSION 0x00
42 #define MT9V032_CHIP_ID_REV1 0x1311
43 #define MT9V032_CHIP_ID_REV3 0x1313
44 #define MT9V034_CHIP_ID_REV1 0X1324
45 #define MT9V032_COLUMN_START 0x01
46 #define MT9V032_COLUMN_START_MIN 1
47 #define MT9V032_COLUMN_START_DEF 1
48 #define MT9V032_COLUMN_START_MAX 752
49 #define MT9V032_ROW_START 0x02
50 #define MT9V032_ROW_START_MIN 4
51 #define MT9V032_ROW_START_DEF 5
52 #define MT9V032_ROW_START_MAX 482
53 #define MT9V032_WINDOW_HEIGHT 0x03
54 #define MT9V032_WINDOW_HEIGHT_MIN 1
55 #define MT9V032_WINDOW_HEIGHT_DEF 480
56 #define MT9V032_WINDOW_HEIGHT_MAX 480
57 #define MT9V032_WINDOW_WIDTH 0x04
58 #define MT9V032_WINDOW_WIDTH_MIN 1
59 #define MT9V032_WINDOW_WIDTH_DEF 752
60 #define MT9V032_WINDOW_WIDTH_MAX 752
61 #define MT9V032_HORIZONTAL_BLANKING 0x05
62 #define MT9V032_HORIZONTAL_BLANKING_MIN 43
63 #define MT9V034_HORIZONTAL_BLANKING_MIN 61
64 #define MT9V032_HORIZONTAL_BLANKING_DEF 94
65 #define MT9V032_HORIZONTAL_BLANKING_MAX 1023
66 #define MT9V032_VERTICAL_BLANKING 0x06
67 #define MT9V032_VERTICAL_BLANKING_MIN 4
68 #define MT9V034_VERTICAL_BLANKING_MIN 2
69 #define MT9V032_VERTICAL_BLANKING_DEF 45
70 #define MT9V032_VERTICAL_BLANKING_MAX 3000
71 #define MT9V034_VERTICAL_BLANKING_MAX 32288
72 #define MT9V032_CHIP_CONTROL 0x07
73 #define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
74 #define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
75 #define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
76 #define MT9V032_SHUTTER_WIDTH1 0x08
77 #define MT9V032_SHUTTER_WIDTH2 0x09
78 #define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
79 #define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
80 #define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
81 #define MT9V034_TOTAL_SHUTTER_WIDTH_MIN 0
82 #define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
83 #define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
84 #define MT9V034_TOTAL_SHUTTER_WIDTH_MAX 32765
85 #define MT9V032_RESET 0x0c
86 #define MT9V032_READ_MODE 0x0d
87 #define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
88 #define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
89 #define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
90 #define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
91 #define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
92 #define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
93 #define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
94 #define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
95 #define MT9V032_READ_MODE_RESERVED 0x0300
96 #define MT9V032_PIXEL_OPERATION_MODE 0x0f
97 #define MT9V034_PIXEL_OPERATION_MODE_HDR (1 << 0)
98 #define MT9V034_PIXEL_OPERATION_MODE_COLOR (1 << 1)
99 #define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
100 #define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
101 #define MT9V032_ANALOG_GAIN 0x35
102 #define MT9V032_ANALOG_GAIN_MIN 16
103 #define MT9V032_ANALOG_GAIN_DEF 16
104 #define MT9V032_ANALOG_GAIN_MAX 64
105 #define MT9V032_MAX_ANALOG_GAIN 0x36
106 #define MT9V032_MAX_ANALOG_GAIN_MAX 127
107 #define MT9V032_FRAME_DARK_AVERAGE 0x42
108 #define MT9V032_DARK_AVG_THRESH 0x46
109 #define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
110 #define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
111 #define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
112 #define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
113 #define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
114 #define MT9V034_ROW_NOISE_CORR_ENABLE (1 << 0)
115 #define MT9V034_ROW_NOISE_CORR_USE_BLK_AVG (1 << 1)
116 #define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
117 #define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
118 #define MT9V032_PIXEL_CLOCK 0x74
119 #define MT9V034_PIXEL_CLOCK 0x72
120 #define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
121 #define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
122 #define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
123 #define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
124 #define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
125 #define MT9V032_TEST_PATTERN 0x7f
126 #define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
127 #define MT9V032_TEST_PATTERN_DATA_SHIFT 0
128 #define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
129 #define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
130 #define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
131 #define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
132 #define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
133 #define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
134 #define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
135 #define MT9V032_TEST_PATTERN_FLIP (1 << 14)
136 #define MT9V032_AEGC_DESIRED_BIN 0xa5
137 #define MT9V032_AEC_UPDATE_FREQUENCY 0xa6
138 #define MT9V032_AEC_LPF 0xa8
139 #define MT9V032_AGC_UPDATE_FREQUENCY 0xa9
140 #define MT9V032_AGC_LPF 0xaa
141 #define MT9V032_AEC_AGC_ENABLE 0xaf
142 #define MT9V032_AEC_ENABLE (1 << 0)
143 #define MT9V032_AGC_ENABLE (1 << 1)
144 #define MT9V034_AEC_MAX_SHUTTER_WIDTH 0xad
145 #define MT9V032_AEC_MAX_SHUTTER_WIDTH 0xbd
146 #define MT9V032_THERMAL_INFO 0xc1
147
148 enum mt9v032_model {
149 MT9V032_MODEL_V022_COLOR, /* MT9V022IX7ATC */
150 MT9V032_MODEL_V022_MONO, /* MT9V022IX7ATM */
151 MT9V032_MODEL_V024_COLOR, /* MT9V024IA7XTC */
152 MT9V032_MODEL_V024_MONO, /* MT9V024IA7XTM */
153 MT9V032_MODEL_V032_COLOR, /* MT9V032C12STM */
154 MT9V032_MODEL_V032_MONO, /* MT9V032C12STC */
155 MT9V032_MODEL_V034_COLOR,
156 MT9V032_MODEL_V034_MONO,
157 };
158
159 struct mt9v032_model_version {
160 unsigned int version;
161 const char *name;
162 };
163
164 struct mt9v032_model_data {
165 unsigned int min_row_time;
166 unsigned int min_hblank;
167 unsigned int min_vblank;
168 unsigned int max_vblank;
169 unsigned int min_shutter;
170 unsigned int max_shutter;
171 unsigned int pclk_reg;
172 unsigned int aec_max_shutter_reg;
173 const struct v4l2_ctrl_config * const aec_max_shutter_v4l2_ctrl;
174 };
175
176 struct mt9v032_model_info {
177 const struct mt9v032_model_data *data;
178 bool color;
179 };
180
181 static const struct mt9v032_model_version mt9v032_versions[] = {
182 { MT9V032_CHIP_ID_REV1, "MT9V022/MT9V032 rev1/2" },
183 { MT9V032_CHIP_ID_REV3, "MT9V022/MT9V032 rev3" },
184 { MT9V034_CHIP_ID_REV1, "MT9V024/MT9V034 rev1" },
185 };
186
187 struct mt9v032 {
188 struct v4l2_subdev subdev;
189 struct media_pad pad;
190
191 struct v4l2_mbus_framefmt format;
192 struct v4l2_rect crop;
193 unsigned int hratio;
194 unsigned int vratio;
195
196 struct v4l2_ctrl_handler ctrls;
197 struct {
198 struct v4l2_ctrl *link_freq;
199 struct v4l2_ctrl *pixel_rate;
200 };
201
202 struct mutex power_lock;
203 int power_count;
204
205 struct regmap *regmap;
206 struct clk *clk;
207 struct gpio_desc *reset_gpio;
208 struct gpio_desc *standby_gpio;
209
210 struct mt9v032_platform_data *pdata;
211 const struct mt9v032_model_info *model;
212 const struct mt9v032_model_version *version;
213
214 u32 sysclk;
215 u16 aec_agc;
216 u16 hblank;
217 struct {
218 struct v4l2_ctrl *test_pattern;
219 struct v4l2_ctrl *test_pattern_color;
220 };
221 };
222
223 static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
224 {
225 return container_of(sd, struct mt9v032, subdev);
226 }
227
228 static int
229 mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
230 {
231 struct regmap *map = mt9v032->regmap;
232 u16 value = mt9v032->aec_agc;
233 int ret;
234
235 if (enable)
236 value |= which;
237 else
238 value &= ~which;
239
240 ret = regmap_write(map, MT9V032_AEC_AGC_ENABLE, value);
241 if (ret < 0)
242 return ret;
243
244 mt9v032->aec_agc = value;
245 return 0;
246 }
247
248 static int
249 mt9v032_update_hblank(struct mt9v032 *mt9v032)
250 {
251 struct v4l2_rect *crop = &mt9v032->crop;
252 unsigned int min_hblank = mt9v032->model->data->min_hblank;
253 unsigned int hblank;
254
255 if (mt9v032->version->version == MT9V034_CHIP_ID_REV1)
256 min_hblank += (mt9v032->hratio - 1) * 10;
257 min_hblank = max_t(int, mt9v032->model->data->min_row_time - crop->width,
258 min_hblank);
259 hblank = max_t(unsigned int, mt9v032->hblank, min_hblank);
260
261 return regmap_write(mt9v032->regmap, MT9V032_HORIZONTAL_BLANKING,
262 hblank);
263 }
264
265 static int mt9v032_power_on(struct mt9v032 *mt9v032)
266 {
267 struct regmap *map = mt9v032->regmap;
268 int ret;
269
270 gpiod_set_value_cansleep(mt9v032->reset_gpio, 1);
271
272 ret = clk_set_rate(mt9v032->clk, mt9v032->sysclk);
273 if (ret < 0)
274 return ret;
275
276 /* System clock has to be enabled before releasing the reset */
277 ret = clk_prepare_enable(mt9v032->clk);
278 if (ret)
279 return ret;
280
281 udelay(1);
282
283 if (mt9v032->reset_gpio) {
284 gpiod_set_value_cansleep(mt9v032->reset_gpio, 0);
285
286 /* After releasing reset we need to wait 10 clock cycles
287 * before accessing the sensor over I2C. As the minimum SYSCLK
288 * frequency is 13MHz, waiting 1µs will be enough in the worst
289 * case.
290 */
291 udelay(1);
292 }
293
294 /* Reset the chip and stop data read out */
295 ret = regmap_write(map, MT9V032_RESET, 1);
296 if (ret < 0)
297 goto err;
298
299 ret = regmap_write(map, MT9V032_RESET, 0);
300 if (ret < 0)
301 goto err;
302
303 ret = regmap_write(map, MT9V032_CHIP_CONTROL,
304 MT9V032_CHIP_CONTROL_MASTER_MODE);
305 if (ret < 0)
306 goto err;
307
308 return 0;
309
310 err:
311 clk_disable_unprepare(mt9v032->clk);
312 return ret;
313 }
314
315 static void mt9v032_power_off(struct mt9v032 *mt9v032)
316 {
317 clk_disable_unprepare(mt9v032->clk);
318 }
319
320 static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
321 {
322 struct regmap *map = mt9v032->regmap;
323 int ret;
324
325 if (!on) {
326 mt9v032_power_off(mt9v032);
327 return 0;
328 }
329
330 ret = mt9v032_power_on(mt9v032);
331 if (ret < 0)
332 return ret;
333
334 /* Configure the pixel clock polarity */
335 if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
336 ret = regmap_write(map, mt9v032->model->data->pclk_reg,
337 MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
338 if (ret < 0)
339 return ret;
340 }
341
342 /* Disable the noise correction algorithm and restore the controls. */
343 ret = regmap_write(map, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
344 if (ret < 0)
345 return ret;
346
347 return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
348 }
349
350 /* -----------------------------------------------------------------------------
351 * V4L2 subdev video operations
352 */
353
354 static struct v4l2_mbus_framefmt *
355 __mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
356 unsigned int pad, enum v4l2_subdev_format_whence which)
357 {
358 switch (which) {
359 case V4L2_SUBDEV_FORMAT_TRY:
360 return v4l2_subdev_get_try_format(&mt9v032->subdev, cfg, pad);
361 case V4L2_SUBDEV_FORMAT_ACTIVE:
362 return &mt9v032->format;
363 default:
364 return NULL;
365 }
366 }
367
368 static struct v4l2_rect *
369 __mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_pad_config *cfg,
370 unsigned int pad, enum v4l2_subdev_format_whence which)
371 {
372 switch (which) {
373 case V4L2_SUBDEV_FORMAT_TRY:
374 return v4l2_subdev_get_try_crop(&mt9v032->subdev, cfg, pad);
375 case V4L2_SUBDEV_FORMAT_ACTIVE:
376 return &mt9v032->crop;
377 default:
378 return NULL;
379 }
380 }
381
382 static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
383 {
384 const u16 mode = MT9V032_CHIP_CONTROL_DOUT_ENABLE
385 | MT9V032_CHIP_CONTROL_SEQUENTIAL;
386 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
387 struct v4l2_rect *crop = &mt9v032->crop;
388 struct regmap *map = mt9v032->regmap;
389 unsigned int hbin;
390 unsigned int vbin;
391 int ret;
392
393 if (!enable)
394 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, 0);
395
396 /* Configure the window size and row/column bin */
397 hbin = fls(mt9v032->hratio) - 1;
398 vbin = fls(mt9v032->vratio) - 1;
399 ret = regmap_update_bits(map, MT9V032_READ_MODE,
400 ~MT9V032_READ_MODE_RESERVED,
401 hbin << MT9V032_READ_MODE_COLUMN_BIN_SHIFT |
402 vbin << MT9V032_READ_MODE_ROW_BIN_SHIFT);
403 if (ret < 0)
404 return ret;
405
406 ret = regmap_write(map, MT9V032_COLUMN_START, crop->left);
407 if (ret < 0)
408 return ret;
409
410 ret = regmap_write(map, MT9V032_ROW_START, crop->top);
411 if (ret < 0)
412 return ret;
413
414 ret = regmap_write(map, MT9V032_WINDOW_WIDTH, crop->width);
415 if (ret < 0)
416 return ret;
417
418 ret = regmap_write(map, MT9V032_WINDOW_HEIGHT, crop->height);
419 if (ret < 0)
420 return ret;
421
422 ret = mt9v032_update_hblank(mt9v032);
423 if (ret < 0)
424 return ret;
425
426 /* Switch to master "normal" mode */
427 return regmap_update_bits(map, MT9V032_CHIP_CONTROL, mode, mode);
428 }
429
430 static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
431 struct v4l2_subdev_pad_config *cfg,
432 struct v4l2_subdev_mbus_code_enum *code)
433 {
434 if (code->index > 0)
435 return -EINVAL;
436
437 code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
438 return 0;
439 }
440
441 static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
442 struct v4l2_subdev_pad_config *cfg,
443 struct v4l2_subdev_frame_size_enum *fse)
444 {
445 if (fse->index >= 3 || fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
446 return -EINVAL;
447
448 fse->min_width = MT9V032_WINDOW_WIDTH_DEF / (1 << fse->index);
449 fse->max_width = fse->min_width;
450 fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / (1 << fse->index);
451 fse->max_height = fse->min_height;
452
453 return 0;
454 }
455
456 static int mt9v032_get_format(struct v4l2_subdev *subdev,
457 struct v4l2_subdev_pad_config *cfg,
458 struct v4l2_subdev_format *format)
459 {
460 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
461
462 format->format = *__mt9v032_get_pad_format(mt9v032, cfg, format->pad,
463 format->which);
464 return 0;
465 }
466
467 static void mt9v032_configure_pixel_rate(struct mt9v032 *mt9v032)
468 {
469 struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
470 int ret;
471
472 ret = v4l2_ctrl_s_ctrl_int64(mt9v032->pixel_rate,
473 mt9v032->sysclk / mt9v032->hratio);
474 if (ret < 0)
475 dev_warn(&client->dev, "failed to set pixel rate (%d)\n", ret);
476 }
477
478 static unsigned int mt9v032_calc_ratio(unsigned int input, unsigned int output)
479 {
480 /* Compute the power-of-two binning factor closest to the input size to
481 * output size ratio. Given that the output size is bounded by input/4
482 * and input, a generic implementation would be an ineffective luxury.
483 */
484 if (output * 3 > input * 2)
485 return 1;
486 if (output * 3 > input)
487 return 2;
488 return 4;
489 }
490
491 static int mt9v032_set_format(struct v4l2_subdev *subdev,
492 struct v4l2_subdev_pad_config *cfg,
493 struct v4l2_subdev_format *format)
494 {
495 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
496 struct v4l2_mbus_framefmt *__format;
497 struct v4l2_rect *__crop;
498 unsigned int width;
499 unsigned int height;
500 unsigned int hratio;
501 unsigned int vratio;
502
503 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, format->pad,
504 format->which);
505
506 /* Clamp the width and height to avoid dividing by zero. */
507 width = clamp(ALIGN(format->format.width, 2),
508 max_t(unsigned int, __crop->width / 4,
509 MT9V032_WINDOW_WIDTH_MIN),
510 __crop->width);
511 height = clamp(ALIGN(format->format.height, 2),
512 max_t(unsigned int, __crop->height / 4,
513 MT9V032_WINDOW_HEIGHT_MIN),
514 __crop->height);
515
516 hratio = mt9v032_calc_ratio(__crop->width, width);
517 vratio = mt9v032_calc_ratio(__crop->height, height);
518
519 __format = __mt9v032_get_pad_format(mt9v032, cfg, format->pad,
520 format->which);
521 __format->width = __crop->width / hratio;
522 __format->height = __crop->height / vratio;
523
524 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
525 mt9v032->hratio = hratio;
526 mt9v032->vratio = vratio;
527 mt9v032_configure_pixel_rate(mt9v032);
528 }
529
530 format->format = *__format;
531
532 return 0;
533 }
534
535 static int mt9v032_get_selection(struct v4l2_subdev *subdev,
536 struct v4l2_subdev_pad_config *cfg,
537 struct v4l2_subdev_selection *sel)
538 {
539 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
540
541 if (sel->target != V4L2_SEL_TGT_CROP)
542 return -EINVAL;
543
544 sel->r = *__mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
545 return 0;
546 }
547
548 static int mt9v032_set_selection(struct v4l2_subdev *subdev,
549 struct v4l2_subdev_pad_config *cfg,
550 struct v4l2_subdev_selection *sel)
551 {
552 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
553 struct v4l2_mbus_framefmt *__format;
554 struct v4l2_rect *__crop;
555 struct v4l2_rect rect;
556
557 if (sel->target != V4L2_SEL_TGT_CROP)
558 return -EINVAL;
559
560 /* Clamp the crop rectangle boundaries and align them to a non multiple
561 * of 2 pixels to ensure a GRBG Bayer pattern.
562 */
563 rect.left = clamp(ALIGN(sel->r.left + 1, 2) - 1,
564 MT9V032_COLUMN_START_MIN,
565 MT9V032_COLUMN_START_MAX);
566 rect.top = clamp(ALIGN(sel->r.top + 1, 2) - 1,
567 MT9V032_ROW_START_MIN,
568 MT9V032_ROW_START_MAX);
569 rect.width = clamp_t(unsigned int, ALIGN(sel->r.width, 2),
570 MT9V032_WINDOW_WIDTH_MIN,
571 MT9V032_WINDOW_WIDTH_MAX);
572 rect.height = clamp_t(unsigned int, ALIGN(sel->r.height, 2),
573 MT9V032_WINDOW_HEIGHT_MIN,
574 MT9V032_WINDOW_HEIGHT_MAX);
575
576 rect.width = min_t(unsigned int,
577 rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
578 rect.height = min_t(unsigned int,
579 rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
580
581 __crop = __mt9v032_get_pad_crop(mt9v032, cfg, sel->pad, sel->which);
582
583 if (rect.width != __crop->width || rect.height != __crop->height) {
584 /* Reset the output image size if the crop rectangle size has
585 * been modified.
586 */
587 __format = __mt9v032_get_pad_format(mt9v032, cfg, sel->pad,
588 sel->which);
589 __format->width = rect.width;
590 __format->height = rect.height;
591 if (sel->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
592 mt9v032->hratio = 1;
593 mt9v032->vratio = 1;
594 mt9v032_configure_pixel_rate(mt9v032);
595 }
596 }
597
598 *__crop = rect;
599 sel->r = rect;
600
601 return 0;
602 }
603
604 /* -----------------------------------------------------------------------------
605 * V4L2 subdev control operations
606 */
607
608 #define V4L2_CID_TEST_PATTERN_COLOR (V4L2_CID_USER_BASE | 0x1001)
609 /*
610 * Value between 1 and 64 to set the desired bin. This is effectively a measure
611 * of how bright the image is supposed to be. Both AGC and AEC try to reach
612 * this.
613 */
614 #define V4L2_CID_AEGC_DESIRED_BIN (V4L2_CID_USER_BASE | 0x1002)
615 /*
616 * LPF is the low pass filter capability of the chip. Both AEC and AGC have
617 * this setting. This limits the speed in which AGC/AEC adjust their settings.
618 * Possible values are 0-2. 0 means no LPF. For 1 and 2 this equation is used:
619 *
620 * if |(calculated new exp - current exp)| > (current exp / 4)
621 * next exp = calculated new exp
622 * else
623 * next exp = current exp + ((calculated new exp - current exp) / 2^LPF)
624 */
625 #define V4L2_CID_AEC_LPF (V4L2_CID_USER_BASE | 0x1003)
626 #define V4L2_CID_AGC_LPF (V4L2_CID_USER_BASE | 0x1004)
627 /*
628 * Value between 0 and 15. This is the number of frames being skipped before
629 * updating the auto exposure/gain.
630 */
631 #define V4L2_CID_AEC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1005)
632 #define V4L2_CID_AGC_UPDATE_INTERVAL (V4L2_CID_USER_BASE | 0x1006)
633 /*
634 * Maximum shutter width used for AEC.
635 */
636 #define V4L2_CID_AEC_MAX_SHUTTER_WIDTH (V4L2_CID_USER_BASE | 0x1007)
637
638 static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
639 {
640 struct mt9v032 *mt9v032 =
641 container_of(ctrl->handler, struct mt9v032, ctrls);
642 struct regmap *map = mt9v032->regmap;
643 u32 freq;
644 u16 data;
645
646 switch (ctrl->id) {
647 case V4L2_CID_AUTOGAIN:
648 return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
649 ctrl->val);
650
651 case V4L2_CID_GAIN:
652 return regmap_write(map, MT9V032_ANALOG_GAIN, ctrl->val);
653
654 case V4L2_CID_EXPOSURE_AUTO:
655 return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
656 !ctrl->val);
657
658 case V4L2_CID_EXPOSURE:
659 return regmap_write(map, MT9V032_TOTAL_SHUTTER_WIDTH,
660 ctrl->val);
661
662 case V4L2_CID_HBLANK:
663 mt9v032->hblank = ctrl->val;
664 return mt9v032_update_hblank(mt9v032);
665
666 case V4L2_CID_VBLANK:
667 return regmap_write(map, MT9V032_VERTICAL_BLANKING,
668 ctrl->val);
669
670 case V4L2_CID_PIXEL_RATE:
671 case V4L2_CID_LINK_FREQ:
672 if (mt9v032->link_freq == NULL)
673 break;
674
675 freq = mt9v032->pdata->link_freqs[mt9v032->link_freq->val];
676 *mt9v032->pixel_rate->p_new.p_s64 = freq;
677 mt9v032->sysclk = freq;
678 break;
679
680 case V4L2_CID_TEST_PATTERN:
681 switch (mt9v032->test_pattern->val) {
682 case 0:
683 data = 0;
684 break;
685 case 1:
686 data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
687 | MT9V032_TEST_PATTERN_ENABLE;
688 break;
689 case 2:
690 data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
691 | MT9V032_TEST_PATTERN_ENABLE;
692 break;
693 case 3:
694 data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
695 | MT9V032_TEST_PATTERN_ENABLE;
696 break;
697 default:
698 data = (mt9v032->test_pattern_color->val <<
699 MT9V032_TEST_PATTERN_DATA_SHIFT)
700 | MT9V032_TEST_PATTERN_USE_DATA
701 | MT9V032_TEST_PATTERN_ENABLE
702 | MT9V032_TEST_PATTERN_FLIP;
703 break;
704 }
705 return regmap_write(map, MT9V032_TEST_PATTERN, data);
706
707 case V4L2_CID_AEGC_DESIRED_BIN:
708 return regmap_write(map, MT9V032_AEGC_DESIRED_BIN, ctrl->val);
709
710 case V4L2_CID_AEC_LPF:
711 return regmap_write(map, MT9V032_AEC_LPF, ctrl->val);
712
713 case V4L2_CID_AGC_LPF:
714 return regmap_write(map, MT9V032_AGC_LPF, ctrl->val);
715
716 case V4L2_CID_AEC_UPDATE_INTERVAL:
717 return regmap_write(map, MT9V032_AEC_UPDATE_FREQUENCY,
718 ctrl->val);
719
720 case V4L2_CID_AGC_UPDATE_INTERVAL:
721 return regmap_write(map, MT9V032_AGC_UPDATE_FREQUENCY,
722 ctrl->val);
723
724 case V4L2_CID_AEC_MAX_SHUTTER_WIDTH:
725 return regmap_write(map,
726 mt9v032->model->data->aec_max_shutter_reg,
727 ctrl->val);
728 }
729
730 return 0;
731 }
732
733 static const struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
734 .s_ctrl = mt9v032_s_ctrl,
735 };
736
737 static const char * const mt9v032_test_pattern_menu[] = {
738 "Disabled",
739 "Gray Vertical Shade",
740 "Gray Horizontal Shade",
741 "Gray Diagonal Shade",
742 "Plain",
743 };
744
745 static const struct v4l2_ctrl_config mt9v032_test_pattern_color = {
746 .ops = &mt9v032_ctrl_ops,
747 .id = V4L2_CID_TEST_PATTERN_COLOR,
748 .type = V4L2_CTRL_TYPE_INTEGER,
749 .name = "Test Pattern Color",
750 .min = 0,
751 .max = 1023,
752 .step = 1,
753 .def = 0,
754 .flags = 0,
755 };
756
757 static const struct v4l2_ctrl_config mt9v032_aegc_controls[] = {
758 {
759 .ops = &mt9v032_ctrl_ops,
760 .id = V4L2_CID_AEGC_DESIRED_BIN,
761 .type = V4L2_CTRL_TYPE_INTEGER,
762 .name = "AEC/AGC Desired Bin",
763 .min = 1,
764 .max = 64,
765 .step = 1,
766 .def = 58,
767 .flags = 0,
768 }, {
769 .ops = &mt9v032_ctrl_ops,
770 .id = V4L2_CID_AEC_LPF,
771 .type = V4L2_CTRL_TYPE_INTEGER,
772 .name = "AEC Low Pass Filter",
773 .min = 0,
774 .max = 2,
775 .step = 1,
776 .def = 0,
777 .flags = 0,
778 }, {
779 .ops = &mt9v032_ctrl_ops,
780 .id = V4L2_CID_AGC_LPF,
781 .type = V4L2_CTRL_TYPE_INTEGER,
782 .name = "AGC Low Pass Filter",
783 .min = 0,
784 .max = 2,
785 .step = 1,
786 .def = 2,
787 .flags = 0,
788 }, {
789 .ops = &mt9v032_ctrl_ops,
790 .id = V4L2_CID_AEC_UPDATE_INTERVAL,
791 .type = V4L2_CTRL_TYPE_INTEGER,
792 .name = "AEC Update Interval",
793 .min = 0,
794 .max = 16,
795 .step = 1,
796 .def = 2,
797 .flags = 0,
798 }, {
799 .ops = &mt9v032_ctrl_ops,
800 .id = V4L2_CID_AGC_UPDATE_INTERVAL,
801 .type = V4L2_CTRL_TYPE_INTEGER,
802 .name = "AGC Update Interval",
803 .min = 0,
804 .max = 16,
805 .step = 1,
806 .def = 2,
807 .flags = 0,
808 }
809 };
810
811 static const struct v4l2_ctrl_config mt9v032_aec_max_shutter_width = {
812 .ops = &mt9v032_ctrl_ops,
813 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
814 .type = V4L2_CTRL_TYPE_INTEGER,
815 .name = "AEC Max Shutter Width",
816 .min = 1,
817 .max = 2047,
818 .step = 1,
819 .def = 480,
820 .flags = 0,
821 };
822
823 static const struct v4l2_ctrl_config mt9v034_aec_max_shutter_width = {
824 .ops = &mt9v032_ctrl_ops,
825 .id = V4L2_CID_AEC_MAX_SHUTTER_WIDTH,
826 .type = V4L2_CTRL_TYPE_INTEGER,
827 .name = "AEC Max Shutter Width",
828 .min = 1,
829 .max = 32765,
830 .step = 1,
831 .def = 480,
832 .flags = 0,
833 };
834
835 /* -----------------------------------------------------------------------------
836 * V4L2 subdev core operations
837 */
838
839 static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
840 {
841 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
842 int ret = 0;
843
844 mutex_lock(&mt9v032->power_lock);
845
846 /* If the power count is modified from 0 to != 0 or from != 0 to 0,
847 * update the power state.
848 */
849 if (mt9v032->power_count == !on) {
850 ret = __mt9v032_set_power(mt9v032, !!on);
851 if (ret < 0)
852 goto done;
853 }
854
855 /* Update the power count. */
856 mt9v032->power_count += on ? 1 : -1;
857 WARN_ON(mt9v032->power_count < 0);
858
859 done:
860 mutex_unlock(&mt9v032->power_lock);
861 return ret;
862 }
863
864 /* -----------------------------------------------------------------------------
865 * V4L2 subdev internal operations
866 */
867
868 static int mt9v032_registered(struct v4l2_subdev *subdev)
869 {
870 struct i2c_client *client = v4l2_get_subdevdata(subdev);
871 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
872 unsigned int i;
873 u32 version;
874 int ret;
875
876 dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
877 client->addr);
878
879 ret = mt9v032_power_on(mt9v032);
880 if (ret < 0) {
881 dev_err(&client->dev, "MT9V032 power up failed\n");
882 return ret;
883 }
884
885 /* Read and check the sensor version */
886 ret = regmap_read(mt9v032->regmap, MT9V032_CHIP_VERSION, &version);
887
888 mt9v032_power_off(mt9v032);
889
890 if (ret < 0) {
891 dev_err(&client->dev, "Failed reading chip version\n");
892 return ret;
893 }
894
895 for (i = 0; i < ARRAY_SIZE(mt9v032_versions); ++i) {
896 if (mt9v032_versions[i].version == version) {
897 mt9v032->version = &mt9v032_versions[i];
898 break;
899 }
900 }
901
902 if (mt9v032->version == NULL) {
903 dev_err(&client->dev, "Unsupported chip version 0x%04x\n",
904 version);
905 return -ENODEV;
906 }
907
908 dev_info(&client->dev, "%s detected at address 0x%02x\n",
909 mt9v032->version->name, client->addr);
910
911 mt9v032_configure_pixel_rate(mt9v032);
912
913 return ret;
914 }
915
916 static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
917 {
918 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
919 struct v4l2_mbus_framefmt *format;
920 struct v4l2_rect *crop;
921
922 crop = v4l2_subdev_get_try_crop(subdev, fh->pad, 0);
923 crop->left = MT9V032_COLUMN_START_DEF;
924 crop->top = MT9V032_ROW_START_DEF;
925 crop->width = MT9V032_WINDOW_WIDTH_DEF;
926 crop->height = MT9V032_WINDOW_HEIGHT_DEF;
927
928 format = v4l2_subdev_get_try_format(subdev, fh->pad, 0);
929
930 if (mt9v032->model->color)
931 format->code = MEDIA_BUS_FMT_SGRBG10_1X10;
932 else
933 format->code = MEDIA_BUS_FMT_Y10_1X10;
934
935 format->width = MT9V032_WINDOW_WIDTH_DEF;
936 format->height = MT9V032_WINDOW_HEIGHT_DEF;
937 format->field = V4L2_FIELD_NONE;
938 format->colorspace = V4L2_COLORSPACE_SRGB;
939
940 return mt9v032_set_power(subdev, 1);
941 }
942
943 static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
944 {
945 return mt9v032_set_power(subdev, 0);
946 }
947
948 static const struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
949 .s_power = mt9v032_set_power,
950 };
951
952 static const struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
953 .s_stream = mt9v032_s_stream,
954 };
955
956 static const struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
957 .enum_mbus_code = mt9v032_enum_mbus_code,
958 .enum_frame_size = mt9v032_enum_frame_size,
959 .get_fmt = mt9v032_get_format,
960 .set_fmt = mt9v032_set_format,
961 .get_selection = mt9v032_get_selection,
962 .set_selection = mt9v032_set_selection,
963 };
964
965 static const struct v4l2_subdev_ops mt9v032_subdev_ops = {
966 .core = &mt9v032_subdev_core_ops,
967 .video = &mt9v032_subdev_video_ops,
968 .pad = &mt9v032_subdev_pad_ops,
969 };
970
971 static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
972 .registered = mt9v032_registered,
973 .open = mt9v032_open,
974 .close = mt9v032_close,
975 };
976
977 static const struct regmap_config mt9v032_regmap_config = {
978 .reg_bits = 8,
979 .val_bits = 16,
980 .max_register = 0xff,
981 .cache_type = REGCACHE_RBTREE,
982 };
983
984 /* -----------------------------------------------------------------------------
985 * Driver initialization and probing
986 */
987
988 static struct mt9v032_platform_data *
989 mt9v032_get_pdata(struct i2c_client *client)
990 {
991 struct mt9v032_platform_data *pdata = NULL;
992 struct v4l2_fwnode_endpoint endpoint;
993 struct device_node *np;
994 struct property *prop;
995
996 if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
997 return client->dev.platform_data;
998
999 np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
1000 if (!np)
1001 return NULL;
1002
1003 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0)
1004 goto done;
1005
1006 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1007 if (!pdata)
1008 goto done;
1009
1010 prop = of_find_property(np, "link-frequencies", NULL);
1011 if (prop) {
1012 u64 *link_freqs;
1013 size_t size = prop->length / sizeof(*link_freqs);
1014
1015 link_freqs = devm_kcalloc(&client->dev, size,
1016 sizeof(*link_freqs), GFP_KERNEL);
1017 if (!link_freqs)
1018 goto done;
1019
1020 if (of_property_read_u64_array(np, "link-frequencies",
1021 link_freqs, size) < 0)
1022 goto done;
1023
1024 pdata->link_freqs = link_freqs;
1025 pdata->link_def_freq = link_freqs[0];
1026 }
1027
1028 pdata->clk_pol = !!(endpoint.bus.parallel.flags &
1029 V4L2_MBUS_PCLK_SAMPLE_RISING);
1030
1031 done:
1032 of_node_put(np);
1033 return pdata;
1034 }
1035
1036 static int mt9v032_probe(struct i2c_client *client,
1037 const struct i2c_device_id *did)
1038 {
1039 struct mt9v032_platform_data *pdata = mt9v032_get_pdata(client);
1040 struct mt9v032 *mt9v032;
1041 unsigned int i;
1042 int ret;
1043
1044 mt9v032 = devm_kzalloc(&client->dev, sizeof(*mt9v032), GFP_KERNEL);
1045 if (!mt9v032)
1046 return -ENOMEM;
1047
1048 mt9v032->regmap = devm_regmap_init_i2c(client, &mt9v032_regmap_config);
1049 if (IS_ERR(mt9v032->regmap))
1050 return PTR_ERR(mt9v032->regmap);
1051
1052 mt9v032->clk = devm_clk_get(&client->dev, NULL);
1053 if (IS_ERR(mt9v032->clk))
1054 return PTR_ERR(mt9v032->clk);
1055
1056 mt9v032->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
1057 GPIOD_OUT_HIGH);
1058 if (IS_ERR(mt9v032->reset_gpio))
1059 return PTR_ERR(mt9v032->reset_gpio);
1060
1061 mt9v032->standby_gpio = devm_gpiod_get_optional(&client->dev, "standby",
1062 GPIOD_OUT_LOW);
1063 if (IS_ERR(mt9v032->standby_gpio))
1064 return PTR_ERR(mt9v032->standby_gpio);
1065
1066 mutex_init(&mt9v032->power_lock);
1067 mt9v032->pdata = pdata;
1068 mt9v032->model = (const void *)did->driver_data;
1069
1070 v4l2_ctrl_handler_init(&mt9v032->ctrls, 11 +
1071 ARRAY_SIZE(mt9v032_aegc_controls));
1072
1073 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1074 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1075 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1076 V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
1077 MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
1078 v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1079 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1080 V4L2_EXPOSURE_AUTO);
1081 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1082 V4L2_CID_EXPOSURE, mt9v032->model->data->min_shutter,
1083 mt9v032->model->data->max_shutter, 1,
1084 MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
1085 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1086 V4L2_CID_HBLANK, mt9v032->model->data->min_hblank,
1087 MT9V032_HORIZONTAL_BLANKING_MAX, 1,
1088 MT9V032_HORIZONTAL_BLANKING_DEF);
1089 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1090 V4L2_CID_VBLANK, mt9v032->model->data->min_vblank,
1091 mt9v032->model->data->max_vblank, 1,
1092 MT9V032_VERTICAL_BLANKING_DEF);
1093 mt9v032->test_pattern = v4l2_ctrl_new_std_menu_items(&mt9v032->ctrls,
1094 &mt9v032_ctrl_ops, V4L2_CID_TEST_PATTERN,
1095 ARRAY_SIZE(mt9v032_test_pattern_menu) - 1, 0, 0,
1096 mt9v032_test_pattern_menu);
1097 mt9v032->test_pattern_color = v4l2_ctrl_new_custom(&mt9v032->ctrls,
1098 &mt9v032_test_pattern_color, NULL);
1099
1100 v4l2_ctrl_new_custom(&mt9v032->ctrls,
1101 mt9v032->model->data->aec_max_shutter_v4l2_ctrl,
1102 NULL);
1103 for (i = 0; i < ARRAY_SIZE(mt9v032_aegc_controls); ++i)
1104 v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_aegc_controls[i],
1105 NULL);
1106
1107 v4l2_ctrl_cluster(2, &mt9v032->test_pattern);
1108
1109 mt9v032->pixel_rate =
1110 v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
1111 V4L2_CID_PIXEL_RATE, 1, INT_MAX, 1, 1);
1112
1113 if (pdata && pdata->link_freqs) {
1114 unsigned int def = 0;
1115
1116 for (i = 0; pdata->link_freqs[i]; ++i) {
1117 if (pdata->link_freqs[i] == pdata->link_def_freq)
1118 def = i;
1119 }
1120
1121 mt9v032->link_freq =
1122 v4l2_ctrl_new_int_menu(&mt9v032->ctrls,
1123 &mt9v032_ctrl_ops,
1124 V4L2_CID_LINK_FREQ, i - 1, def,
1125 pdata->link_freqs);
1126 v4l2_ctrl_cluster(2, &mt9v032->link_freq);
1127 }
1128
1129
1130 mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
1131
1132 if (mt9v032->ctrls.error) {
1133 dev_err(&client->dev, "control initialization error %d\n",
1134 mt9v032->ctrls.error);
1135 ret = mt9v032->ctrls.error;
1136 goto err;
1137 }
1138
1139 mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
1140 mt9v032->crop.top = MT9V032_ROW_START_DEF;
1141 mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
1142 mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
1143
1144 if (mt9v032->model->color)
1145 mt9v032->format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1146 else
1147 mt9v032->format.code = MEDIA_BUS_FMT_Y10_1X10;
1148
1149 mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
1150 mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
1151 mt9v032->format.field = V4L2_FIELD_NONE;
1152 mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
1153
1154 mt9v032->hratio = 1;
1155 mt9v032->vratio = 1;
1156
1157 mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
1158 mt9v032->hblank = MT9V032_HORIZONTAL_BLANKING_DEF;
1159 mt9v032->sysclk = MT9V032_SYSCLK_FREQ_DEF;
1160
1161 v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
1162 mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
1163 mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1164
1165 mt9v032->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1166 mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
1167 ret = media_entity_pads_init(&mt9v032->subdev.entity, 1, &mt9v032->pad);
1168 if (ret < 0)
1169 goto err;
1170
1171 mt9v032->subdev.dev = &client->dev;
1172 ret = v4l2_async_register_subdev(&mt9v032->subdev);
1173 if (ret < 0)
1174 goto err;
1175
1176 return 0;
1177
1178 err:
1179 media_entity_cleanup(&mt9v032->subdev.entity);
1180 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1181 return ret;
1182 }
1183
1184 static int mt9v032_remove(struct i2c_client *client)
1185 {
1186 struct v4l2_subdev *subdev = i2c_get_clientdata(client);
1187 struct mt9v032 *mt9v032 = to_mt9v032(subdev);
1188
1189 v4l2_async_unregister_subdev(subdev);
1190 v4l2_ctrl_handler_free(&mt9v032->ctrls);
1191 media_entity_cleanup(&subdev->entity);
1192
1193 return 0;
1194 }
1195
1196 static const struct mt9v032_model_data mt9v032_model_data[] = {
1197 {
1198 /* MT9V022, MT9V032 revisions 1/2/3 */
1199 .min_row_time = 660,
1200 .min_hblank = MT9V032_HORIZONTAL_BLANKING_MIN,
1201 .min_vblank = MT9V032_VERTICAL_BLANKING_MIN,
1202 .max_vblank = MT9V032_VERTICAL_BLANKING_MAX,
1203 .min_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
1204 .max_shutter = MT9V032_TOTAL_SHUTTER_WIDTH_MAX,
1205 .pclk_reg = MT9V032_PIXEL_CLOCK,
1206 .aec_max_shutter_reg = MT9V032_AEC_MAX_SHUTTER_WIDTH,
1207 .aec_max_shutter_v4l2_ctrl = &mt9v032_aec_max_shutter_width,
1208 }, {
1209 /* MT9V024, MT9V034 */
1210 .min_row_time = 690,
1211 .min_hblank = MT9V034_HORIZONTAL_BLANKING_MIN,
1212 .min_vblank = MT9V034_VERTICAL_BLANKING_MIN,
1213 .max_vblank = MT9V034_VERTICAL_BLANKING_MAX,
1214 .min_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MIN,
1215 .max_shutter = MT9V034_TOTAL_SHUTTER_WIDTH_MAX,
1216 .pclk_reg = MT9V034_PIXEL_CLOCK,
1217 .aec_max_shutter_reg = MT9V034_AEC_MAX_SHUTTER_WIDTH,
1218 .aec_max_shutter_v4l2_ctrl = &mt9v034_aec_max_shutter_width,
1219 },
1220 };
1221
1222 static const struct mt9v032_model_info mt9v032_models[] = {
1223 [MT9V032_MODEL_V022_COLOR] = {
1224 .data = &mt9v032_model_data[0],
1225 .color = true,
1226 },
1227 [MT9V032_MODEL_V022_MONO] = {
1228 .data = &mt9v032_model_data[0],
1229 .color = false,
1230 },
1231 [MT9V032_MODEL_V024_COLOR] = {
1232 .data = &mt9v032_model_data[1],
1233 .color = true,
1234 },
1235 [MT9V032_MODEL_V024_MONO] = {
1236 .data = &mt9v032_model_data[1],
1237 .color = false,
1238 },
1239 [MT9V032_MODEL_V032_COLOR] = {
1240 .data = &mt9v032_model_data[0],
1241 .color = true,
1242 },
1243 [MT9V032_MODEL_V032_MONO] = {
1244 .data = &mt9v032_model_data[0],
1245 .color = false,
1246 },
1247 [MT9V032_MODEL_V034_COLOR] = {
1248 .data = &mt9v032_model_data[1],
1249 .color = true,
1250 },
1251 [MT9V032_MODEL_V034_MONO] = {
1252 .data = &mt9v032_model_data[1],
1253 .color = false,
1254 },
1255 };
1256
1257 static const struct i2c_device_id mt9v032_id[] = {
1258 { "mt9v022", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_COLOR] },
1259 { "mt9v022m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V022_MONO] },
1260 { "mt9v024", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_COLOR] },
1261 { "mt9v024m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V024_MONO] },
1262 { "mt9v032", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_COLOR] },
1263 { "mt9v032m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V032_MONO] },
1264 { "mt9v034", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_COLOR] },
1265 { "mt9v034m", (kernel_ulong_t)&mt9v032_models[MT9V032_MODEL_V034_MONO] },
1266 { }
1267 };
1268 MODULE_DEVICE_TABLE(i2c, mt9v032_id);
1269
1270 #if IS_ENABLED(CONFIG_OF)
1271 static const struct of_device_id mt9v032_of_match[] = {
1272 { .compatible = "aptina,mt9v022" },
1273 { .compatible = "aptina,mt9v022m" },
1274 { .compatible = "aptina,mt9v024" },
1275 { .compatible = "aptina,mt9v024m" },
1276 { .compatible = "aptina,mt9v032" },
1277 { .compatible = "aptina,mt9v032m" },
1278 { .compatible = "aptina,mt9v034" },
1279 { .compatible = "aptina,mt9v034m" },
1280 { /* Sentinel */ }
1281 };
1282 MODULE_DEVICE_TABLE(of, mt9v032_of_match);
1283 #endif
1284
1285 static struct i2c_driver mt9v032_driver = {
1286 .driver = {
1287 .name = "mt9v032",
1288 .of_match_table = of_match_ptr(mt9v032_of_match),
1289 },
1290 .probe = mt9v032_probe,
1291 .remove = mt9v032_remove,
1292 .id_table = mt9v032_id,
1293 };
1294
1295 module_i2c_driver(mt9v032_driver);
1296
1297 MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
1298 MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
1299 MODULE_LICENSE("GPL");
Linux with added FPC-III support