drivers/media/pci/cx18/cx18-io.c

   1 /*
   2  *  cx18 driver PCI memory mapped IO access routines
   3  *
   4  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
   5  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; either version 2 of the License, or
  10  *  (at your option) any later version.
  11  *
  12  *  This program is distributed in the hope that it will be useful,
  13  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *  GNU General Public License for more details.
  16  */
  17
  18 #include "cx18-driver.h"
  19 #include "cx18-io.h"
  20 #include "cx18-irq.h"
  21
  22 void cx18_memset_io(struct cx18 *cx, void __iomem *addr, int val, size_t count)
  23 {
  24         u8 __iomem *dst = addr;
  25         u16 val2 = val | (val << 8);
  26         u32 val4 = val2 | (val2 << 16);
  27
  28         /* Align writes on the CX23418's addresses */
  29         if ((count > 0) && ((unsigned long)dst & 1)) {
  30                 cx18_writeb(cx, (u8) val, dst);
  31                 count--;
  32                 dst++;
  33         }
  34         if ((count > 1) && ((unsigned long)dst & 2)) {
  35                 cx18_writew(cx, val2, dst);
  36                 count -= 2;
  37                 dst += 2;
  38         }
  39         while (count > 3) {
  40                 cx18_writel(cx, val4, dst);
  41                 count -= 4;
  42                 dst += 4;
  43         }
  44         if (count > 1) {
  45                 cx18_writew(cx, val2, dst);
  46                 count -= 2;
  47                 dst += 2;
  48         }
  49         if (count > 0)
  50                 cx18_writeb(cx, (u8) val, dst);
  51 }
  52
  53 void cx18_sw1_irq_enable(struct cx18 *cx, u32 val)
  54 {
  55         cx18_write_reg_expect(cx, val, SW1_INT_STATUS, ~val, val);
  56         cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) | val;
  57         cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
  58 }
  59
  60 void cx18_sw1_irq_disable(struct cx18 *cx, u32 val)
  61 {
  62         cx->sw1_irq_mask = cx18_read_reg(cx, SW1_INT_ENABLE_PCI) & ~val;
  63         cx18_write_reg(cx, cx->sw1_irq_mask, SW1_INT_ENABLE_PCI);
  64 }
  65
  66 void cx18_sw2_irq_enable(struct cx18 *cx, u32 val)
  67 {
  68         cx18_write_reg_expect(cx, val, SW2_INT_STATUS, ~val, val);
  69         cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) | val;
  70         cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
  71 }
  72
  73 void cx18_sw2_irq_disable(struct cx18 *cx, u32 val)
  74 {
  75         cx->sw2_irq_mask = cx18_read_reg(cx, SW2_INT_ENABLE_PCI) & ~val;
  76         cx18_write_reg(cx, cx->sw2_irq_mask, SW2_INT_ENABLE_PCI);
  77 }
  78
  79 void cx18_sw2_irq_disable_cpu(struct cx18 *cx, u32 val)
  80 {
  81         u32 r;
  82         r = cx18_read_reg(cx, SW2_INT_ENABLE_CPU);
  83         cx18_write_reg(cx, r & ~val, SW2_INT_ENABLE_CPU);
  84 }
  85
  86 void cx18_setup_page(struct cx18 *cx, u32 addr)
  87 {
  88         u32 val;
  89         val = cx18_read_reg(cx, 0xD000F8);
  90         val = (val & ~0x1f00) | ((addr >> 17) & 0x1f00);
  91         cx18_write_reg(cx, val, 0xD000F8);
  92 }