| blob | 97d3ba1614d6033b52f089212c0ee82c3dc46dc8 |
1 /*
2 * Copyright (C) 2008-2009 Texas Instruments Inc
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14 #ifndef _ISIF_REGS_H
15 #define _ISIF_REGS_H
17 /* ISIF registers relative offsets */
18 #define SYNCEN 0x00
19 #define MODESET 0x04
20 #define HDW 0x08
21 #define VDW 0x0c
22 #define PPLN 0x10
23 #define LPFR 0x14
24 #define SPH 0x18
25 #define LNH 0x1c
26 #define SLV0 0x20
27 #define SLV1 0x24
28 #define LNV 0x28
29 #define CULH 0x2c
30 #define CULV 0x30
31 #define HSIZE 0x34
32 #define SDOFST 0x38
33 #define CADU 0x3c
34 #define CADL 0x40
35 #define LINCFG0 0x44
36 #define LINCFG1 0x48
37 #define CCOLP 0x4c
38 #define CRGAIN 0x50
39 #define CGRGAIN 0x54
40 #define CGBGAIN 0x58
41 #define CBGAIN 0x5c
42 #define COFSTA 0x60
43 #define FLSHCFG0 0x64
44 #define FLSHCFG1 0x68
45 #define FLSHCFG2 0x6c
46 #define VDINT0 0x70
47 #define VDINT1 0x74
48 #define VDINT2 0x78
49 #define MISC 0x7c
50 #define CGAMMAWD 0x80
51 #define REC656IF 0x84
52 #define CCDCFG 0x88
53 /*****************************************************
54 * Defect Correction registers
55 *****************************************************/
56 #define DFCCTL 0x8c
57 #define VDFSATLV 0x90
58 #define DFCMEMCTL 0x94
59 #define DFCMEM0 0x98
60 #define DFCMEM1 0x9c
61 #define DFCMEM2 0xa0
62 #define DFCMEM3 0xa4
63 #define DFCMEM4 0xa8
64 /****************************************************
65 * Black Clamp registers
66 ****************************************************/
67 #define CLAMPCFG 0xac
68 #define CLDCOFST 0xb0
69 #define CLSV 0xb4
70 #define CLHWIN0 0xb8
71 #define CLHWIN1 0xbc
72 #define CLHWIN2 0xc0
73 #define CLVRV 0xc4
74 #define CLVWIN0 0xc8
75 #define CLVWIN1 0xcc
76 #define CLVWIN2 0xd0
77 #define CLVWIN3 0xd4
78 /****************************************************
79 * Lense Shading Correction
80 ****************************************************/
81 #define DATAHOFST 0xd8
82 #define DATAVOFST 0xdc
83 #define LSCHVAL 0xe0
84 #define LSCVVAL 0xe4
85 #define TWODLSCCFG 0xe8
86 #define TWODLSCOFST 0xec
87 #define TWODLSCINI 0xf0
88 #define TWODLSCGRBU 0xf4
89 #define TWODLSCGRBL 0xf8
90 #define TWODLSCGROF 0xfc
91 #define TWODLSCORBU 0x100
92 #define TWODLSCORBL 0x104
93 #define TWODLSCOROF 0x108
94 #define TWODLSCIRQEN 0x10c
95 #define TWODLSCIRQST 0x110
96 /****************************************************
97 * Data formatter
98 ****************************************************/
99 #define FMTCFG 0x114
100 #define FMTPLEN 0x118
101 #define FMTSPH 0x11c
102 #define FMTLNH 0x120
103 #define FMTSLV 0x124
104 #define FMTLNV 0x128
105 #define FMTRLEN 0x12c
106 #define FMTHCNT 0x130
107 #define FMTAPTR_BASE 0x134
108 /* Below macro for addresses FMTAPTR0 - FMTAPTR15 */
109 #define FMTAPTR(i) (FMTAPTR_BASE + (i * 4))
110 #define FMTPGMVF0 0x174
111 #define FMTPGMVF1 0x178
112 #define FMTPGMAPU0 0x17c
113 #define FMTPGMAPU1 0x180
114 #define FMTPGMAPS0 0x184
115 #define FMTPGMAPS1 0x188
116 #define FMTPGMAPS2 0x18c
117 #define FMTPGMAPS3 0x190
118 #define FMTPGMAPS4 0x194
119 #define FMTPGMAPS5 0x198
120 #define FMTPGMAPS6 0x19c
121 #define FMTPGMAPS7 0x1a0
122 /************************************************
123 * Color Space Converter
124 ************************************************/
125 #define CSCCTL 0x1a4
126 #define CSCM0 0x1a8
127 #define CSCM1 0x1ac
128 #define CSCM2 0x1b0
129 #define CSCM3 0x1b4
130 #define CSCM4 0x1b8
131 #define CSCM5 0x1bc
132 #define CSCM6 0x1c0
133 #define CSCM7 0x1c4
134 #define OBWIN0 0x1c8
135 #define OBWIN1 0x1cc
136 #define OBWIN2 0x1d0
137 #define OBWIN3 0x1d4
138 #define OBVAL0 0x1d8
139 #define OBVAL1 0x1dc
140 #define OBVAL2 0x1e0
141 #define OBVAL3 0x1e4
142 #define OBVAL4 0x1e8
143 #define OBVAL5 0x1ec
144 #define OBVAL6 0x1f0
145 #define OBVAL7 0x1f4
146 #define CLKCTL 0x1f8
148 /* Masks & Shifts below */
149 #define START_PX_HOR_MASK 0x7FFF
150 #define NUM_PX_HOR_MASK 0x7FFF
151 #define START_VER_ONE_MASK 0x7FFF
152 #define START_VER_TWO_MASK 0x7FFF
153 #define NUM_LINES_VER 0x7FFF
155 /* gain - offset masks */
156 #define GAIN_INTEGER_SHIFT 9
157 #define OFFSET_MASK 0xFFF
158 #define GAIN_SDRAM_EN_SHIFT 12
159 #define GAIN_IPIPE_EN_SHIFT 13
160 #define GAIN_H3A_EN_SHIFT 14
161 #define OFST_SDRAM_EN_SHIFT 8
162 #define OFST_IPIPE_EN_SHIFT 9
163 #define OFST_H3A_EN_SHIFT 10
164 #define GAIN_OFFSET_EN_MASK 0x7700
166 /* Culling */
167 #define CULL_PAT_EVEN_LINE_SHIFT 8
169 /* CCDCFG register */
170 #define ISIF_YCINSWP_RAW (0x00 << 4)
171 #define ISIF_YCINSWP_YCBCR (0x01 << 4)
172 #define ISIF_CCDCFG_FIDMD_LATCH_VSYNC (0x00 << 6)
173 #define ISIF_CCDCFG_WENLOG_AND (0x00 << 8)
174 #define ISIF_CCDCFG_TRGSEL_WEN (0x00 << 9)
175 #define ISIF_CCDCFG_EXTRG_DISABLE (0x00 << 10)
176 #define ISIF_LATCH_ON_VSYNC_DISABLE (0x01 << 15)
177 #define ISIF_LATCH_ON_VSYNC_ENABLE (0x00 << 15)
178 #define ISIF_DATA_PACK_MASK 3
179 #define ISIF_DATA_PACK16 0
180 #define ISIF_DATA_PACK12 1
181 #define ISIF_DATA_PACK8 2
182 #define ISIF_PIX_ORDER_SHIFT 11
183 #define ISIF_BW656_ENABLE (0x01 << 5)
185 /* MODESET registers */
186 #define ISIF_VDHDOUT_INPUT (0x00 << 0)
187 #define ISIF_INPUT_SHIFT 12
188 #define ISIF_RAW_INPUT_MODE 0
189 #define ISIF_FID_POL_SHIFT 4
190 #define ISIF_HD_POL_SHIFT 3
191 #define ISIF_VD_POL_SHIFT 2
192 #define ISIF_DATAPOL_NORMAL 0
193 #define ISIF_DATAPOL_SHIFT 6
194 #define ISIF_EXWEN_DISABLE 0
195 #define ISIF_EXWEN_SHIFT 5
196 #define ISIF_FRM_FMT_SHIFT 7
197 #define ISIF_DATASFT_SHIFT 8
198 #define ISIF_LPF_SHIFT 14
199 #define ISIF_LPF_MASK 1
201 /* GAMMAWD registers */
202 #define ISIF_ALAW_GAMMA_WD_MASK 0xF
203 #define ISIF_ALAW_GAMMA_WD_SHIFT 1
204 #define ISIF_ALAW_ENABLE 1
205 #define ISIF_GAMMAWD_CFA_SHIFT 5
207 /* HSIZE registers */
208 #define ISIF_HSIZE_FLIP_MASK 1
209 #define ISIF_HSIZE_FLIP_SHIFT 12
211 /* MISC registers */
212 #define ISIF_DPCM_EN_SHIFT 12
213 #define ISIF_DPCM_PREDICTOR_SHIFT 13
215 /* Black clamp related */
216 #define ISIF_BC_MODE_COLOR_SHIFT 4
217 #define ISIF_HORZ_BC_MODE_SHIFT 1
218 #define ISIF_HORZ_BC_WIN_SEL_SHIFT 5
219 #define ISIF_HORZ_BC_PIX_LIMIT_SHIFT 6
220 #define ISIF_HORZ_BC_WIN_H_SIZE_SHIFT 8
221 #define ISIF_HORZ_BC_WIN_V_SIZE_SHIFT 12
222 #define ISIF_VERT_BC_RST_VAL_SEL_SHIFT 4
223 #define ISIF_VERT_BC_LINE_AVE_COEF_SHIFT 8
225 /* VDFC registers */
226 #define ISIF_VDFC_EN_SHIFT 4
227 #define ISIF_VDFC_CORR_MOD_SHIFT 5
228 #define ISIF_VDFC_CORR_WHOLE_LN_SHIFT 7
229 #define ISIF_VDFC_LEVEL_SHFT_SHIFT 8
230 #define ISIF_VDFC_POS_MASK 0x1FFF
231 #define ISIF_DFCMEMCTL_DFCMARST_SHIFT 2
233 /* CSC registers */
234 #define ISIF_CSC_COEF_INTEG_MASK 7
235 #define ISIF_CSC_COEF_DECIMAL_MASK 0x1f
236 #define ISIF_CSC_COEF_INTEG_SHIFT 5
237 #define ISIF_CSCM_MSB_SHIFT 8
238 #define ISIF_DF_CSC_SPH_MASK 0x1FFF
239 #define ISIF_DF_CSC_LNH_MASK 0x1FFF
240 #define ISIF_DF_CSC_SLV_MASK 0x1FFF
241 #define ISIF_DF_CSC_LNV_MASK 0x1FFF
242 #define ISIF_DF_NUMLINES 0x7FFF
243 #define ISIF_DF_NUMPIX 0x1FFF
245 /* Offsets for LSC/DFC/Gain */
246 #define ISIF_DATA_H_OFFSET_MASK 0x1FFF
247 #define ISIF_DATA_V_OFFSET_MASK 0x1FFF
249 /* Linearization */
250 #define ISIF_LIN_CORRSFT_SHIFT 4
251 #define ISIF_LIN_SCALE_FACT_INTEG_SHIFT 10
254 /* Pattern registers */
255 #define ISIF_PG_EN (1 << 3)
256 #define ISIF_SEL_PG_SRC (3 << 4)
257 #define ISIF_PG_VD_POL_SHIFT 0
258 #define ISIF_PG_HD_POL_SHIFT 1
260 /*random other junk*/
261 #define ISIF_SYNCEN_VDHDEN_MASK (1 << 0)
262 #define ISIF_SYNCEN_WEN_MASK (1 << 1)
263 #define ISIF_SYNCEN_WEN_SHIFT 1
265 #endif