2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: PC Chen <pc.chen@mediatek.com>
4 * Tiffany Lin <tiffany.lin@mediatek.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _MTK_VCODEC_DRV_H_
17 #define _MTK_VCODEC_DRV_H_
19 #include <linux/platform_device.h>
20 #include <linux/videodev2.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/videobuf2-core.h>
25 #include "mtk_vcodec_util.h"
27 #define MTK_VCODEC_DRV_NAME "mtk_vcodec_drv"
28 #define MTK_VCODEC_DEC_NAME "mtk-vcodec-dec"
29 #define MTK_VCODEC_ENC_NAME "mtk-vcodec-enc"
30 #define MTK_PLATFORM_STR "platform:mt8173"
32 #define MTK_VCODEC_MAX_PLANES 3
33 #define MTK_V4L2_BENCHMARK 0
34 #define WAIT_INTR_TIMEOUT_MS 1000
37 * enum mtk_hw_reg_idx - MTK hw register base index
52 NUM_MAX_VDEC_REG_BASE
,
54 VENC_SYS
= NUM_MAX_VDEC_REG_BASE
,
57 NUM_MAX_VCODEC_REG_BASE
61 * enum mtk_instance_type - The type of an MTK Vcodec instance.
63 enum mtk_instance_type
{
69 * enum mtk_instance_state - The state of an MTK Vcodec instance.
70 * @MTK_STATE_FREE - default state when instance is created
71 * @MTK_STATE_INIT - vcodec instance is initialized
72 * @MTK_STATE_HEADER - vdec had sps/pps header parsed or venc
73 * had sps/pps header encoded
74 * @MTK_STATE_FLUSH - vdec is flushing. Only used by decoder
75 * @MTK_STATE_ABORT - vcodec should be aborted
77 enum mtk_instance_state
{
86 * struct mtk_encode_param - General encoding parameters type
88 enum mtk_encode_param
{
89 MTK_ENCODE_PARAM_NONE
= 0,
90 MTK_ENCODE_PARAM_BITRATE
= (1 << 0),
91 MTK_ENCODE_PARAM_FRAMERATE
= (1 << 1),
92 MTK_ENCODE_PARAM_INTRA_PERIOD
= (1 << 2),
93 MTK_ENCODE_PARAM_FORCE_INTRA
= (1 << 3),
94 MTK_ENCODE_PARAM_GOP_SIZE
= (1 << 4),
104 * struct mtk_video_fmt - Structure used to store information about pixelformats
106 struct mtk_video_fmt
{
108 enum mtk_fmt_type type
;
113 * struct mtk_codec_framesizes - Structure used to store information about
116 struct mtk_codec_framesizes
{
118 struct v4l2_frmsize_stepwise stepwise
;
122 * struct mtk_q_type - Type of queue
130 * struct mtk_q_data - Structure used to store information about queue
133 unsigned int visible_width
;
134 unsigned int visible_height
;
135 unsigned int coded_width
;
136 unsigned int coded_height
;
137 enum v4l2_field field
;
138 unsigned int bytesperline
[MTK_VCODEC_MAX_PLANES
];
139 unsigned int sizeimage
[MTK_VCODEC_MAX_PLANES
];
140 struct mtk_video_fmt
*fmt
;
144 * struct mtk_enc_params - General encoding parameters
145 * @bitrate: target bitrate in bits per second
146 * @num_b_frame: number of b frames between p-frame
147 * @rc_frame: frame based rate control
148 * @rc_mb: macroblock based rate control
149 * @seq_hdr_mode: H.264 sequence header is encoded separately or joined
150 * with the first frame
151 * @intra_period: I frame period
152 * @gop_size: group of picture size, it's used as the intra frame period
153 * @framerate_num: frame rate numerator. ex: framerate_num=30 and
154 * framerate_denom=1 menas FPS is 30
155 * @framerate_denom: frame rate denominator. ex: framerate_num=30 and
156 * framerate_denom=1 menas FPS is 30
157 * @h264_max_qp: Max value for H.264 quantization parameter
158 * @h264_profile: V4L2 defined H.264 profile
159 * @h264_level: V4L2 defined H.264 level
160 * @force_intra: force/insert intra frame
162 struct mtk_enc_params
{
163 unsigned int bitrate
;
164 unsigned int num_b_frame
;
165 unsigned int rc_frame
;
167 unsigned int seq_hdr_mode
;
168 unsigned int intra_period
;
169 unsigned int gop_size
;
170 unsigned int framerate_num
;
171 unsigned int framerate_denom
;
172 unsigned int h264_max_qp
;
173 unsigned int h264_profile
;
174 unsigned int h264_level
;
175 unsigned int force_intra
;
179 * struct mtk_vcodec_pm - Power management data structure
181 struct mtk_vcodec_pm
{
182 struct clk
*vdec_bus_clk_src
;
185 struct clk
*vcodecpll
;
186 struct clk
*univpll_d2
;
187 struct clk
*clk_cci400_sel
;
189 struct clk
*vdec_sel
;
190 struct clk
*vencpll_d2
;
191 struct clk
*venc_sel
;
192 struct clk
*univpll1_d2
;
193 struct clk
*venc_lt_sel
;
194 struct device
*larbvdec
;
195 struct device
*larbvenc
;
196 struct device
*larbvenclt
;
198 struct mtk_vcodec_dev
*mtkdev
;
202 * struct vdec_pic_info - picture size information
203 * @pic_w: picture width
204 * @pic_h: picture height
205 * @buf_w: picture buffer width (64 aligned up from pic_w)
206 * @buf_h: picture buffer heiht (64 aligned up from pic_h)
207 * @y_bs_sz: Y bitstream size
208 * @c_bs_sz: CbCr bitstream size
209 * @y_len_sz: additional size required to store decompress information for y
211 * @c_len_sz: additional size required to store decompress information for cbcr
213 * E.g. suppose picture size is 176x144,
214 * buffer size will be aligned to 176x160.
216 struct vdec_pic_info
{
221 unsigned int y_bs_sz
;
222 unsigned int c_bs_sz
;
223 unsigned int y_len_sz
;
224 unsigned int c_len_sz
;
228 * struct mtk_vcodec_ctx - Context (instance) private data.
230 * @type: type of the instance - decoder or encoder
231 * @dev: pointer to the mtk_vcodec_dev of the device
232 * @list: link to ctx_list of mtk_vcodec_dev
233 * @fh: struct v4l2_fh
234 * @m2m_ctx: pointer to the v4l2_m2m_ctx of the context
235 * @q_data: store information of input and output queue
237 * @id: index of the context that this structure describes
238 * @state: state of the context
239 * @param_change: indicate encode parameter type
240 * @enc_params: encoding parameters
241 * @dec_if: hooked decoder driver interface
242 * @enc_if: hoooked encoder driver interface
243 * @drv_handle: driver handle for specific decode/encode instance
245 * @picinfo: store picture info after header parsing
246 * @dpb_size: store dpb count after header parsing
247 * @int_cond: variable used by the waitqueue
248 * @int_type: type of the last interrupt
249 * @queue: waitqueue that can be used to wait for this context to
251 * @irq_status: irq status
253 * @ctrl_hdl: handler for v4l2 framework
254 * @decode_work: worker for the decoding
255 * @encode_work: worker for the encoding
256 * @last_decoded_picinfo: pic information get from latest decode
257 * @empty_flush_buf: a fake size-0 capture buffer that indicates flush
259 * @colorspace: enum v4l2_colorspace; supplemental to pixelformat
260 * @ycbcr_enc: enum v4l2_ycbcr_encoding, Y'CbCr encoding
261 * @quantization: enum v4l2_quantization, colorspace quantization
262 * @xfer_func: enum v4l2_xfer_func, colorspace transfer function
263 * @lock: protect variables accessed by V4L2 threads and worker thread such as
266 struct mtk_vcodec_ctx
{
267 enum mtk_instance_type type
;
268 struct mtk_vcodec_dev
*dev
;
269 struct list_head list
;
272 struct v4l2_m2m_ctx
*m2m_ctx
;
273 struct mtk_q_data q_data
[2];
275 enum mtk_instance_state state
;
276 enum mtk_encode_param param_change
;
277 struct mtk_enc_params enc_params
;
279 const struct vdec_common_if
*dec_if
;
280 const struct venc_common_if
*enc_if
;
281 unsigned long drv_handle
;
283 struct vdec_pic_info picinfo
;
288 wait_queue_head_t queue
;
289 unsigned int irq_status
;
291 struct v4l2_ctrl_handler ctrl_hdl
;
292 struct work_struct decode_work
;
293 struct work_struct encode_work
;
294 struct vdec_pic_info last_decoded_picinfo
;
295 struct mtk_video_dec_buf
*empty_flush_buf
;
297 enum v4l2_colorspace colorspace
;
298 enum v4l2_ycbcr_encoding ycbcr_enc
;
299 enum v4l2_quantization quantization
;
300 enum v4l2_xfer_func xfer_func
;
302 int decoded_frame_cnt
;
308 * struct mtk_vcodec_dev - driver data
309 * @v4l2_dev: V4L2 device to register video devices for.
310 * @vfd_dec: Video device for decoder
311 * @vfd_enc: Video device for encoder.
313 * @m2m_dev_dec: m2m device for decoder
314 * @m2m_dev_enc: m2m device for encoder.
315 * @plat_dev: platform device
316 * @vpu_plat_dev: mtk vpu platform device
317 * @ctx_list: list of struct mtk_vcodec_ctx
318 * @irqlock: protect data access by irq handler and work thread
319 * @curr_ctx: The context that is waiting for codec hardware
321 * @reg_base: Mapped address of MTK Vcodec registers.
323 * @id_counter: used to identify current opened instance
325 * @encode_workqueue: encode work queue
327 * @int_cond: used to identify interrupt condition happen
328 * @int_type: used to identify what kind of interrupt condition happen
329 * @dev_mutex: video_device lock
330 * @queue: waitqueue for waiting for completion of device commands
332 * @dec_irq: decoder irq resource
333 * @enc_irq: h264 encoder irq resource
334 * @enc_lt_irq: vp8 encoder irq resource
336 * @dec_mutex: decoder hardware lock
337 * @enc_mutex: encoder hardware lock.
339 * @pm: power management control
340 * @dec_capability: used to identify decode capability, ex: 4k
341 * @enc_capability: used to identify encode capability
343 struct mtk_vcodec_dev
{
344 struct v4l2_device v4l2_dev
;
345 struct video_device
*vfd_dec
;
346 struct video_device
*vfd_enc
;
348 struct v4l2_m2m_dev
*m2m_dev_dec
;
349 struct v4l2_m2m_dev
*m2m_dev_enc
;
350 struct platform_device
*plat_dev
;
351 struct platform_device
*vpu_plat_dev
;
352 struct list_head ctx_list
;
354 struct mtk_vcodec_ctx
*curr_ctx
;
355 void __iomem
*reg_base
[NUM_MAX_VCODEC_REG_BASE
];
357 unsigned long id_counter
;
359 struct workqueue_struct
*decode_workqueue
;
360 struct workqueue_struct
*encode_workqueue
;
363 struct mutex dev_mutex
;
364 wait_queue_head_t queue
;
370 struct mutex dec_mutex
;
371 struct mutex enc_mutex
;
373 struct mtk_vcodec_pm pm
;
374 unsigned int dec_capability
;
375 unsigned int enc_capability
;
378 static inline struct mtk_vcodec_ctx
*fh_to_ctx(struct v4l2_fh
*fh
)
380 return container_of(fh
, struct mtk_vcodec_ctx
, fh
);
383 static inline struct mtk_vcodec_ctx
*ctrl_to_ctx(struct v4l2_ctrl
*ctrl
)
385 return container_of(ctrl
->handler
, struct mtk_vcodec_ctx
, ctrl_hdl
);
388 #endif /* _MTK_VCODEC_DRV_H_ */