drivers/media/platform/s5p-mfc/s5p_mfc_common.h

   1 /*
   2  * Samsung S5P Multi Format Codec v 5.0
   3  *
   4  * This file contains definitions of enums and structs used by the codec
   5  * driver.
   6  *
   7  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
   8  * Kamil Debski, <k.debski@samsung.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the
  13  * License, or (at your option) any later version
  14  */
  15
  16 #ifndef S5P_MFC_COMMON_H_
  17 #define S5P_MFC_COMMON_H_
  18
  19 #include <linux/platform_device.h>
  20 #include <linux/videodev2.h>
  21 #include <media/v4l2-ctrls.h>
  22 #include <media/v4l2-device.h>
  23 #include <media/v4l2-ioctl.h>
  24 #include <media/videobuf2-v4l2.h>
  25 #include "regs-mfc.h"
  26 #include "regs-mfc-v10.h"
  27
  28 #define S5P_MFC_NAME            "s5p-mfc"
  29
  30 /* Definitions related to MFC memory */
  31
  32 /* Offset base used to differentiate between CAPTURE and OUTPUT
  33 *  while mmaping */
  34 #define DST_QUEUE_OFF_BASE      (1 << 30)
  35
  36 #define BANK_L_CTX      0
  37 #define BANK_R_CTX      1
  38 #define BANK_CTX_NUM    2
  39
  40 #define MFC_BANK1_ALIGN_ORDER   13
  41 #define MFC_BANK2_ALIGN_ORDER   13
  42 #define MFC_BASE_ALIGN_ORDER    17
  43
  44 #define MFC_FW_MAX_VERSIONS     2
  45
  46 #include <media/videobuf2-dma-contig.h>
  47
  48 /* MFC definitions */
  49 #define MFC_MAX_EXTRA_DPB       5
  50 #define MFC_MAX_BUFFERS         32
  51 #define MFC_NUM_CONTEXTS        4
  52 /* Interrupt timeout */
  53 #define MFC_INT_TIMEOUT         2000
  54 /* Busy wait timeout */
  55 #define MFC_BW_TIMEOUT          500
  56 /* Watchdog interval */
  57 #define MFC_WATCHDOG_INTERVAL   1000
  58 /* After how many executions watchdog should assume lock up */
  59 #define MFC_WATCHDOG_CNT        10
  60 #define MFC_NO_INSTANCE_SET     -1
  61 #define MFC_ENC_CAP_PLANE_COUNT 1
  62 #define MFC_ENC_OUT_PLANE_COUNT 2
  63 #define STUFF_BYTE              4
  64 #define MFC_MAX_CTRLS           128
  65
  66 #define S5P_MFC_CODEC_NONE              -1
  67 #define S5P_MFC_CODEC_H264_DEC          0
  68 #define S5P_MFC_CODEC_H264_MVC_DEC      1
  69 #define S5P_MFC_CODEC_VC1_DEC           2
  70 #define S5P_MFC_CODEC_MPEG4_DEC         3
  71 #define S5P_MFC_CODEC_MPEG2_DEC         4
  72 #define S5P_MFC_CODEC_H263_DEC          5
  73 #define S5P_MFC_CODEC_VC1RCV_DEC        6
  74 #define S5P_MFC_CODEC_VP8_DEC           7
  75 #define S5P_MFC_CODEC_HEVC_DEC          17
  76 #define S5P_MFC_CODEC_VP9_DEC           18
  77
  78 #define S5P_MFC_CODEC_H264_ENC          20
  79 #define S5P_MFC_CODEC_H264_MVC_ENC      21
  80 #define S5P_MFC_CODEC_MPEG4_ENC         22
  81 #define S5P_MFC_CODEC_H263_ENC          23
  82 #define S5P_MFC_CODEC_VP8_ENC           24
  83 #define S5P_MFC_CODEC_HEVC_ENC          26
  84
  85 #define S5P_MFC_R2H_CMD_EMPTY                   0
  86 #define S5P_MFC_R2H_CMD_SYS_INIT_RET            1
  87 #define S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET       2
  88 #define S5P_MFC_R2H_CMD_SEQ_DONE_RET            3
  89 #define S5P_MFC_R2H_CMD_INIT_BUFFERS_RET        4
  90 #define S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET      6
  91 #define S5P_MFC_R2H_CMD_SLEEP_RET               7
  92 #define S5P_MFC_R2H_CMD_WAKEUP_RET              8
  93 #define S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET        9
  94 #define S5P_MFC_R2H_CMD_DPB_FLUSH_RET           10
  95 #define S5P_MFC_R2H_CMD_NAL_ABORT_RET           11
  96 #define S5P_MFC_R2H_CMD_FW_STATUS_RET           12
  97 #define S5P_MFC_R2H_CMD_FRAME_DONE_RET          13
  98 #define S5P_MFC_R2H_CMD_FIELD_DONE_RET          14
  99 #define S5P_MFC_R2H_CMD_SLICE_DONE_RET          15
 100 #define S5P_MFC_R2H_CMD_ENC_BUFFER_FUL_RET      16
 101 #define S5P_MFC_R2H_CMD_ERR_RET                 32
 102
 103 #define MFC_MAX_CLOCKS          4
 104
 105 #define mfc_read(dev, offset)           readl(dev->regs_base + (offset))
 106 #define mfc_write(dev, data, offset)    writel((data), dev->regs_base + \
 107                                                                 (offset))
 108
 109 /**
 110  * enum s5p_mfc_fmt_type - type of the pixelformat
 111  */
 112 enum s5p_mfc_fmt_type {
 113         MFC_FMT_DEC,
 114         MFC_FMT_ENC,
 115         MFC_FMT_RAW,
 116 };
 117
 118 /**
 119  * enum s5p_mfc_inst_type - The type of an MFC instance.
 120  */
 121 enum s5p_mfc_inst_type {
 122         MFCINST_INVALID,
 123         MFCINST_DECODER,
 124         MFCINST_ENCODER,
 125 };
 126
 127 /**
 128  * enum s5p_mfc_inst_state - The state of an MFC instance.
 129  */
 130 enum s5p_mfc_inst_state {
 131         MFCINST_FREE = 0,
 132         MFCINST_INIT = 100,
 133         MFCINST_GOT_INST,
 134         MFCINST_HEAD_PARSED,
 135         MFCINST_HEAD_PRODUCED,
 136         MFCINST_BUFS_SET,
 137         MFCINST_RUNNING,
 138         MFCINST_FINISHING,
 139         MFCINST_FINISHED,
 140         MFCINST_RETURN_INST,
 141         MFCINST_ERROR,
 142         MFCINST_ABORT,
 143         MFCINST_FLUSH,
 144         MFCINST_RES_CHANGE_INIT,
 145         MFCINST_RES_CHANGE_FLUSH,
 146         MFCINST_RES_CHANGE_END,
 147 };
 148
 149 /**
 150  * enum s5p_mfc_queue_state - The state of buffer queue.
 151  */
 152 enum s5p_mfc_queue_state {
 153         QUEUE_FREE,
 154         QUEUE_BUFS_REQUESTED,
 155         QUEUE_BUFS_QUERIED,
 156         QUEUE_BUFS_MMAPED,
 157 };
 158
 159 /**
 160  * enum s5p_mfc_decode_arg - type of frame decoding
 161  */
 162 enum s5p_mfc_decode_arg {
 163         MFC_DEC_FRAME,
 164         MFC_DEC_LAST_FRAME,
 165         MFC_DEC_RES_CHANGE,
 166 };
 167
 168 enum s5p_mfc_fw_ver {
 169         MFC_FW_V1,
 170         MFC_FW_V2,
 171 };
 172
 173 #define MFC_BUF_FLAG_USED       (1 << 0)
 174 #define MFC_BUF_FLAG_EOS        (1 << 1)
 175
 176 struct s5p_mfc_ctx;
 177
 178 /**
 179  * struct s5p_mfc_buf - MFC buffer
 180  */
 181 struct s5p_mfc_buf {
 182         struct vb2_v4l2_buffer *b;
 183         struct list_head list;
 184         union {
 185                 struct {
 186                         size_t luma;
 187                         size_t chroma;
 188                 } raw;
 189                 size_t stream;
 190         } cookie;
 191         int flags;
 192 };
 193
 194 /**
 195  * struct s5p_mfc_pm - power management data structure
 196  */
 197 struct s5p_mfc_pm {
 198         struct clk      *clock_gate;
 199         const char * const *clk_names;
 200         struct clk      *clocks[MFC_MAX_CLOCKS];
 201         int             num_clocks;
 202         bool            use_clock_gating;
 203
 204         struct device   *device;
 205 };
 206
 207 struct s5p_mfc_buf_size_v5 {
 208         unsigned int h264_ctx;
 209         unsigned int non_h264_ctx;
 210         unsigned int dsc;
 211         unsigned int shm;
 212 };
 213
 214 struct s5p_mfc_buf_size_v6 {
 215         unsigned int dev_ctx;
 216         unsigned int h264_dec_ctx;
 217         unsigned int other_dec_ctx;
 218         unsigned int h264_enc_ctx;
 219         unsigned int hevc_enc_ctx;
 220         unsigned int other_enc_ctx;
 221 };
 222
 223 struct s5p_mfc_buf_size {
 224         unsigned int fw;
 225         unsigned int cpb;
 226         void *priv;
 227 };
 228
 229 struct s5p_mfc_variant {
 230         unsigned int version;
 231         unsigned int port_num;
 232         u32 version_bit;
 233         struct s5p_mfc_buf_size *buf_size;
 234         char    *fw_name[MFC_FW_MAX_VERSIONS];
 235         const char      *clk_names[MFC_MAX_CLOCKS];
 236         int             num_clocks;
 237         bool            use_clock_gating;
 238 };
 239
 240 /**
 241  * struct s5p_mfc_priv_buf - represents internal used buffer
 242  * @ofs:                offset of each buffer, will be used for MFC
 243  * @virt:               kernel virtual address, only valid when the
 244  *                      buffer accessed by driver
 245  * @dma:                DMA address, only valid when kernel DMA API used
 246  * @size:               size of the buffer
 247  * @ctx:                memory context (bank) used for this allocation
 248  */
 249 struct s5p_mfc_priv_buf {
 250         unsigned long   ofs;
 251         void            *virt;
 252         dma_addr_t      dma;
 253         size_t          size;
 254         unsigned int    ctx;
 255 };
 256
 257 /**
 258  * struct s5p_mfc_dev - The struct containing driver internal parameters.
 259  *
 260  * @v4l2_dev:           v4l2_device
 261  * @vfd_dec:            video device for decoding
 262  * @vfd_enc:            video device for encoding
 263  * @plat_dev:           platform device
 264  * @mem_dev[]:          child devices of the memory banks
 265  * @regs_base:          base address of the MFC hw registers
 266  * @irq:                irq resource
 267  * @dec_ctrl_handler:   control framework handler for decoding
 268  * @enc_ctrl_handler:   control framework handler for encoding
 269  * @pm:                 power management control
 270  * @variant:            MFC hardware variant information
 271  * @num_inst:           couter of active MFC instances
 272  * @irqlock:            lock for operations on videobuf2 queues
 273  * @condlock:           lock for changing/checking if a context is ready to be
 274  *                      processed
 275  * @mfc_mutex:          lock for video_device
 276  * @int_cond:           variable used by the waitqueue
 277  * @int_type:           type of last interrupt
 278  * @int_err:            error number for last interrupt
 279  * @queue:              waitqueue for waiting for completion of device commands
 280  * @fw_size:            size of firmware
 281  * @fw_virt_addr:       virtual firmware address
 282  * @dma_base[]:         address of the beginning of memory banks
 283  * @hw_lock:            used for hardware locking
 284  * @ctx:                array of driver contexts
 285  * @curr_ctx:           number of the currently running context
 286  * @ctx_work_bits:      used to mark which contexts are waiting for hardware
 287  * @watchdog_cnt:       counter for the watchdog
 288  * @watchdog_workqueue: workqueue for the watchdog
 289  * @watchdog_work:      worker for the watchdog
 290  * @enter_suspend:      flag set when entering suspend
 291  * @ctx_buf:            common context memory (MFCv6)
 292  * @warn_start:         hardware error code from which warnings start
 293  * @mfc_ops:            ops structure holding HW operation function pointers
 294  * @mfc_cmds:           cmd structure holding HW commands function pointers
 295  * @mfc_regs:           structure holding MFC registers
 296  * @fw_ver:             loaded firmware sub-version
 297  * @fw_get_done         flag set when request_firmware() is complete and
 298  *                      copied into fw_buf
 299  * risc_on:             flag indicates RISC is on or off
 300  *
 301  */
 302 struct s5p_mfc_dev {
 303         struct v4l2_device      v4l2_dev;
 304         struct video_device     *vfd_dec;
 305         struct video_device     *vfd_enc;
 306         struct platform_device  *plat_dev;
 307         struct device           *mem_dev[BANK_CTX_NUM];
 308         void __iomem            *regs_base;
 309         int                     irq;
 310         struct v4l2_ctrl_handler dec_ctrl_handler;
 311         struct v4l2_ctrl_handler enc_ctrl_handler;
 312         struct s5p_mfc_pm       pm;
 313         const struct s5p_mfc_variant    *variant;
 314         int num_inst;
 315         spinlock_t irqlock;     /* lock when operating on context */
 316         spinlock_t condlock;    /* lock when changing/checking if a context is
 317                                         ready to be processed */
 318         struct mutex mfc_mutex; /* video_device lock */
 319         int int_cond;
 320         int int_type;
 321         unsigned int int_err;
 322         wait_queue_head_t queue;
 323         struct s5p_mfc_priv_buf fw_buf;
 324         size_t mem_size;
 325         dma_addr_t mem_base;
 326         unsigned long *mem_bitmap;
 327         void *mem_virt;
 328         dma_addr_t dma_base[BANK_CTX_NUM];
 329         unsigned long hw_lock;
 330         struct s5p_mfc_ctx *ctx[MFC_NUM_CONTEXTS];
 331         int curr_ctx;
 332         unsigned long ctx_work_bits;
 333         atomic_t watchdog_cnt;
 334         struct timer_list watchdog_timer;
 335         struct workqueue_struct *watchdog_workqueue;
 336         struct work_struct watchdog_work;
 337         unsigned long enter_suspend;
 338
 339         struct s5p_mfc_priv_buf ctx_buf;
 340         int warn_start;
 341         struct s5p_mfc_hw_ops *mfc_ops;
 342         struct s5p_mfc_hw_cmds *mfc_cmds;
 343         const struct s5p_mfc_regs *mfc_regs;
 344         enum s5p_mfc_fw_ver fw_ver;
 345         bool fw_get_done;
 346         bool risc_on; /* indicates if RISC is on or off */
 347 };
 348
 349 /**
 350  * struct s5p_mfc_h264_enc_params - encoding parameters for h264
 351  */
 352 struct s5p_mfc_h264_enc_params {
 353         enum v4l2_mpeg_video_h264_profile profile;
 354         enum v4l2_mpeg_video_h264_loop_filter_mode loop_filter_mode;
 355         s8 loop_filter_alpha;
 356         s8 loop_filter_beta;
 357         enum v4l2_mpeg_video_h264_entropy_mode entropy_mode;
 358         u8 max_ref_pic;
 359         u8 num_ref_pic_4p;
 360         int _8x8_transform;
 361         int rc_mb_dark;
 362         int rc_mb_smooth;
 363         int rc_mb_static;
 364         int rc_mb_activity;
 365         int vui_sar;
 366         u8 vui_sar_idc;
 367         u16 vui_ext_sar_width;
 368         u16 vui_ext_sar_height;
 369         int open_gop;
 370         u16 open_gop_size;
 371         u8 rc_frame_qp;
 372         u8 rc_min_qp;
 373         u8 rc_max_qp;
 374         u8 rc_p_frame_qp;
 375         u8 rc_b_frame_qp;
 376         enum v4l2_mpeg_video_h264_level level_v4l2;
 377         int level;
 378         u16 cpb_size;
 379         int interlace;
 380         u8 hier_qp;
 381         u8 hier_qp_type;
 382         u8 hier_qp_layer;
 383         u8 hier_qp_layer_qp[7];
 384         u8 sei_frame_packing;
 385         u8 sei_fp_curr_frame_0;
 386         u8 sei_fp_arrangement_type;
 387
 388         u8 fmo;
 389         u8 fmo_map_type;
 390         u8 fmo_slice_grp;
 391         u8 fmo_chg_dir;
 392         u32 fmo_chg_rate;
 393         u32 fmo_run_len[4];
 394         u8 aso;
 395         u32 aso_slice_order[8];
 396 };
 397
 398 /**
 399  * struct s5p_mfc_mpeg4_enc_params - encoding parameters for h263 and mpeg4
 400  */
 401 struct s5p_mfc_mpeg4_enc_params {
 402         /* MPEG4 Only */
 403         enum v4l2_mpeg_video_mpeg4_profile profile;
 404         int quarter_pixel;
 405         /* Common for MPEG4, H263 */
 406         u16 vop_time_res;
 407         u16 vop_frm_delta;
 408         u8 rc_frame_qp;
 409         u8 rc_min_qp;
 410         u8 rc_max_qp;
 411         u8 rc_p_frame_qp;
 412         u8 rc_b_frame_qp;
 413         enum v4l2_mpeg_video_mpeg4_level level_v4l2;
 414         int level;
 415 };
 416
 417 /**
 418  * struct s5p_mfc_vp8_enc_params - encoding parameters for vp8
 419  */
 420 struct s5p_mfc_vp8_enc_params {
 421         u8 imd_4x4;
 422         enum v4l2_vp8_num_partitions num_partitions;
 423         enum v4l2_vp8_num_ref_frames num_ref;
 424         u8 filter_level;
 425         u8 filter_sharpness;
 426         u32 golden_frame_ref_period;
 427         enum v4l2_vp8_golden_frame_sel golden_frame_sel;
 428         u8 hier_layer;
 429         u8 hier_layer_qp[3];
 430         u8 rc_min_qp;
 431         u8 rc_max_qp;
 432         u8 rc_frame_qp;
 433         u8 rc_p_frame_qp;
 434         u8 profile;
 435 };
 436
 437 struct s5p_mfc_hevc_enc_params {
 438         enum v4l2_mpeg_video_hevc_profile profile;
 439         int level;
 440         enum v4l2_mpeg_video_h264_level level_v4l2;
 441         u8 tier;
 442         u32 rc_framerate;
 443         u8 rc_min_qp;
 444         u8 rc_max_qp;
 445         u8 rc_lcu_dark;
 446         u8 rc_lcu_smooth;
 447         u8 rc_lcu_static;
 448         u8 rc_lcu_activity;
 449         u8 rc_frame_qp;
 450         u8 rc_p_frame_qp;
 451         u8 rc_b_frame_qp;
 452         u8 max_partition_depth;
 453         u8 num_refs_for_p;
 454         u8 refreshtype;
 455         u16 refreshperiod;
 456         s32 lf_beta_offset_div2;
 457         s32 lf_tc_offset_div2;
 458         u8 loopfilter;
 459         u8 loopfilter_disable;
 460         u8 loopfilter_across;
 461         u8 nal_control_length_filed;
 462         u8 nal_control_user_ref;
 463         u8 nal_control_store_ref;
 464         u8 const_intra_period_enable;
 465         u8 lossless_cu_enable;
 466         u8 wavefront_enable;
 467         u8 enable_ltr;
 468         u8 hier_qp_enable;
 469         enum v4l2_mpeg_video_hevc_hier_coding_type hier_qp_type;
 470         u8 num_hier_layer;
 471         u8 hier_qp_layer[7];
 472         u32 hier_bit_layer[7];
 473         u8 sign_data_hiding;
 474         u8 general_pb_enable;
 475         u8 temporal_id_enable;
 476         u8 strong_intra_smooth;
 477         u8 intra_pu_split_disable;
 478         u8 tmv_prediction_disable;
 479         u8 max_num_merge_mv;
 480         u8 eco_mode_enable;
 481         u8 encoding_nostartcode_enable;
 482         u8 size_of_length_field;
 483         u8 prepend_sps_pps_to_idr;
 484 };
 485
 486 /**
 487  * struct s5p_mfc_enc_params - general encoding parameters
 488  */
 489 struct s5p_mfc_enc_params {
 490         u16 width;
 491         u16 height;
 492         u32 mv_h_range;
 493         u32 mv_v_range;
 494
 495         u16 gop_size;
 496         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 497         u16 slice_mb;
 498         u32 slice_bit;
 499         u16 intra_refresh_mb;
 500         int pad;
 501         u8 pad_luma;
 502         u8 pad_cb;
 503         u8 pad_cr;
 504         int rc_frame;
 505         int rc_mb;
 506         u32 rc_bitrate;
 507         u16 rc_reaction_coeff;
 508         u16 vbv_size;
 509         u32 vbv_delay;
 510
 511         enum v4l2_mpeg_video_header_mode seq_hdr_mode;
 512         enum v4l2_mpeg_mfc51_video_frame_skip_mode frame_skip_mode;
 513         int fixed_target_bit;
 514
 515         u8 num_b_frame;
 516         u32 rc_framerate_num;
 517         u32 rc_framerate_denom;
 518
 519         struct {
 520                 struct s5p_mfc_h264_enc_params h264;
 521                 struct s5p_mfc_mpeg4_enc_params mpeg4;
 522                 struct s5p_mfc_vp8_enc_params vp8;
 523                 struct s5p_mfc_hevc_enc_params hevc;
 524         } codec;
 525
 526 };
 527
 528 /**
 529  * struct s5p_mfc_codec_ops - codec ops, used by encoding
 530  */
 531 struct s5p_mfc_codec_ops {
 532         /* initialization routines */
 533         int (*pre_seq_start) (struct s5p_mfc_ctx *ctx);
 534         int (*post_seq_start) (struct s5p_mfc_ctx *ctx);
 535         /* execution routines */
 536         int (*pre_frame_start) (struct s5p_mfc_ctx *ctx);
 537         int (*post_frame_start) (struct s5p_mfc_ctx *ctx);
 538 };
 539
 540 #define call_cop(c, op, args...)                                \
 541         (((c)->c_ops->op) ?                                     \
 542                 ((c)->c_ops->op(args)) : 0)
 543
 544 /**
 545  * struct s5p_mfc_ctx - This struct contains the instance context
 546  *
 547  * @dev:                pointer to the s5p_mfc_dev of the device
 548  * @fh:                 struct v4l2_fh
 549  * @num:                number of the context that this structure describes
 550  * @int_cond:           variable used by the waitqueue
 551  * @int_type:           type of the last interrupt
 552  * @int_err:            error number received from MFC hw in the interrupt
 553  * @queue:              waitqueue that can be used to wait for this context to
 554  *                      finish
 555  * @src_fmt:            source pixelformat information
 556  * @dst_fmt:            destination pixelformat information
 557  * @vq_src:             vb2 queue for source buffers
 558  * @vq_dst:             vb2 queue for destination buffers
 559  * @src_queue:          driver internal queue for source buffers
 560  * @dst_queue:          driver internal queue for destination buffers
 561  * @src_queue_cnt:      number of buffers queued on the source internal queue
 562  * @dst_queue_cnt:      number of buffers queued on the dest internal queue
 563  * @type:               type of the instance - decoder or encoder
 564  * @state:              state of the context
 565  * @inst_no:            number of hw instance associated with the context
 566  * @img_width:          width of the image that is decoded or encoded
 567  * @img_height:         height of the image that is decoded or encoded
 568  * @buf_width:          width of the buffer for processed image
 569  * @buf_height:         height of the buffer for processed image
 570  * @luma_size:          size of a luma plane
 571  * @chroma_size:        size of a chroma plane
 572  * @mv_size:            size of a motion vectors buffer
 573  * @consumed_stream:    number of bytes that have been used so far from the
 574  *                      decoding buffer
 575  * @dpb_flush_flag:     flag used to indicate that a DPB buffers are being
 576  *                      flushed
 577  * @head_processed:     flag mentioning whether the header data is processed
 578  *                      completely or not
 579  * @bank1:              handle to memory allocated for temporary buffers from
 580  *                      memory bank 1
 581  * @bank2:              handle to memory allocated for temporary buffers from
 582  *                      memory bank 2
 583  * @capture_state:      state of the capture buffers queue
 584  * @output_state:       state of the output buffers queue
 585  * @src_bufs:           information on allocated source buffers
 586  * @dst_bufs:           information on allocated destination buffers
 587  * @sequence:           counter for the sequence number for v4l2
 588  * @dec_dst_flag:       flags for buffers queued in the hardware
 589  * @dec_src_buf_size:   size of the buffer for source buffers in decoding
 590  * @codec_mode:         number of codec mode used by MFC hw
 591  * @slice_interface:    slice interface flag
 592  * @loop_filter_mpeg4:  loop filter for MPEG4 flag
 593  * @display_delay:      value of the display delay for H264
 594  * @display_delay_enable:       display delay for H264 enable flag
 595  * @after_packed_pb:    flag used to track buffer when stream is in
 596  *                      Packed PB format
 597  * @sei_fp_parse:       enable/disable parsing of frame packing SEI information
 598  * @dpb_count:          count of the DPB buffers required by MFC hw
 599  * @total_dpb_count:    count of DPB buffers with additional buffers
 600  *                      requested by the application
 601  * @ctx:                context buffer information
 602  * @dsc:                descriptor buffer information
 603  * @shm:                shared memory buffer information
 604  * @mv_count:           number of MV buffers allocated for decoding
 605  * @enc_params:         encoding parameters for MFC
 606  * @enc_dst_buf_size:   size of the buffers for encoder output
 607  * @luma_dpb_size:      dpb buffer size for luma
 608  * @chroma_dpb_size:    dpb buffer size for chroma
 609  * @me_buffer_size:     size of the motion estimation buffer
 610  * @tmv_buffer_size:    size of temporal predictor motion vector buffer
 611  * @frame_type:         used to force the type of the next encoded frame
 612  * @ref_queue:          list of the reference buffers for encoding
 613  * @ref_queue_cnt:      number of the buffers in the reference list
 614  * @c_ops:              ops for encoding
 615  * @ctrls:              array of controls, used when adding controls to the
 616  *                      v4l2 control framework
 617  * @ctrl_handler:       handler for v4l2 framework
 618  */
 619 struct s5p_mfc_ctx {
 620         struct s5p_mfc_dev *dev;
 621         struct v4l2_fh fh;
 622
 623         int num;
 624
 625         int int_cond;
 626         int int_type;
 627         unsigned int int_err;
 628         wait_queue_head_t queue;
 629
 630         struct s5p_mfc_fmt *src_fmt;
 631         struct s5p_mfc_fmt *dst_fmt;
 632
 633         struct vb2_queue vq_src;
 634         struct vb2_queue vq_dst;
 635
 636         struct list_head src_queue;
 637         struct list_head dst_queue;
 638
 639         unsigned int src_queue_cnt;
 640         unsigned int dst_queue_cnt;
 641
 642         enum s5p_mfc_inst_type type;
 643         enum s5p_mfc_inst_state state;
 644         int inst_no;
 645
 646         /* Image parameters */
 647         int img_width;
 648         int img_height;
 649         int buf_width;
 650         int buf_height;
 651
 652         int luma_size;
 653         int chroma_size;
 654         int mv_size;
 655
 656         unsigned long consumed_stream;
 657
 658         unsigned int dpb_flush_flag;
 659         unsigned int head_processed;
 660
 661         struct s5p_mfc_priv_buf bank1;
 662         struct s5p_mfc_priv_buf bank2;
 663
 664         enum s5p_mfc_queue_state capture_state;
 665         enum s5p_mfc_queue_state output_state;
 666
 667         struct s5p_mfc_buf src_bufs[MFC_MAX_BUFFERS];
 668         int src_bufs_cnt;
 669         struct s5p_mfc_buf dst_bufs[MFC_MAX_BUFFERS];
 670         int dst_bufs_cnt;
 671
 672         unsigned int sequence;
 673         unsigned long dec_dst_flag;
 674         size_t dec_src_buf_size;
 675
 676         /* Control values */
 677         int codec_mode;
 678         int slice_interface;
 679         int loop_filter_mpeg4;
 680         int display_delay;
 681         int display_delay_enable;
 682         int after_packed_pb;
 683         int sei_fp_parse;
 684
 685         int pb_count;
 686         int total_dpb_count;
 687         int mv_count;
 688         /* Buffers */
 689         struct s5p_mfc_priv_buf ctx;
 690         struct s5p_mfc_priv_buf dsc;
 691         struct s5p_mfc_priv_buf shm;
 692
 693         struct s5p_mfc_enc_params enc_params;
 694
 695         size_t enc_dst_buf_size;
 696         size_t luma_dpb_size;
 697         size_t chroma_dpb_size;
 698         size_t me_buffer_size;
 699         size_t tmv_buffer_size;
 700
 701         enum v4l2_mpeg_mfc51_video_force_frame_type force_frame_type;
 702
 703         struct list_head ref_queue;
 704         unsigned int ref_queue_cnt;
 705
 706         enum v4l2_mpeg_video_multi_slice_mode slice_mode;
 707         union {
 708                 unsigned int mb;
 709                 unsigned int bits;
 710         } slice_size;
 711
 712         const struct s5p_mfc_codec_ops *c_ops;
 713
 714         struct v4l2_ctrl *ctrls[MFC_MAX_CTRLS];
 715         struct v4l2_ctrl_handler ctrl_handler;
 716         unsigned int frame_tag;
 717         size_t scratch_buf_size;
 718 };
 719
 720 /*
 721  * struct s5p_mfc_fmt - structure used to store information about pixelformats
 722  *                      used by the MFC
 723  */
 724 struct s5p_mfc_fmt {
 725         char *name;
 726         u32 fourcc;
 727         u32 codec_mode;
 728         enum s5p_mfc_fmt_type type;
 729         u32 num_planes;
 730         u32 versions;
 731 };
 732
 733 /**
 734  * struct mfc_control - structure used to store information about MFC controls
 735  *                      it is used to initialize the control framework.
 736  */
 737 struct mfc_control {
 738         __u32                   id;
 739         enum v4l2_ctrl_type     type;
 740         __u8                    name[32];  /* Whatever */
 741         __s32                   minimum;   /* Note signedness */
 742         __s32                   maximum;
 743         __s32                   step;
 744         __u32                   menu_skip_mask;
 745         __s32                   default_value;
 746         __u32                   flags;
 747         __u32                   reserved[2];
 748         __u8                    is_volatile;
 749 };
 750
 751 /* Macro for making hardware specific calls */
 752 #define s5p_mfc_hw_call(f, op, args...) \
 753         ((f && f->op) ? f->op(args) : (typeof(f->op(args)))(-ENODEV))
 754
 755 #define fh_to_ctx(__fh) container_of(__fh, struct s5p_mfc_ctx, fh)
 756 #define ctrl_to_ctx(__ctrl) \
 757         container_of((__ctrl)->handler, struct s5p_mfc_ctx, ctrl_handler)
 758
 759 void clear_work_bit(struct s5p_mfc_ctx *ctx);
 760 void set_work_bit(struct s5p_mfc_ctx *ctx);
 761 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
 762 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx);
 763 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev);
 764 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq);
 765
 766 #define HAS_PORTNUM(dev)        (dev ? (dev->variant ? \
 767                                 (dev->variant->port_num ? 1 : 0) : 0) : 0)
 768 #define IS_TWOPORT(dev)         (dev->variant->port_num == 2 ? 1 : 0)
 769 #define IS_MFCV6_PLUS(dev)      (dev->variant->version >= 0x60 ? 1 : 0)
 770 #define IS_MFCV7_PLUS(dev)      (dev->variant->version >= 0x70 ? 1 : 0)
 771 #define IS_MFCV8_PLUS(dev)      (dev->variant->version >= 0x80 ? 1 : 0)
 772 #define IS_MFCV10(dev)          (dev->variant->version >= 0xA0 ? 1 : 0)
 773 #define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev))
 774
 775 #define MFC_V5_BIT      BIT(0)
 776 #define MFC_V6_BIT      BIT(1)
 777 #define MFC_V7_BIT      BIT(2)
 778 #define MFC_V8_BIT      BIT(3)
 779 #define MFC_V10_BIT     BIT(5)
 780
 781 #define MFC_V5PLUS_BITS         (MFC_V5_BIT | MFC_V6_BIT | MFC_V7_BIT | \
 782                                         MFC_V8_BIT | MFC_V10_BIT)
 783 #define MFC_V6PLUS_BITS         (MFC_V6_BIT | MFC_V7_BIT | MFC_V8_BIT | \
 784                                         MFC_V10_BIT)
 785 #define MFC_V7PLUS_BITS         (MFC_V7_BIT | MFC_V8_BIT | MFC_V10_BIT)
 786
 787 #endif /* S5P_MFC_COMMON_H_ */