drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c

   1 /*
   2  * linux/drivers/media/platform/s5p-mfc/s5p_mfc_ctrl.c
   3  *
   4  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com/
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/delay.h>
  14 #include <linux/err.h>
  15 #include <linux/firmware.h>
  16 #include <linux/jiffies.h>
  17 #include <linux/sched.h>
  18 #include "s5p_mfc_cmd.h"
  19 #include "s5p_mfc_common.h"
  20 #include "s5p_mfc_debug.h"
  21 #include "s5p_mfc_intr.h"
  22 #include "s5p_mfc_opr.h"
  23 #include "s5p_mfc_pm.h"
  24 #include "s5p_mfc_ctrl.h"
  25
  26 /* Allocate memory for firmware */
  27 int s5p_mfc_alloc_firmware(struct s5p_mfc_dev *dev)
  28 {
  29         struct s5p_mfc_priv_buf *fw_buf = &dev->fw_buf;
  30         int err;
  31
  32         fw_buf->size = dev->variant->buf_size->fw;
  33
  34         if (fw_buf->virt) {
  35                 mfc_err("Attempting to allocate firmware when it seems that it is already loaded\n");
  36                 return -ENOMEM;
  37         }
  38
  39         err = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->fw_buf);
  40         if (err) {
  41                 mfc_err("Allocating bitprocessor buffer failed\n");
  42                 return err;
  43         }
  44
  45         return 0;
  46 }
  47
  48 /* Load firmware */
  49 int s5p_mfc_load_firmware(struct s5p_mfc_dev *dev)
  50 {
  51         struct firmware *fw_blob;
  52         int i, err = -EINVAL;
  53
  54         /* Firmare has to be present as a separate file or compiled
  55          * into kernel. */
  56         mfc_debug_enter();
  57
  58         if (dev->fw_get_done)
  59                 return 0;
  60
  61         for (i = MFC_FW_MAX_VERSIONS - 1; i >= 0; i--) {
  62                 if (!dev->variant->fw_name[i])
  63                         continue;
  64                 err = request_firmware((const struct firmware **)&fw_blob,
  65                                 dev->variant->fw_name[i], &dev->plat_dev->dev);
  66                 if (!err) {
  67                         dev->fw_ver = (enum s5p_mfc_fw_ver) i;
  68                         break;
  69                 }
  70         }
  71
  72         if (err != 0) {
  73                 mfc_err("Firmware is not present in the /lib/firmware directory nor compiled in kernel\n");
  74                 return -EINVAL;
  75         }
  76         if (fw_blob->size > dev->fw_buf.size) {
  77                 mfc_err("MFC firmware is too big to be loaded\n");
  78                 release_firmware(fw_blob);
  79                 return -ENOMEM;
  80         }
  81         memcpy(dev->fw_buf.virt, fw_blob->data, fw_blob->size);
  82         wmb();
  83         dev->fw_get_done = true;
  84         release_firmware(fw_blob);
  85         mfc_debug_leave();
  86         return 0;
  87 }
  88
  89 /* Release firmware memory */
  90 int s5p_mfc_release_firmware(struct s5p_mfc_dev *dev)
  91 {
  92         /* Before calling this function one has to make sure
  93          * that MFC is no longer processing */
  94         s5p_mfc_release_priv_buf(dev, &dev->fw_buf);
  95         dev->fw_get_done = false;
  96         return 0;
  97 }
  98
  99 static int s5p_mfc_bus_reset(struct s5p_mfc_dev *dev)
 100 {
 101         unsigned int status;
 102         unsigned long timeout;
 103
 104         /* Reset */
 105         mfc_write(dev, 0x1, S5P_FIMV_MFC_BUS_RESET_CTRL);
 106         timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
 107         /* Check bus status */
 108         do {
 109                 if (time_after(jiffies, timeout)) {
 110                         mfc_err("Timeout while resetting MFC.\n");
 111                         return -EIO;
 112                 }
 113                 status = mfc_read(dev, S5P_FIMV_MFC_BUS_RESET_CTRL);
 114         } while ((status & 0x2) == 0);
 115         return 0;
 116 }
 117
 118 /* Reset the device */
 119 int s5p_mfc_reset(struct s5p_mfc_dev *dev)
 120 {
 121         unsigned int mc_status;
 122         unsigned long timeout;
 123         int i;
 124
 125         mfc_debug_enter();
 126
 127         if (IS_MFCV6_PLUS(dev)) {
 128                 /* Zero Initialization of MFC registers */
 129                 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD_V6);
 130                 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD_V6);
 131                 mfc_write(dev, 0, S5P_FIMV_FW_VERSION_V6);
 132
 133                 for (i = 0; i < S5P_FIMV_REG_CLEAR_COUNT_V6; i++)
 134                         mfc_write(dev, 0, S5P_FIMV_REG_CLEAR_BEGIN_V6 + (i*4));
 135
 136                 /* check bus reset control before reset */
 137                 if (dev->risc_on)
 138                         if (s5p_mfc_bus_reset(dev))
 139                                 return -EIO;
 140                 /* Reset
 141                  * set RISC_ON to 0 during power_on & wake_up.
 142                  * V6 needs RISC_ON set to 0 during reset also.
 143                  */
 144                 if ((!dev->risc_on) || (!IS_MFCV7_PLUS(dev)))
 145                         mfc_write(dev, 0, S5P_FIMV_RISC_ON_V6);
 146
 147                 mfc_write(dev, 0x1FFF, S5P_FIMV_MFC_RESET_V6);
 148                 mfc_write(dev, 0, S5P_FIMV_MFC_RESET_V6);
 149         } else {
 150                 /* Stop procedure */
 151                 /*  reset RISC */
 152                 mfc_write(dev, 0x3f6, S5P_FIMV_SW_RESET);
 153                 /*  All reset except for MC */
 154                 mfc_write(dev, 0x3e2, S5P_FIMV_SW_RESET);
 155                 mdelay(10);
 156
 157                 timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
 158                 /* Check MC status */
 159                 do {
 160                         if (time_after(jiffies, timeout)) {
 161                                 mfc_err("Timeout while resetting MFC\n");
 162                                 return -EIO;
 163                         }
 164
 165                         mc_status = mfc_read(dev, S5P_FIMV_MC_STATUS);
 166
 167                 } while (mc_status & 0x3);
 168
 169                 mfc_write(dev, 0x0, S5P_FIMV_SW_RESET);
 170                 mfc_write(dev, 0x3fe, S5P_FIMV_SW_RESET);
 171         }
 172
 173         mfc_debug_leave();
 174         return 0;
 175 }
 176
 177 static inline void s5p_mfc_init_memctrl(struct s5p_mfc_dev *dev)
 178 {
 179         if (IS_MFCV6_PLUS(dev)) {
 180                 mfc_write(dev, dev->dma_base[BANK_L_CTX],
 181                           S5P_FIMV_RISC_BASE_ADDRESS_V6);
 182                 mfc_debug(2, "Base Address : %pad\n",
 183                           &dev->dma_base[BANK_L_CTX]);
 184         } else {
 185                 mfc_write(dev, dev->dma_base[BANK_L_CTX],
 186                           S5P_FIMV_MC_DRAMBASE_ADR_A);
 187                 mfc_write(dev, dev->dma_base[BANK_R_CTX],
 188                           S5P_FIMV_MC_DRAMBASE_ADR_B);
 189                 mfc_debug(2, "Bank1: %pad, Bank2: %pad\n",
 190                           &dev->dma_base[BANK_L_CTX],
 191                           &dev->dma_base[BANK_R_CTX]);
 192         }
 193 }
 194
 195 static inline void s5p_mfc_clear_cmds(struct s5p_mfc_dev *dev)
 196 {
 197         if (IS_MFCV6_PLUS(dev)) {
 198                 /* Zero initialization should be done before RESET.
 199                  * Nothing to do here. */
 200         } else {
 201                 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH0_INST_ID);
 202                 mfc_write(dev, 0xffffffff, S5P_FIMV_SI_CH1_INST_ID);
 203                 mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD);
 204                 mfc_write(dev, 0, S5P_FIMV_HOST2RISC_CMD);
 205         }
 206 }
 207
 208 /* Initialize hardware */
 209 int s5p_mfc_init_hw(struct s5p_mfc_dev *dev)
 210 {
 211         unsigned int ver;
 212         int ret;
 213
 214         mfc_debug_enter();
 215         if (!dev->fw_buf.virt) {
 216                 mfc_err("Firmware memory is not allocated.\n");
 217                 return -EINVAL;
 218         }
 219
 220         /* 0. MFC reset */
 221         mfc_debug(2, "MFC reset..\n");
 222         s5p_mfc_clock_on();
 223         dev->risc_on = 0;
 224         ret = s5p_mfc_reset(dev);
 225         if (ret) {
 226                 mfc_err("Failed to reset MFC - timeout\n");
 227                 return ret;
 228         }
 229         mfc_debug(2, "Done MFC reset..\n");
 230         /* 1. Set DRAM base Addr */
 231         s5p_mfc_init_memctrl(dev);
 232         /* 2. Initialize registers of channel I/F */
 233         s5p_mfc_clear_cmds(dev);
 234         /* 3. Release reset signal to the RISC */
 235         s5p_mfc_clean_dev_int_flags(dev);
 236         if (IS_MFCV6_PLUS(dev)) {
 237                 dev->risc_on = 1;
 238                 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
 239         }
 240         else
 241                 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
 242
 243         if (IS_MFCV10(dev))
 244                 mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10);
 245
 246         mfc_debug(2, "Will now wait for completion of firmware transfer\n");
 247         if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
 248                 mfc_err("Failed to load firmware\n");
 249                 s5p_mfc_reset(dev);
 250                 s5p_mfc_clock_off();
 251                 return -EIO;
 252         }
 253         s5p_mfc_clean_dev_int_flags(dev);
 254         /* 4. Initialize firmware */
 255         ret = s5p_mfc_hw_call(dev->mfc_cmds, sys_init_cmd, dev);
 256         if (ret) {
 257                 mfc_err("Failed to send command to MFC - timeout\n");
 258                 s5p_mfc_reset(dev);
 259                 s5p_mfc_clock_off();
 260                 return ret;
 261         }
 262         mfc_debug(2, "Ok, now will wait for completion of hardware init\n");
 263         if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SYS_INIT_RET)) {
 264                 mfc_err("Failed to init hardware\n");
 265                 s5p_mfc_reset(dev);
 266                 s5p_mfc_clock_off();
 267                 return -EIO;
 268         }
 269         dev->int_cond = 0;
 270         if (dev->int_err != 0 || dev->int_type !=
 271                                         S5P_MFC_R2H_CMD_SYS_INIT_RET) {
 272                 /* Failure. */
 273                 mfc_err("Failed to init firmware - error: %d int: %d\n",
 274                                                 dev->int_err, dev->int_type);
 275                 s5p_mfc_reset(dev);
 276                 s5p_mfc_clock_off();
 277                 return -EIO;
 278         }
 279         if (IS_MFCV6_PLUS(dev))
 280                 ver = mfc_read(dev, S5P_FIMV_FW_VERSION_V6);
 281         else
 282                 ver = mfc_read(dev, S5P_FIMV_FW_VERSION);
 283
 284         mfc_debug(2, "MFC F/W version : %02xyy, %02xmm, %02xdd\n",
 285                 (ver >> 16) & 0xFF, (ver >> 8) & 0xFF, ver & 0xFF);
 286         s5p_mfc_clock_off();
 287         mfc_debug_leave();
 288         return 0;
 289 }
 290
 291
 292 /* Deinitialize hardware */
 293 void s5p_mfc_deinit_hw(struct s5p_mfc_dev *dev)
 294 {
 295         s5p_mfc_clock_on();
 296
 297         s5p_mfc_reset(dev);
 298         s5p_mfc_hw_call(dev->mfc_ops, release_dev_context_buffer, dev);
 299
 300         s5p_mfc_clock_off();
 301 }
 302
 303 int s5p_mfc_sleep(struct s5p_mfc_dev *dev)
 304 {
 305         int ret;
 306
 307         mfc_debug_enter();
 308         s5p_mfc_clock_on();
 309         s5p_mfc_clean_dev_int_flags(dev);
 310         ret = s5p_mfc_hw_call(dev->mfc_cmds, sleep_cmd, dev);
 311         if (ret) {
 312                 mfc_err("Failed to send command to MFC - timeout\n");
 313                 return ret;
 314         }
 315         if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_SLEEP_RET)) {
 316                 mfc_err("Failed to sleep\n");
 317                 return -EIO;
 318         }
 319         s5p_mfc_clock_off();
 320         dev->int_cond = 0;
 321         if (dev->int_err != 0 || dev->int_type !=
 322                                                 S5P_MFC_R2H_CMD_SLEEP_RET) {
 323                 /* Failure. */
 324                 mfc_err("Failed to sleep - error: %d int: %d\n", dev->int_err,
 325                                                                 dev->int_type);
 326                 return -EIO;
 327         }
 328         mfc_debug_leave();
 329         return ret;
 330 }
 331
 332 static int s5p_mfc_v8_wait_wakeup(struct s5p_mfc_dev *dev)
 333 {
 334         int ret;
 335
 336         /* Release reset signal to the RISC */
 337         dev->risc_on = 1;
 338         mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
 339
 340         if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_FW_STATUS_RET)) {
 341                 mfc_err("Failed to reset MFCV8\n");
 342                 return -EIO;
 343         }
 344         mfc_debug(2, "Write command to wakeup MFCV8\n");
 345         ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
 346         if (ret) {
 347                 mfc_err("Failed to send command to MFCV8 - timeout\n");
 348                 return ret;
 349         }
 350
 351         if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
 352                 mfc_err("Failed to wakeup MFC\n");
 353                 return -EIO;
 354         }
 355         return ret;
 356 }
 357
 358 static int s5p_mfc_wait_wakeup(struct s5p_mfc_dev *dev)
 359 {
 360         int ret;
 361
 362         /* Send MFC wakeup command */
 363         ret = s5p_mfc_hw_call(dev->mfc_cmds, wakeup_cmd, dev);
 364         if (ret) {
 365                 mfc_err("Failed to send command to MFC - timeout\n");
 366                 return ret;
 367         }
 368
 369         /* Release reset signal to the RISC */
 370         if (IS_MFCV6_PLUS(dev)) {
 371                 dev->risc_on = 1;
 372                 mfc_write(dev, 0x1, S5P_FIMV_RISC_ON_V6);
 373         } else {
 374                 mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET);
 375         }
 376
 377         if (s5p_mfc_wait_for_done_dev(dev, S5P_MFC_R2H_CMD_WAKEUP_RET)) {
 378                 mfc_err("Failed to wakeup MFC\n");
 379                 return -EIO;
 380         }
 381         return ret;
 382 }
 383
 384 int s5p_mfc_wakeup(struct s5p_mfc_dev *dev)
 385 {
 386         int ret;
 387
 388         mfc_debug_enter();
 389         /* 0. MFC reset */
 390         mfc_debug(2, "MFC reset..\n");
 391         s5p_mfc_clock_on();
 392         dev->risc_on = 0;
 393         ret = s5p_mfc_reset(dev);
 394         if (ret) {
 395                 mfc_err("Failed to reset MFC - timeout\n");
 396                 s5p_mfc_clock_off();
 397                 return ret;
 398         }
 399         mfc_debug(2, "Done MFC reset..\n");
 400         /* 1. Set DRAM base Addr */
 401         s5p_mfc_init_memctrl(dev);
 402         /* 2. Initialize registers of channel I/F */
 403         s5p_mfc_clear_cmds(dev);
 404         s5p_mfc_clean_dev_int_flags(dev);
 405         /* 3. Send MFC wakeup command and wait for completion*/
 406         if (IS_MFCV8_PLUS(dev))
 407                 ret = s5p_mfc_v8_wait_wakeup(dev);
 408         else
 409                 ret = s5p_mfc_wait_wakeup(dev);
 410
 411         s5p_mfc_clock_off();
 412         if (ret)
 413                 return ret;
 414
 415         dev->int_cond = 0;
 416         if (dev->int_err != 0 || dev->int_type !=
 417                                                 S5P_MFC_R2H_CMD_WAKEUP_RET) {
 418                 /* Failure. */
 419                 mfc_err("Failed to wakeup - error: %d int: %d\n", dev->int_err,
 420                                                                 dev->int_type);
 421                 return -EIO;
 422         }
 423         mfc_debug_leave();
 424         return 0;
 425 }
 426
 427 int s5p_mfc_open_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
 428 {
 429         int ret = 0;
 430
 431         ret = s5p_mfc_hw_call(dev->mfc_ops, alloc_instance_buffer, ctx);
 432         if (ret) {
 433                 mfc_err("Failed allocating instance buffer\n");
 434                 goto err;
 435         }
 436
 437         if (ctx->type == MFCINST_DECODER) {
 438                 ret = s5p_mfc_hw_call(dev->mfc_ops,
 439                                         alloc_dec_temp_buffers, ctx);
 440                 if (ret) {
 441                         mfc_err("Failed allocating temporary buffers\n");
 442                         goto err_free_inst_buf;
 443                 }
 444         }
 445
 446         set_work_bit_irqsave(ctx);
 447         s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 448         if (s5p_mfc_wait_for_done_ctx(ctx,
 449                 S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET, 0)) {
 450                 /* Error or timeout */
 451                 mfc_err("Error getting instance from hardware\n");
 452                 ret = -EIO;
 453                 goto err_free_desc_buf;
 454         }
 455
 456         mfc_debug(2, "Got instance number: %d\n", ctx->inst_no);
 457         return ret;
 458
 459 err_free_desc_buf:
 460         if (ctx->type == MFCINST_DECODER)
 461                 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
 462 err_free_inst_buf:
 463         s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
 464 err:
 465         return ret;
 466 }
 467
 468 void s5p_mfc_close_mfc_inst(struct s5p_mfc_dev *dev, struct s5p_mfc_ctx *ctx)
 469 {
 470         ctx->state = MFCINST_RETURN_INST;
 471         set_work_bit_irqsave(ctx);
 472         s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
 473         /* Wait until instance is returned or timeout occurred */
 474         if (s5p_mfc_wait_for_done_ctx(ctx,
 475                                 S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET, 0))
 476                 mfc_err("Err returning instance\n");
 477
 478         /* Free resources */
 479         s5p_mfc_hw_call(dev->mfc_ops, release_codec_buffers, ctx);
 480         s5p_mfc_hw_call(dev->mfc_ops, release_instance_buffer, ctx);
 481         if (ctx->type == MFCINST_DECODER)
 482                 s5p_mfc_hw_call(dev->mfc_ops, release_dec_desc_buffer, ctx);
 483
 484         ctx->inst_no = MFC_NO_INSTANCE_SET;
 485         ctx->state = MFCINST_FREE;
 486 }