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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / media / platform / s5p-mfc / s5p_mfc_opr_v6.c
blob7c629be432052d4be1e867ca96eebf208812bd23
1 /*
2 * drivers/media/platform/s5p-mfc/s5p_mfc_opr_v6.c
3 *
4 * Samsung MFC (Multi Function Codec - FIMV) driver
5 * This file contains hw related functions.
6 *
7 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
8 * http://www.samsung.com/
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15 #undef DEBUG
16
17 #include <linux/delay.h>
18 #include <linux/mm.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/firmware.h>
22 #include <linux/err.h>
23 #include <linux/sched.h>
24 #include <linux/dma-mapping.h>
25
26 #include <asm/cacheflush.h>
27
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_cmd.h"
30 #include "s5p_mfc_intr.h"
31 #include "s5p_mfc_pm.h"
32 #include "s5p_mfc_debug.h"
33 #include "s5p_mfc_opr.h"
34 #include "s5p_mfc_opr_v6.h"
35
36 /* #define S5P_MFC_DEBUG_REGWRITE */
37 #ifdef S5P_MFC_DEBUG_REGWRITE
38 #undef writel
39 #define writel(v, r) \
40 do { \
41 pr_err("MFCWRITE(%p): %08x\n", r, (unsigned int)v); \
42 __raw_writel(v, r); \
43 } while (0)
44 #endif /* S5P_MFC_DEBUG_REGWRITE */
45
46 #define IS_MFCV6_V2(dev) (!IS_MFCV7_PLUS(dev) && dev->fw_ver == MFC_FW_V2)
47
48 /* Allocate temporary buffers for decoding */
49 static int s5p_mfc_alloc_dec_temp_buffers_v6(struct s5p_mfc_ctx *ctx)
50 {
51 /* NOP */
52
53 return 0;
54 }
55
56 /* Release temproary buffers for decoding */
57 static void s5p_mfc_release_dec_desc_buffer_v6(struct s5p_mfc_ctx *ctx)
58 {
59 /* NOP */
60 }
61
62 /* Allocate codec buffers */
63 static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
64 {
65 struct s5p_mfc_dev *dev = ctx->dev;
66 unsigned int mb_width, mb_height;
67 unsigned int lcu_width = 0, lcu_height = 0;
68 int ret;
69
70 mb_width = MB_WIDTH(ctx->img_width);
71 mb_height = MB_HEIGHT(ctx->img_height);
72
73 if (ctx->type == MFCINST_DECODER) {
74 mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n",
75 ctx->luma_size, ctx->chroma_size, ctx->mv_size);
76 mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count);
77 } else if (ctx->type == MFCINST_ENCODER) {
78 if (IS_MFCV10(dev)) {
79 ctx->tmv_buffer_size = 0;
80 } else if (IS_MFCV8_PLUS(dev))
81 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
82 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height),
83 S5P_FIMV_TMV_BUFFER_ALIGN_V6);
84 else
85 ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 *
86 ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height),
87 S5P_FIMV_TMV_BUFFER_ALIGN_V6);
88 if (IS_MFCV10(dev)) {
89 lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width);
90 lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height);
91 if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) {
92 ctx->luma_dpb_size =
93 ALIGN((mb_width * 16), 64)
94 * ALIGN((mb_height * 16), 32)
95 + 64;
96 ctx->chroma_dpb_size =
97 ALIGN((mb_width * 16), 64)
98 * (mb_height * 8)
99 + 64;
100 } else {
101 ctx->luma_dpb_size =
102 ALIGN((lcu_width * 32), 64)
103 * ALIGN((lcu_height * 32), 32)
104 + 64;
105 ctx->chroma_dpb_size =
106 ALIGN((lcu_width * 32), 64)
107 * (lcu_height * 16)
108 + 64;
109 }
110 } else {
111 ctx->luma_dpb_size = ALIGN((mb_width * mb_height) *
112 S5P_FIMV_LUMA_MB_TO_PIXEL_V6,
113 S5P_FIMV_LUMA_DPB_BUFFER_ALIGN_V6);
114 ctx->chroma_dpb_size = ALIGN((mb_width * mb_height) *
115 S5P_FIMV_CHROMA_MB_TO_PIXEL_V6,
116 S5P_FIMV_CHROMA_DPB_BUFFER_ALIGN_V6);
117 }
118 if (IS_MFCV8_PLUS(dev))
119 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V8(
120 ctx->img_width, ctx->img_height,
121 mb_width, mb_height),
122 S5P_FIMV_ME_BUFFER_ALIGN_V6);
123 else
124 ctx->me_buffer_size = ALIGN(S5P_FIMV_ME_BUFFER_SIZE_V6(
125 ctx->img_width, ctx->img_height,
126 mb_width, mb_height),
127 S5P_FIMV_ME_BUFFER_ALIGN_V6);
128
129 mfc_debug(2, "recon luma size: %zu chroma size: %zu\n",
130 ctx->luma_dpb_size, ctx->chroma_dpb_size);
131 } else {
132 return -EINVAL;
133 }
134
135 /* Codecs have different memory requirements */
136 switch (ctx->codec_mode) {
137 case S5P_MFC_CODEC_H264_DEC:
138 case S5P_MFC_CODEC_H264_MVC_DEC:
139 if (IS_MFCV10(dev))
140 mfc_debug(2, "Use min scratch buffer size\n");
141 else if (IS_MFCV8_PLUS(dev))
142 ctx->scratch_buf_size =
143 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V8(
144 mb_width,
145 mb_height);
146 else
147 ctx->scratch_buf_size =
148 S5P_FIMV_SCRATCH_BUF_SIZE_H264_DEC_V6(
149 mb_width,
150 mb_height);
151 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
152 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
153 ctx->bank1.size =
154 ctx->scratch_buf_size +
155 (ctx->mv_count * ctx->mv_size);
156 break;
157 case S5P_MFC_CODEC_MPEG4_DEC:
158 if (IS_MFCV10(dev))
159 mfc_debug(2, "Use min scratch buffer size\n");
160 else if (IS_MFCV7_PLUS(dev)) {
161 ctx->scratch_buf_size =
162 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V7(
163 mb_width,
164 mb_height);
165 } else {
166 ctx->scratch_buf_size =
167 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_DEC_V6(
168 mb_width,
169 mb_height);
170 }
171
172 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
173 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
174 ctx->bank1.size = ctx->scratch_buf_size;
175 break;
176 case S5P_MFC_CODEC_VC1RCV_DEC:
177 case S5P_MFC_CODEC_VC1_DEC:
178 if (IS_MFCV10(dev))
179 mfc_debug(2, "Use min scratch buffer size\n");
180 else
181 ctx->scratch_buf_size =
182 S5P_FIMV_SCRATCH_BUF_SIZE_VC1_DEC_V6(
183 mb_width,
184 mb_height);
185
186 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
187 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
188 ctx->bank1.size = ctx->scratch_buf_size;
189 break;
190 case S5P_MFC_CODEC_MPEG2_DEC:
191 ctx->bank1.size = 0;
192 ctx->bank2.size = 0;
193 break;
194 case S5P_MFC_CODEC_H263_DEC:
195 if (IS_MFCV10(dev))
196 mfc_debug(2, "Use min scratch buffer size\n");
197 else
198 ctx->scratch_buf_size =
199 S5P_FIMV_SCRATCH_BUF_SIZE_H263_DEC_V6(
200 mb_width,
201 mb_height);
202 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
203 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
204 ctx->bank1.size = ctx->scratch_buf_size;
205 break;
206 case S5P_MFC_CODEC_VP8_DEC:
207 if (IS_MFCV10(dev))
208 mfc_debug(2, "Use min scratch buffer size\n");
209 else if (IS_MFCV8_PLUS(dev))
210 ctx->scratch_buf_size =
211 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V8(
212 mb_width,
213 mb_height);
214 else
215 ctx->scratch_buf_size =
216 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_DEC_V6(
217 mb_width,
218 mb_height);
219 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
220 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
221 ctx->bank1.size = ctx->scratch_buf_size;
222 break;
223 case S5P_MFC_CODEC_HEVC_DEC:
224 mfc_debug(2, "Use min scratch buffer size\n");
225 ctx->bank1.size =
226 ctx->scratch_buf_size +
227 (ctx->mv_count * ctx->mv_size);
228 break;
229 case S5P_MFC_CODEC_VP9_DEC:
230 mfc_debug(2, "Use min scratch buffer size\n");
231 ctx->bank1.size =
232 ctx->scratch_buf_size +
233 DEC_VP9_STATIC_BUFFER_SIZE;
234 break;
235 case S5P_MFC_CODEC_H264_ENC:
236 if (IS_MFCV10(dev)) {
237 mfc_debug(2, "Use min scratch buffer size\n");
238 ctx->me_buffer_size =
239 ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16);
240 } else if (IS_MFCV8_PLUS(dev))
241 ctx->scratch_buf_size =
242 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V8(
243 mb_width,
244 mb_height);
245 else
246 ctx->scratch_buf_size =
247 S5P_FIMV_SCRATCH_BUF_SIZE_H264_ENC_V6(
248 mb_width,
249 mb_height);
250 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
251 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
252 ctx->bank1.size =
253 ctx->scratch_buf_size + ctx->tmv_buffer_size +
254 (ctx->pb_count * (ctx->luma_dpb_size +
255 ctx->chroma_dpb_size + ctx->me_buffer_size));
256 ctx->bank2.size = 0;
257 break;
258 case S5P_MFC_CODEC_MPEG4_ENC:
259 case S5P_MFC_CODEC_H263_ENC:
260 if (IS_MFCV10(dev)) {
261 mfc_debug(2, "Use min scratch buffer size\n");
262 ctx->me_buffer_size =
263 ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width,
264 mb_height), 16);
265 } else
266 ctx->scratch_buf_size =
267 S5P_FIMV_SCRATCH_BUF_SIZE_MPEG4_ENC_V6(
268 mb_width,
269 mb_height);
270 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
271 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
272 ctx->bank1.size =
273 ctx->scratch_buf_size + ctx->tmv_buffer_size +
274 (ctx->pb_count * (ctx->luma_dpb_size +
275 ctx->chroma_dpb_size + ctx->me_buffer_size));
276 ctx->bank2.size = 0;
277 break;
278 case S5P_MFC_CODEC_VP8_ENC:
279 if (IS_MFCV10(dev)) {
280 mfc_debug(2, "Use min scratch buffer size\n");
281 ctx->me_buffer_size =
282 ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height),
283 16);
284 } else if (IS_MFCV8_PLUS(dev))
285 ctx->scratch_buf_size =
286 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V8(
287 mb_width,
288 mb_height);
289 else
290 ctx->scratch_buf_size =
291 S5P_FIMV_SCRATCH_BUF_SIZE_VP8_ENC_V7(
292 mb_width,
293 mb_height);
294 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size,
295 S5P_FIMV_SCRATCH_BUFFER_ALIGN_V6);
296 ctx->bank1.size =
297 ctx->scratch_buf_size + ctx->tmv_buffer_size +
298 (ctx->pb_count * (ctx->luma_dpb_size +
299 ctx->chroma_dpb_size + ctx->me_buffer_size));
300 ctx->bank2.size = 0;
301 break;
302 case S5P_MFC_CODEC_HEVC_ENC:
303 mfc_debug(2, "Use min scratch buffer size\n");
304 ctx->me_buffer_size =
305 ALIGN(ENC_V100_HEVC_ME_SIZE(lcu_width, lcu_height), 16);
306 ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256);
307 ctx->bank1.size =
308 ctx->scratch_buf_size + ctx->tmv_buffer_size +
309 (ctx->pb_count * (ctx->luma_dpb_size +
310 ctx->chroma_dpb_size + ctx->me_buffer_size));
311 ctx->bank2.size = 0;
312 break;
313 default:
314 break;
315 }
316
317 /* Allocate only if memory from bank 1 is necessary */
318 if (ctx->bank1.size > 0) {
319 ret = s5p_mfc_alloc_generic_buf(dev, BANK_L_CTX, &ctx->bank1);
320 if (ret) {
321 mfc_err("Failed to allocate Bank1 memory\n");
322 return ret;
323 }
324 BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1));
325 }
326 return 0;
327 }
328
329 /* Release buffers allocated for codec */
330 static void s5p_mfc_release_codec_buffers_v6(struct s5p_mfc_ctx *ctx)
331 {
332 s5p_mfc_release_generic_buf(ctx->dev, &ctx->bank1);
333 }
334
335 /* Allocate memory for instance data buffer */
336 static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
337 {
338 struct s5p_mfc_dev *dev = ctx->dev;
339 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
340 int ret;
341
342 mfc_debug_enter();
343
344 switch (ctx->codec_mode) {
345 case S5P_MFC_CODEC_H264_DEC:
346 case S5P_MFC_CODEC_H264_MVC_DEC:
347 case S5P_MFC_CODEC_HEVC_DEC:
348 ctx->ctx.size = buf_size->h264_dec_ctx;
349 break;
350 case S5P_MFC_CODEC_MPEG4_DEC:
351 case S5P_MFC_CODEC_H263_DEC:
352 case S5P_MFC_CODEC_VC1RCV_DEC:
353 case S5P_MFC_CODEC_VC1_DEC:
354 case S5P_MFC_CODEC_MPEG2_DEC:
355 case S5P_MFC_CODEC_VP8_DEC:
356 case S5P_MFC_CODEC_VP9_DEC:
357 ctx->ctx.size = buf_size->other_dec_ctx;
358 break;
359 case S5P_MFC_CODEC_H264_ENC:
360 ctx->ctx.size = buf_size->h264_enc_ctx;
361 break;
362 case S5P_MFC_CODEC_HEVC_ENC:
363 ctx->ctx.size = buf_size->hevc_enc_ctx;
364 break;
365 case S5P_MFC_CODEC_MPEG4_ENC:
366 case S5P_MFC_CODEC_H263_ENC:
367 case S5P_MFC_CODEC_VP8_ENC:
368 ctx->ctx.size = buf_size->other_enc_ctx;
369 break;
370 default:
371 ctx->ctx.size = 0;
372 mfc_err("Codec type(%d) should be checked!\n", ctx->codec_mode);
373 break;
374 }
375
376 ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &ctx->ctx);
377 if (ret) {
378 mfc_err("Failed to allocate instance buffer\n");
379 return ret;
380 }
381
382 memset(ctx->ctx.virt, 0, ctx->ctx.size);
383 wmb();
384
385 mfc_debug_leave();
386
387 return 0;
388 }
389
390 /* Release instance buffer */
391 static void s5p_mfc_release_instance_buffer_v6(struct s5p_mfc_ctx *ctx)
392 {
393 s5p_mfc_release_priv_buf(ctx->dev, &ctx->ctx);
394 }
395
396 /* Allocate context buffers for SYS_INIT */
397 static int s5p_mfc_alloc_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
398 {
399 struct s5p_mfc_buf_size_v6 *buf_size = dev->variant->buf_size->priv;
400 int ret;
401
402 mfc_debug_enter();
403
404 dev->ctx_buf.size = buf_size->dev_ctx;
405 ret = s5p_mfc_alloc_priv_buf(dev, BANK_L_CTX, &dev->ctx_buf);
406 if (ret) {
407 mfc_err("Failed to allocate device context buffer\n");
408 return ret;
409 }
410
411 memset(dev->ctx_buf.virt, 0, buf_size->dev_ctx);
412 wmb();
413
414 mfc_debug_leave();
415
416 return 0;
417 }
418
419 /* Release context buffers for SYS_INIT */
420 static void s5p_mfc_release_dev_context_buffer_v6(struct s5p_mfc_dev *dev)
421 {
422 s5p_mfc_release_priv_buf(dev, &dev->ctx_buf);
423 }
424
425 static int calc_plane(int width, int height)
426 {
427 int mbX, mbY;
428
429 mbX = DIV_ROUND_UP(width, S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
430 mbY = DIV_ROUND_UP(height, S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6);
431
432 if (width * height < S5P_FIMV_MAX_FRAME_SIZE_V6)
433 mbY = (mbY + 1) / 2 * 2;
434
435 return (mbX * S5P_FIMV_NUM_PIXELS_IN_MB_COL_V6) *
436 (mbY * S5P_FIMV_NUM_PIXELS_IN_MB_ROW_V6);
437 }
438
439 static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx)
440 {
441 struct s5p_mfc_dev *dev = ctx->dev;
442 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN_V6);
443 ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN_V6);
444 mfc_debug(2, "SEQ Done: Movie dimensions %dx%d,\n"
445 "buffer dimensions: %dx%d\n", ctx->img_width,
446 ctx->img_height, ctx->buf_width, ctx->buf_height);
447
448 ctx->luma_size = calc_plane(ctx->img_width, ctx->img_height);
449 ctx->chroma_size = calc_plane(ctx->img_width, (ctx->img_height >> 1));
450 if (IS_MFCV8_PLUS(ctx->dev)) {
451 /* MFCv8 needs additional 64 bytes for luma,chroma dpb*/
452 ctx->luma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
453 ctx->chroma_size += S5P_FIMV_D_ALIGN_PLANE_SIZE_V8;
454 }
455
456 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
457 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) {
458 if (IS_MFCV10(dev)) {
459 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width,
460 ctx->img_height);
461 } else {
462 ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V6(ctx->img_width,
463 ctx->img_height);
464 }
465 } else if (ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
466 ctx->mv_size = s5p_mfc_dec_hevc_mv_size(ctx->img_width,
467 ctx->img_height);
468 ctx->mv_size = ALIGN(ctx->mv_size, 32);
469 } else {
470 ctx->mv_size = 0;
471 }
472 }
473
474 static void s5p_mfc_enc_calc_src_size_v6(struct s5p_mfc_ctx *ctx)
475 {
476 unsigned int mb_width, mb_height;
477
478 mb_width = MB_WIDTH(ctx->img_width);
479 mb_height = MB_HEIGHT(ctx->img_height);
480
481 ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN_V6);
482 ctx->luma_size = ALIGN((mb_width * mb_height) * 256, 256);
483 ctx->chroma_size = ALIGN((mb_width * mb_height) * 128, 256);
484
485 /* MFCv7 needs pad bytes for Luma and Chroma */
486 if (IS_MFCV7_PLUS(ctx->dev)) {
487 ctx->luma_size += MFC_LUMA_PAD_BYTES_V7;
488 ctx->chroma_size += MFC_CHROMA_PAD_BYTES_V7;
489 }
490 }
491
492 /* Set registers for decoding stream buffer */
493 static int s5p_mfc_set_dec_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
494 int buf_addr, unsigned int start_num_byte,
495 unsigned int strm_size)
496 {
497 struct s5p_mfc_dev *dev = ctx->dev;
498 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
499 struct s5p_mfc_buf_size *buf_size = dev->variant->buf_size;
500
501 mfc_debug_enter();
502 mfc_debug(2, "inst_no: %d, buf_addr: 0x%08x,\n"
503 "buf_size: 0x%08x (%d)\n",
504 ctx->inst_no, buf_addr, strm_size, strm_size);
505 writel(strm_size, mfc_regs->d_stream_data_size);
506 writel(buf_addr, mfc_regs->d_cpb_buffer_addr);
507 writel(buf_size->cpb, mfc_regs->d_cpb_buffer_size);
508 writel(start_num_byte, mfc_regs->d_cpb_buffer_offset);
509
510 mfc_debug_leave();
511 return 0;
512 }
513
514 /* Set decoding frame buffer */
515 static int s5p_mfc_set_dec_frame_buffer_v6(struct s5p_mfc_ctx *ctx)
516 {
517 unsigned int frame_size, i;
518 unsigned int frame_size_ch, frame_size_mv;
519 struct s5p_mfc_dev *dev = ctx->dev;
520 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
521 size_t buf_addr1;
522 int buf_size1;
523 int align_gap;
524
525 buf_addr1 = ctx->bank1.dma;
526 buf_size1 = ctx->bank1.size;
527
528 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
529 mfc_debug(2, "Total DPB COUNT: %d\n", ctx->total_dpb_count);
530 mfc_debug(2, "Setting display delay to %d\n", ctx->display_delay);
531
532 writel(ctx->total_dpb_count, mfc_regs->d_num_dpb);
533 writel(ctx->luma_size, mfc_regs->d_first_plane_dpb_size);
534 writel(ctx->chroma_size, mfc_regs->d_second_plane_dpb_size);
535
536 writel(buf_addr1, mfc_regs->d_scratch_buffer_addr);
537 writel(ctx->scratch_buf_size, mfc_regs->d_scratch_buffer_size);
538
539 if (IS_MFCV8_PLUS(dev)) {
540 writel(ctx->img_width,
541 mfc_regs->d_first_plane_dpb_stride_size);
542 writel(ctx->img_width,
543 mfc_regs->d_second_plane_dpb_stride_size);
544 }
545
546 buf_addr1 += ctx->scratch_buf_size;
547 buf_size1 -= ctx->scratch_buf_size;
548
549 if (ctx->codec_mode == S5P_FIMV_CODEC_H264_DEC ||
550 ctx->codec_mode == S5P_FIMV_CODEC_H264_MVC_DEC ||
551 ctx->codec_mode == S5P_FIMV_CODEC_HEVC_DEC) {
552 writel(ctx->mv_size, mfc_regs->d_mv_buffer_size);
553 writel(ctx->mv_count, mfc_regs->d_num_mv);
554 }
555
556 frame_size = ctx->luma_size;
557 frame_size_ch = ctx->chroma_size;
558 frame_size_mv = ctx->mv_size;
559 mfc_debug(2, "Frame size: %d ch: %d mv: %d\n",
560 frame_size, frame_size_ch, frame_size_mv);
561
562 for (i = 0; i < ctx->total_dpb_count; i++) {
563 /* Bank2 */
564 mfc_debug(2, "Luma %d: %zx\n", i,
565 ctx->dst_bufs[i].cookie.raw.luma);
566 writel(ctx->dst_bufs[i].cookie.raw.luma,
567 mfc_regs->d_first_plane_dpb + i * 4);
568 mfc_debug(2, "\tChroma %d: %zx\n", i,
569 ctx->dst_bufs[i].cookie.raw.chroma);
570 writel(ctx->dst_bufs[i].cookie.raw.chroma,
571 mfc_regs->d_second_plane_dpb + i * 4);
572 }
573 if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
574 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC ||
575 ctx->codec_mode == S5P_MFC_CODEC_HEVC_DEC) {
576 for (i = 0; i < ctx->mv_count; i++) {
577 /* To test alignment */
578 align_gap = buf_addr1;
579 buf_addr1 = ALIGN(buf_addr1, 16);
580 align_gap = buf_addr1 - align_gap;
581 buf_size1 -= align_gap;
582
583 mfc_debug(2, "\tBuf1: %zx, size: %d\n",
584 buf_addr1, buf_size1);
585 writel(buf_addr1, mfc_regs->d_mv_buffer + i * 4);
586 buf_addr1 += frame_size_mv;
587 buf_size1 -= frame_size_mv;
588 }
589 }
590 if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_DEC) {
591 writel(buf_addr1, mfc_regs->d_static_buffer_addr);
592 writel(DEC_VP9_STATIC_BUFFER_SIZE,
593 mfc_regs->d_static_buffer_size);
594 buf_addr1 += DEC_VP9_STATIC_BUFFER_SIZE;
595 buf_size1 -= DEC_VP9_STATIC_BUFFER_SIZE;
596 }
597
598 mfc_debug(2, "Buf1: %zx, buf_size1: %d (frames %d)\n",
599 buf_addr1, buf_size1, ctx->total_dpb_count);
600 if (buf_size1 < 0) {
601 mfc_debug(2, "Not enough memory has been allocated.\n");
602 return -ENOMEM;
603 }
604
605 writel(ctx->inst_no, mfc_regs->instance_id);
606 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
607 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
608
609 mfc_debug(2, "After setting buffers.\n");
610 return 0;
611 }
612
613 /* Set registers for encoding stream buffer */
614 static int s5p_mfc_set_enc_stream_buffer_v6(struct s5p_mfc_ctx *ctx,
615 unsigned long addr, unsigned int size)
616 {
617 struct s5p_mfc_dev *dev = ctx->dev;
618 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
619
620 writel(addr, mfc_regs->e_stream_buffer_addr); /* 16B align */
621 writel(size, mfc_regs->e_stream_buffer_size);
622
623 mfc_debug(2, "stream buf addr: 0x%08lx, size: 0x%x\n",
624 addr, size);
625
626 return 0;
627 }
628
629 static void s5p_mfc_set_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
630 unsigned long y_addr, unsigned long c_addr)
631 {
632 struct s5p_mfc_dev *dev = ctx->dev;
633 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
634
635 writel(y_addr, mfc_regs->e_source_first_plane_addr);
636 writel(c_addr, mfc_regs->e_source_second_plane_addr);
637
638 mfc_debug(2, "enc src y buf addr: 0x%08lx\n", y_addr);
639 mfc_debug(2, "enc src c buf addr: 0x%08lx\n", c_addr);
640 }
641
642 static void s5p_mfc_get_enc_frame_buffer_v6(struct s5p_mfc_ctx *ctx,
643 unsigned long *y_addr, unsigned long *c_addr)
644 {
645 struct s5p_mfc_dev *dev = ctx->dev;
646 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
647 unsigned long enc_recon_y_addr, enc_recon_c_addr;
648
649 *y_addr = readl(mfc_regs->e_encoded_source_first_plane_addr);
650 *c_addr = readl(mfc_regs->e_encoded_source_second_plane_addr);
651
652 enc_recon_y_addr = readl(mfc_regs->e_recon_luma_dpb_addr);
653 enc_recon_c_addr = readl(mfc_regs->e_recon_chroma_dpb_addr);
654
655 mfc_debug(2, "recon y addr: 0x%08lx y_addr: 0x%08lx\n", enc_recon_y_addr, *y_addr);
656 mfc_debug(2, "recon c addr: 0x%08lx\n", enc_recon_c_addr);
657 }
658
659 /* Set encoding ref & codec buffer */
660 static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx)
661 {
662 struct s5p_mfc_dev *dev = ctx->dev;
663 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
664 size_t buf_addr1;
665 int i, buf_size1;
666
667 mfc_debug_enter();
668
669 buf_addr1 = ctx->bank1.dma;
670 buf_size1 = ctx->bank1.size;
671
672 mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1);
673
674 if (IS_MFCV10(dev)) {
675 /* start address of per buffer is aligned */
676 for (i = 0; i < ctx->pb_count; i++) {
677 writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
678 buf_addr1 += ctx->luma_dpb_size;
679 buf_size1 -= ctx->luma_dpb_size;
680 }
681 for (i = 0; i < ctx->pb_count; i++) {
682 writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
683 buf_addr1 += ctx->chroma_dpb_size;
684 buf_size1 -= ctx->chroma_dpb_size;
685 }
686 for (i = 0; i < ctx->pb_count; i++) {
687 writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
688 buf_addr1 += ctx->me_buffer_size;
689 buf_size1 -= ctx->me_buffer_size;
690 }
691 } else {
692 for (i = 0; i < ctx->pb_count; i++) {
693 writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i));
694 buf_addr1 += ctx->luma_dpb_size;
695 writel(buf_addr1, mfc_regs->e_chroma_dpb + (4 * i));
696 buf_addr1 += ctx->chroma_dpb_size;
697 writel(buf_addr1, mfc_regs->e_me_buffer + (4 * i));
698 buf_addr1 += ctx->me_buffer_size;
699 buf_size1 -= (ctx->luma_dpb_size + ctx->chroma_dpb_size
700 + ctx->me_buffer_size);
701 }
702 }
703
704 writel(buf_addr1, mfc_regs->e_scratch_buffer_addr);
705 writel(ctx->scratch_buf_size, mfc_regs->e_scratch_buffer_size);
706 buf_addr1 += ctx->scratch_buf_size;
707 buf_size1 -= ctx->scratch_buf_size;
708
709 writel(buf_addr1, mfc_regs->e_tmv_buffer0);
710 buf_addr1 += ctx->tmv_buffer_size >> 1;
711 writel(buf_addr1, mfc_regs->e_tmv_buffer1);
712 buf_addr1 += ctx->tmv_buffer_size >> 1;
713 buf_size1 -= ctx->tmv_buffer_size;
714
715 mfc_debug(2, "Buf1: %zu, buf_size1: %d (ref frames %d)\n",
716 buf_addr1, buf_size1, ctx->pb_count);
717 if (buf_size1 < 0) {
718 mfc_debug(2, "Not enough memory has been allocated.\n");
719 return -ENOMEM;
720 }
721
722 writel(ctx->inst_no, mfc_regs->instance_id);
723 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
724 S5P_FIMV_CH_INIT_BUFS_V6, NULL);
725
726 mfc_debug_leave();
727
728 return 0;
729 }
730
731 static int s5p_mfc_set_slice_mode(struct s5p_mfc_ctx *ctx)
732 {
733 struct s5p_mfc_dev *dev = ctx->dev;
734 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
735
736 /* multi-slice control */
737 /* multi-slice MB number or bit size */
738 writel(ctx->slice_mode, mfc_regs->e_mslice_mode);
739 if (ctx->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
740 writel(ctx->slice_size.mb, mfc_regs->e_mslice_size_mb);
741 } else if (ctx->slice_mode ==
742 V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
743 writel(ctx->slice_size.bits, mfc_regs->e_mslice_size_bits);
744 } else {
745 writel(0x0, mfc_regs->e_mslice_size_mb);
746 writel(0x0, mfc_regs->e_mslice_size_bits);
747 }
748
749 return 0;
750 }
751
752 static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx)
753 {
754 struct s5p_mfc_dev *dev = ctx->dev;
755 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
756 struct s5p_mfc_enc_params *p = &ctx->enc_params;
757 unsigned int reg = 0;
758
759 mfc_debug_enter();
760
761 /* width */
762 writel(ctx->img_width, mfc_regs->e_frame_width); /* 16 align */
763 /* height */
764 writel(ctx->img_height, mfc_regs->e_frame_height); /* 16 align */
765
766 /* cropped width */
767 writel(ctx->img_width, mfc_regs->e_cropped_frame_width);
768 /* cropped height */
769 writel(ctx->img_height, mfc_regs->e_cropped_frame_height);
770 /* cropped offset */
771 writel(0x0, mfc_regs->e_frame_crop_offset);
772
773 /* pictype : IDR period */
774 reg = 0;
775 reg |= p->gop_size & 0xFFFF;
776 writel(reg, mfc_regs->e_gop_config);
777
778 /* multi-slice control */
779 /* multi-slice MB number or bit size */
780 ctx->slice_mode = p->slice_mode;
781 reg = 0;
782 if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) {
783 reg |= (0x1 << 3);
784 writel(reg, mfc_regs->e_enc_options);
785 ctx->slice_size.mb = p->slice_mb;
786 } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) {
787 reg |= (0x1 << 3);
788 writel(reg, mfc_regs->e_enc_options);
789 ctx->slice_size.bits = p->slice_bit;
790 } else {
791 reg &= ~(0x1 << 3);
792 writel(reg, mfc_regs->e_enc_options);
793 }
794
795 s5p_mfc_set_slice_mode(ctx);
796
797 /* cyclic intra refresh */
798 writel(p->intra_refresh_mb, mfc_regs->e_ir_size);
799 reg = readl(mfc_regs->e_enc_options);
800 if (p->intra_refresh_mb == 0)
801 reg &= ~(0x1 << 4);
802 else
803 reg |= (0x1 << 4);
804 writel(reg, mfc_regs->e_enc_options);
805
806 /* 'NON_REFERENCE_STORE_ENABLE' for debugging */
807 reg = readl(mfc_regs->e_enc_options);
808 reg &= ~(0x1 << 9);
809 writel(reg, mfc_regs->e_enc_options);
810
811 /* memory structure cur. frame */
812 if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) {
813 /* 0: Linear, 1: 2D tiled*/
814 reg = readl(mfc_regs->e_enc_options);
815 reg &= ~(0x1 << 7);
816 writel(reg, mfc_regs->e_enc_options);
817 /* 0: NV12(CbCr), 1: NV21(CrCb) */
818 writel(0x0, mfc_regs->pixel_format);
819 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV21M) {
820 /* 0: Linear, 1: 2D tiled*/
821 reg = readl(mfc_regs->e_enc_options);
822 reg &= ~(0x1 << 7);
823 writel(reg, mfc_regs->e_enc_options);
824 /* 0: NV12(CbCr), 1: NV21(CrCb) */
825 writel(0x1, mfc_regs->pixel_format);
826 } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16) {
827 /* 0: Linear, 1: 2D tiled*/
828 reg = readl(mfc_regs->e_enc_options);
829 reg |= (0x1 << 7);
830 writel(reg, mfc_regs->e_enc_options);
831 /* 0: NV12(CbCr), 1: NV21(CrCb) */
832 writel(0x0, mfc_regs->pixel_format);
833 }
834
835 /* memory structure recon. frame */
836 /* 0: Linear, 1: 2D tiled */
837 reg = readl(mfc_regs->e_enc_options);
838 reg |= (0x1 << 8);
839 writel(reg, mfc_regs->e_enc_options);
840
841 /* padding control & value */
842 writel(0x0, mfc_regs->e_padding_ctrl);
843 if (p->pad) {
844 reg = 0;
845 /** enable */
846 reg |= (1 << 31);
847 /** cr value */
848 reg |= ((p->pad_cr & 0xFF) << 16);
849 /** cb value */
850 reg |= ((p->pad_cb & 0xFF) << 8);
851 /** y value */
852 reg |= p->pad_luma & 0xFF;
853 writel(reg, mfc_regs->e_padding_ctrl);
854 }
855
856 /* rate control config. */
857 reg = 0;
858 /* frame-level rate control */
859 reg |= ((p->rc_frame & 0x1) << 9);
860 writel(reg, mfc_regs->e_rc_config);
861
862 /* bit rate */
863 if (p->rc_frame)
864 writel(p->rc_bitrate,
865 mfc_regs->e_rc_bit_rate);
866 else
867 writel(1, mfc_regs->e_rc_bit_rate);
868
869 /* reaction coefficient */
870 if (p->rc_frame) {
871 if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */
872 writel(1, mfc_regs->e_rc_mode);
873 else /* loose CBR */
874 writel(2, mfc_regs->e_rc_mode);
875 }
876
877 /* seq header ctrl */
878 reg = readl(mfc_regs->e_enc_options);
879 reg &= ~(0x1 << 2);
880 reg |= ((p->seq_hdr_mode & 0x1) << 2);
881
882 /* frame skip mode */
883 reg &= ~(0x3);
884 reg |= (p->frame_skip_mode & 0x3);
885 writel(reg, mfc_regs->e_enc_options);
886
887 /* 'DROP_CONTROL_ENABLE', disable */
888 reg = readl(mfc_regs->e_rc_config);
889 reg &= ~(0x1 << 10);
890 writel(reg, mfc_regs->e_rc_config);
891
892 /* setting for MV range [16, 256] */
893 reg = (p->mv_h_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
894 writel(reg, mfc_regs->e_mv_hor_range);
895
896 reg = (p->mv_v_range & S5P_FIMV_E_MV_RANGE_V6_MASK);
897 writel(reg, mfc_regs->e_mv_ver_range);
898
899 writel(0x0, mfc_regs->e_frame_insertion);
900 writel(0x0, mfc_regs->e_roi_buffer_addr);
901 writel(0x0, mfc_regs->e_param_change);
902 writel(0x0, mfc_regs->e_rc_roi_ctrl);
903 writel(0x0, mfc_regs->e_picture_tag);
904
905 writel(0x0, mfc_regs->e_bit_count_enable);
906 writel(0x0, mfc_regs->e_max_bit_count);
907 writel(0x0, mfc_regs->e_min_bit_count);
908
909 writel(0x0, mfc_regs->e_metadata_buffer_addr);
910 writel(0x0, mfc_regs->e_metadata_buffer_size);
911
912 mfc_debug_leave();
913
914 return 0;
915 }
916
917 static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx)
918 {
919 struct s5p_mfc_dev *dev = ctx->dev;
920 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
921 struct s5p_mfc_enc_params *p = &ctx->enc_params;
922 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
923 unsigned int reg = 0;
924 int i;
925
926 mfc_debug_enter();
927
928 s5p_mfc_set_enc_params(ctx);
929
930 /* pictype : number of B */
931 reg = readl(mfc_regs->e_gop_config);
932 reg &= ~(0x3 << 16);
933 reg |= ((p->num_b_frame & 0x3) << 16);
934 writel(reg, mfc_regs->e_gop_config);
935
936 /* profile & level */
937 reg = 0;
938 /** level */
939 reg |= ((p_h264->level & 0xFF) << 8);
940 /** profile - 0 ~ 3 */
941 reg |= p_h264->profile & 0x3F;
942 writel(reg, mfc_regs->e_picture_profile);
943
944 /* rate control config. */
945 reg = readl(mfc_regs->e_rc_config);
946 /** macroblock level rate control */
947 reg &= ~(0x1 << 8);
948 reg |= ((p->rc_mb & 0x1) << 8);
949 writel(reg, mfc_regs->e_rc_config);
950
951 /** frame QP */
952 reg &= ~(0x3F);
953 reg |= p_h264->rc_frame_qp & 0x3F;
954 writel(reg, mfc_regs->e_rc_config);
955
956 /* max & min value of QP */
957 reg = 0;
958 /** max QP */
959 reg |= ((p_h264->rc_max_qp & 0x3F) << 8);
960 /** min QP */
961 reg |= p_h264->rc_min_qp & 0x3F;
962 writel(reg, mfc_regs->e_rc_qp_bound);
963
964 /* other QPs */
965 writel(0x0, mfc_regs->e_fixed_picture_qp);
966 if (!p->rc_frame && !p->rc_mb) {
967 reg = 0;
968 reg |= ((p_h264->rc_b_frame_qp & 0x3F) << 16);
969 reg |= ((p_h264->rc_p_frame_qp & 0x3F) << 8);
970 reg |= p_h264->rc_frame_qp & 0x3F;
971 writel(reg, mfc_regs->e_fixed_picture_qp);
972 }
973
974 /* frame rate */
975 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
976 reg = 0;
977 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
978 reg |= p->rc_framerate_denom & 0xFFFF;
979 writel(reg, mfc_regs->e_rc_frame_rate);
980 }
981
982 /* vbv buffer size */
983 if (p->frame_skip_mode ==
984 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
985 writel(p_h264->cpb_size & 0xFFFF,
986 mfc_regs->e_vbv_buffer_size);
987
988 if (p->rc_frame)
989 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
990 }
991
992 /* interlace */
993 reg = 0;
994 reg |= ((p_h264->interlace & 0x1) << 3);
995 writel(reg, mfc_regs->e_h264_options);
996
997 /* height */
998 if (p_h264->interlace) {
999 writel(ctx->img_height >> 1,
1000 mfc_regs->e_frame_height); /* 32 align */
1001 /* cropped height */
1002 writel(ctx->img_height >> 1,
1003 mfc_regs->e_cropped_frame_height);
1004 }
1005
1006 /* loop filter ctrl */
1007 reg = readl(mfc_regs->e_h264_options);
1008 reg &= ~(0x3 << 1);
1009 reg |= ((p_h264->loop_filter_mode & 0x3) << 1);
1010 writel(reg, mfc_regs->e_h264_options);
1011
1012 /* loopfilter alpha offset */
1013 if (p_h264->loop_filter_alpha < 0) {
1014 reg = 0x10;
1015 reg |= (0xFF - p_h264->loop_filter_alpha) + 1;
1016 } else {
1017 reg = 0x00;
1018 reg |= (p_h264->loop_filter_alpha & 0xF);
1019 }
1020 writel(reg, mfc_regs->e_h264_lf_alpha_offset);
1021
1022 /* loopfilter beta offset */
1023 if (p_h264->loop_filter_beta < 0) {
1024 reg = 0x10;
1025 reg |= (0xFF - p_h264->loop_filter_beta) + 1;
1026 } else {
1027 reg = 0x00;
1028 reg |= (p_h264->loop_filter_beta & 0xF);
1029 }
1030 writel(reg, mfc_regs->e_h264_lf_beta_offset);
1031
1032 /* entropy coding mode */
1033 reg = readl(mfc_regs->e_h264_options);
1034 reg &= ~(0x1);
1035 reg |= p_h264->entropy_mode & 0x1;
1036 writel(reg, mfc_regs->e_h264_options);
1037
1038 /* number of ref. picture */
1039 reg = readl(mfc_regs->e_h264_options);
1040 reg &= ~(0x1 << 7);
1041 reg |= (((p_h264->num_ref_pic_4p - 1) & 0x1) << 7);
1042 writel(reg, mfc_regs->e_h264_options);
1043
1044 /* 8x8 transform enable */
1045 reg = readl(mfc_regs->e_h264_options);
1046 reg &= ~(0x3 << 12);
1047 reg |= ((p_h264->_8x8_transform & 0x3) << 12);
1048 writel(reg, mfc_regs->e_h264_options);
1049
1050 /* macroblock adaptive scaling features */
1051 writel(0x0, mfc_regs->e_mb_rc_config);
1052 if (p->rc_mb) {
1053 reg = 0;
1054 /** dark region */
1055 reg |= ((p_h264->rc_mb_dark & 0x1) << 3);
1056 /** smooth region */
1057 reg |= ((p_h264->rc_mb_smooth & 0x1) << 2);
1058 /** static region */
1059 reg |= ((p_h264->rc_mb_static & 0x1) << 1);
1060 /** high activity region */
1061 reg |= p_h264->rc_mb_activity & 0x1;
1062 writel(reg, mfc_regs->e_mb_rc_config);
1063 }
1064
1065 /* aspect ratio VUI */
1066 readl(mfc_regs->e_h264_options);
1067 reg &= ~(0x1 << 5);
1068 reg |= ((p_h264->vui_sar & 0x1) << 5);
1069 writel(reg, mfc_regs->e_h264_options);
1070
1071 writel(0x0, mfc_regs->e_aspect_ratio);
1072 writel(0x0, mfc_regs->e_extended_sar);
1073 if (p_h264->vui_sar) {
1074 /* aspect ration IDC */
1075 reg = 0;
1076 reg |= p_h264->vui_sar_idc & 0xFF;
1077 writel(reg, mfc_regs->e_aspect_ratio);
1078 if (p_h264->vui_sar_idc == 0xFF) {
1079 /* extended SAR */
1080 reg = 0;
1081 reg |= (p_h264->vui_ext_sar_width & 0xFFFF) << 16;
1082 reg |= p_h264->vui_ext_sar_height & 0xFFFF;
1083 writel(reg, mfc_regs->e_extended_sar);
1084 }
1085 }
1086
1087 /* intra picture period for H.264 open GOP */
1088 /* control */
1089 readl(mfc_regs->e_h264_options);
1090 reg &= ~(0x1 << 4);
1091 reg |= ((p_h264->open_gop & 0x1) << 4);
1092 writel(reg, mfc_regs->e_h264_options);
1093
1094 /* value */
1095 writel(0x0, mfc_regs->e_h264_i_period);
1096 if (p_h264->open_gop) {
1097 reg = 0;
1098 reg |= p_h264->open_gop_size & 0xFFFF;
1099 writel(reg, mfc_regs->e_h264_i_period);
1100 }
1101
1102 /* 'WEIGHTED_BI_PREDICTION' for B is disable */
1103 readl(mfc_regs->e_h264_options);
1104 reg &= ~(0x3 << 9);
1105 writel(reg, mfc_regs->e_h264_options);
1106
1107 /* 'CONSTRAINED_INTRA_PRED_ENABLE' is disable */
1108 readl(mfc_regs->e_h264_options);
1109 reg &= ~(0x1 << 14);
1110 writel(reg, mfc_regs->e_h264_options);
1111
1112 /* ASO */
1113 readl(mfc_regs->e_h264_options);
1114 reg &= ~(0x1 << 6);
1115 reg |= ((p_h264->aso & 0x1) << 6);
1116 writel(reg, mfc_regs->e_h264_options);
1117
1118 /* hier qp enable */
1119 readl(mfc_regs->e_h264_options);
1120 reg &= ~(0x1 << 8);
1121 reg |= ((p_h264->open_gop & 0x1) << 8);
1122 writel(reg, mfc_regs->e_h264_options);
1123 reg = 0;
1124 if (p_h264->hier_qp && p_h264->hier_qp_layer) {
1125 reg |= (p_h264->hier_qp_type & 0x1) << 0x3;
1126 reg |= p_h264->hier_qp_layer & 0x7;
1127 writel(reg, mfc_regs->e_h264_num_t_layer);
1128 /* QP value for each layer */
1129 for (i = 0; i < p_h264->hier_qp_layer &&
1130 i < ARRAY_SIZE(p_h264->hier_qp_layer_qp); i++) {
1131 writel(p_h264->hier_qp_layer_qp[i],
1132 mfc_regs->e_h264_hierarchical_qp_layer0
1133 + i * 4);
1134 }
1135 }
1136 /* number of coding layer should be zero when hierarchical is disable */
1137 writel(reg, mfc_regs->e_h264_num_t_layer);
1138
1139 /* frame packing SEI generation */
1140 readl(mfc_regs->e_h264_options);
1141 reg &= ~(0x1 << 25);
1142 reg |= ((p_h264->sei_frame_packing & 0x1) << 25);
1143 writel(reg, mfc_regs->e_h264_options);
1144 if (p_h264->sei_frame_packing) {
1145 reg = 0;
1146 /** current frame0 flag */
1147 reg |= ((p_h264->sei_fp_curr_frame_0 & 0x1) << 2);
1148 /** arrangement type */
1149 reg |= p_h264->sei_fp_arrangement_type & 0x3;
1150 writel(reg, mfc_regs->e_h264_frame_packing_sei_info);
1151 }
1152
1153 if (p_h264->fmo) {
1154 switch (p_h264->fmo_map_type) {
1155 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_INTERLEAVED_SLICES:
1156 if (p_h264->fmo_slice_grp > 4)
1157 p_h264->fmo_slice_grp = 4;
1158 for (i = 0; i < (p_h264->fmo_slice_grp & 0xF); i++)
1159 writel(p_h264->fmo_run_len[i] - 1,
1160 mfc_regs->e_h264_fmo_run_length_minus1_0
1161 + i * 4);
1162 break;
1163 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_SCATTERED_SLICES:
1164 if (p_h264->fmo_slice_grp > 4)
1165 p_h264->fmo_slice_grp = 4;
1166 break;
1167 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_RASTER_SCAN:
1168 case V4L2_MPEG_VIDEO_H264_FMO_MAP_TYPE_WIPE_SCAN:
1169 if (p_h264->fmo_slice_grp > 2)
1170 p_h264->fmo_slice_grp = 2;
1171 writel(p_h264->fmo_chg_dir & 0x1,
1172 mfc_regs->e_h264_fmo_slice_grp_change_dir);
1173 /* the valid range is 0 ~ number of macroblocks -1 */
1174 writel(p_h264->fmo_chg_rate,
1175 mfc_regs->e_h264_fmo_slice_grp_change_rate_minus1);
1176 break;
1177 default:
1178 mfc_err("Unsupported map type for FMO: %d\n",
1179 p_h264->fmo_map_type);
1180 p_h264->fmo_map_type = 0;
1181 p_h264->fmo_slice_grp = 1;
1182 break;
1183 }
1184
1185 writel(p_h264->fmo_map_type,
1186 mfc_regs->e_h264_fmo_slice_grp_map_type);
1187 writel(p_h264->fmo_slice_grp - 1,
1188 mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1189 } else {
1190 writel(0, mfc_regs->e_h264_fmo_num_slice_grp_minus1);
1191 }
1192
1193 mfc_debug_leave();
1194
1195 return 0;
1196 }
1197
1198 static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx)
1199 {
1200 struct s5p_mfc_dev *dev = ctx->dev;
1201 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1202 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1203 struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4;
1204 unsigned int reg = 0;
1205
1206 mfc_debug_enter();
1207
1208 s5p_mfc_set_enc_params(ctx);
1209
1210 /* pictype : number of B */
1211 reg = readl(mfc_regs->e_gop_config);
1212 reg &= ~(0x3 << 16);
1213 reg |= ((p->num_b_frame & 0x3) << 16);
1214 writel(reg, mfc_regs->e_gop_config);
1215
1216 /* profile & level */
1217 reg = 0;
1218 /** level */
1219 reg |= ((p_mpeg4->level & 0xFF) << 8);
1220 /** profile - 0 ~ 1 */
1221 reg |= p_mpeg4->profile & 0x3F;
1222 writel(reg, mfc_regs->e_picture_profile);
1223
1224 /* rate control config. */
1225 reg = readl(mfc_regs->e_rc_config);
1226 /** macroblock level rate control */
1227 reg &= ~(0x1 << 8);
1228 reg |= ((p->rc_mb & 0x1) << 8);
1229 writel(reg, mfc_regs->e_rc_config);
1230
1231 /** frame QP */
1232 reg &= ~(0x3F);
1233 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1234 writel(reg, mfc_regs->e_rc_config);
1235
1236 /* max & min value of QP */
1237 reg = 0;
1238 /** max QP */
1239 reg |= ((p_mpeg4->rc_max_qp & 0x3F) << 8);
1240 /** min QP */
1241 reg |= p_mpeg4->rc_min_qp & 0x3F;
1242 writel(reg, mfc_regs->e_rc_qp_bound);
1243
1244 /* other QPs */
1245 writel(0x0, mfc_regs->e_fixed_picture_qp);
1246 if (!p->rc_frame && !p->rc_mb) {
1247 reg = 0;
1248 reg |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 16);
1249 reg |= ((p_mpeg4->rc_p_frame_qp & 0x3F) << 8);
1250 reg |= p_mpeg4->rc_frame_qp & 0x3F;
1251 writel(reg, mfc_regs->e_fixed_picture_qp);
1252 }
1253
1254 /* frame rate */
1255 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1256 reg = 0;
1257 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1258 reg |= p->rc_framerate_denom & 0xFFFF;
1259 writel(reg, mfc_regs->e_rc_frame_rate);
1260 }
1261
1262 /* vbv buffer size */
1263 if (p->frame_skip_mode ==
1264 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1265 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1266
1267 if (p->rc_frame)
1268 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1269 }
1270
1271 /* Disable HEC */
1272 writel(0x0, mfc_regs->e_mpeg4_options);
1273 writel(0x0, mfc_regs->e_mpeg4_hec_period);
1274
1275 mfc_debug_leave();
1276
1277 return 0;
1278 }
1279
1280 static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx)
1281 {
1282 struct s5p_mfc_dev *dev = ctx->dev;
1283 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1284 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1285 struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4;
1286 unsigned int reg = 0;
1287
1288 mfc_debug_enter();
1289
1290 s5p_mfc_set_enc_params(ctx);
1291
1292 /* profile & level */
1293 reg = 0;
1294 /** profile */
1295 reg |= (0x1 << 4);
1296 writel(reg, mfc_regs->e_picture_profile);
1297
1298 /* rate control config. */
1299 reg = readl(mfc_regs->e_rc_config);
1300 /** macroblock level rate control */
1301 reg &= ~(0x1 << 8);
1302 reg |= ((p->rc_mb & 0x1) << 8);
1303 writel(reg, mfc_regs->e_rc_config);
1304
1305 /** frame QP */
1306 reg &= ~(0x3F);
1307 reg |= p_h263->rc_frame_qp & 0x3F;
1308 writel(reg, mfc_regs->e_rc_config);
1309
1310 /* max & min value of QP */
1311 reg = 0;
1312 /** max QP */
1313 reg |= ((p_h263->rc_max_qp & 0x3F) << 8);
1314 /** min QP */
1315 reg |= p_h263->rc_min_qp & 0x3F;
1316 writel(reg, mfc_regs->e_rc_qp_bound);
1317
1318 /* other QPs */
1319 writel(0x0, mfc_regs->e_fixed_picture_qp);
1320 if (!p->rc_frame && !p->rc_mb) {
1321 reg = 0;
1322 reg |= ((p_h263->rc_b_frame_qp & 0x3F) << 16);
1323 reg |= ((p_h263->rc_p_frame_qp & 0x3F) << 8);
1324 reg |= p_h263->rc_frame_qp & 0x3F;
1325 writel(reg, mfc_regs->e_fixed_picture_qp);
1326 }
1327
1328 /* frame rate */
1329 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1330 reg = 0;
1331 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1332 reg |= p->rc_framerate_denom & 0xFFFF;
1333 writel(reg, mfc_regs->e_rc_frame_rate);
1334 }
1335
1336 /* vbv buffer size */
1337 if (p->frame_skip_mode ==
1338 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1339 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1340
1341 if (p->rc_frame)
1342 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1343 }
1344
1345 mfc_debug_leave();
1346
1347 return 0;
1348 }
1349
1350 static int s5p_mfc_set_enc_params_vp8(struct s5p_mfc_ctx *ctx)
1351 {
1352 struct s5p_mfc_dev *dev = ctx->dev;
1353 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1354 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1355 struct s5p_mfc_vp8_enc_params *p_vp8 = &p->codec.vp8;
1356 unsigned int reg = 0;
1357 unsigned int val = 0;
1358
1359 mfc_debug_enter();
1360
1361 s5p_mfc_set_enc_params(ctx);
1362
1363 /* pictype : number of B */
1364 reg = readl(mfc_regs->e_gop_config);
1365 reg &= ~(0x3 << 16);
1366 reg |= ((p->num_b_frame & 0x3) << 16);
1367 writel(reg, mfc_regs->e_gop_config);
1368
1369 /* profile - 0 ~ 3 */
1370 reg = p_vp8->profile & 0x3;
1371 writel(reg, mfc_regs->e_picture_profile);
1372
1373 /* rate control config. */
1374 reg = readl(mfc_regs->e_rc_config);
1375 /** macroblock level rate control */
1376 reg &= ~(0x1 << 8);
1377 reg |= ((p->rc_mb & 0x1) << 8);
1378 writel(reg, mfc_regs->e_rc_config);
1379
1380 /* frame rate */
1381 if (p->rc_frame && p->rc_framerate_num && p->rc_framerate_denom) {
1382 reg = 0;
1383 reg |= ((p->rc_framerate_num & 0xFFFF) << 16);
1384 reg |= p->rc_framerate_denom & 0xFFFF;
1385 writel(reg, mfc_regs->e_rc_frame_rate);
1386 }
1387
1388 /* frame QP */
1389 reg &= ~(0x7F);
1390 reg |= p_vp8->rc_frame_qp & 0x7F;
1391 writel(reg, mfc_regs->e_rc_config);
1392
1393 /* other QPs */
1394 writel(0x0, mfc_regs->e_fixed_picture_qp);
1395 if (!p->rc_frame && !p->rc_mb) {
1396 reg = 0;
1397 reg |= ((p_vp8->rc_p_frame_qp & 0x7F) << 8);
1398 reg |= p_vp8->rc_frame_qp & 0x7F;
1399 writel(reg, mfc_regs->e_fixed_picture_qp);
1400 }
1401
1402 /* max QP */
1403 reg = ((p_vp8->rc_max_qp & 0x7F) << 8);
1404 /* min QP */
1405 reg |= p_vp8->rc_min_qp & 0x7F;
1406 writel(reg, mfc_regs->e_rc_qp_bound);
1407
1408 /* vbv buffer size */
1409 if (p->frame_skip_mode ==
1410 V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) {
1411 writel(p->vbv_size & 0xFFFF, mfc_regs->e_vbv_buffer_size);
1412
1413 if (p->rc_frame)
1414 writel(p->vbv_delay, mfc_regs->e_vbv_init_delay);
1415 }
1416
1417 /* VP8 specific params */
1418 reg = 0;
1419 reg |= (p_vp8->imd_4x4 & 0x1) << 10;
1420 switch (p_vp8->num_partitions) {
1421 case V4L2_CID_MPEG_VIDEO_VPX_1_PARTITION:
1422 val = 0;
1423 break;
1424 case V4L2_CID_MPEG_VIDEO_VPX_2_PARTITIONS:
1425 val = 2;
1426 break;
1427 case V4L2_CID_MPEG_VIDEO_VPX_4_PARTITIONS:
1428 val = 4;
1429 break;
1430 case V4L2_CID_MPEG_VIDEO_VPX_8_PARTITIONS:
1431 val = 8;
1432 break;
1433 }
1434 reg |= (val & 0xF) << 3;
1435 reg |= (p_vp8->num_ref & 0x2);
1436 writel(reg, mfc_regs->e_vp8_options);
1437
1438 mfc_debug_leave();
1439
1440 return 0;
1441 }
1442
1443 static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx)
1444 {
1445 struct s5p_mfc_dev *dev = ctx->dev;
1446 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1447 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1448 struct s5p_mfc_hevc_enc_params *p_hevc = &p->codec.hevc;
1449 unsigned int reg = 0;
1450 int i;
1451
1452 mfc_debug_enter();
1453
1454 s5p_mfc_set_enc_params(ctx);
1455
1456 /* pictype : number of B */
1457 reg = readl(mfc_regs->e_gop_config);
1458 /* num_b_frame - 0 ~ 2 */
1459 reg &= ~(0x3 << 16);
1460 reg |= (p->num_b_frame << 16);
1461 writel(reg, mfc_regs->e_gop_config);
1462
1463 /* UHD encoding case */
1464 if ((ctx->img_width == 3840) && (ctx->img_height == 2160)) {
1465 p_hevc->level = 51;
1466 p_hevc->tier = 0;
1467 /* this tier can be changed */
1468 }
1469
1470 /* tier & level */
1471 reg = 0;
1472 /* profile */
1473 reg |= p_hevc->profile & 0x3;
1474 /* level */
1475 reg &= ~(0xFF << 8);
1476 reg |= (p_hevc->level << 8);
1477 /* tier - 0 ~ 1 */
1478 reg |= (p_hevc->tier << 16);
1479 writel(reg, mfc_regs->e_picture_profile);
1480
1481 switch (p_hevc->loopfilter) {
1482 case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED:
1483 p_hevc->loopfilter_disable = 1;
1484 break;
1485 case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_ENABLED:
1486 p_hevc->loopfilter_disable = 0;
1487 p_hevc->loopfilter_across = 1;
1488 break;
1489 case V4L2_MPEG_VIDEO_HEVC_LOOP_FILTER_MODE_DISABLED_AT_SLICE_BOUNDARY:
1490 p_hevc->loopfilter_disable = 0;
1491 p_hevc->loopfilter_across = 0;
1492 break;
1493 }
1494
1495 /* max partition depth */
1496 reg = 0;
1497 reg |= (p_hevc->max_partition_depth & 0x1);
1498 reg |= (p_hevc->num_refs_for_p-1) << 2;
1499 reg |= (p_hevc->refreshtype & 0x3) << 3;
1500 reg |= (p_hevc->const_intra_period_enable & 0x1) << 5;
1501 reg |= (p_hevc->lossless_cu_enable & 0x1) << 6;
1502 reg |= (p_hevc->wavefront_enable & 0x1) << 7;
1503 reg |= (p_hevc->loopfilter_disable & 0x1) << 8;
1504 reg |= (p_hevc->loopfilter_across & 0x1) << 9;
1505 reg |= (p_hevc->enable_ltr & 0x1) << 10;
1506 reg |= (p_hevc->hier_qp_enable & 0x1) << 11;
1507 reg |= (p_hevc->general_pb_enable & 0x1) << 13;
1508 reg |= (p_hevc->temporal_id_enable & 0x1) << 14;
1509 reg |= (p_hevc->strong_intra_smooth & 0x1) << 15;
1510 reg |= (p_hevc->intra_pu_split_disable & 0x1) << 16;
1511 reg |= (p_hevc->tmv_prediction_disable & 0x1) << 17;
1512 reg |= (p_hevc->max_num_merge_mv & 0x7) << 18;
1513 reg |= (p_hevc->encoding_nostartcode_enable & 0x1) << 23;
1514 reg |= (p_hevc->prepend_sps_pps_to_idr << 26);
1515
1516 writel(reg, mfc_regs->e_hevc_options);
1517 /* refresh period */
1518 if (p_hevc->refreshtype) {
1519 reg = 0;
1520 reg |= (p_hevc->refreshperiod & 0xFFFF);
1521 writel(reg, mfc_regs->e_hevc_refresh_period);
1522 }
1523 /* loop filter setting */
1524 if (!(p_hevc->loopfilter_disable & 0x1)) {
1525 reg = 0;
1526 reg |= (p_hevc->lf_beta_offset_div2);
1527 writel(reg, mfc_regs->e_hevc_lf_beta_offset_div2);
1528 reg = 0;
1529 reg |= (p_hevc->lf_tc_offset_div2);
1530 writel(reg, mfc_regs->e_hevc_lf_tc_offset_div2);
1531 }
1532 /* hier qp enable */
1533 if (p_hevc->num_hier_layer) {
1534 reg = 0;
1535 reg |= (p_hevc->hier_qp_type & 0x1) << 0x3;
1536 reg |= p_hevc->num_hier_layer & 0x7;
1537 writel(reg, mfc_regs->e_num_t_layer);
1538 /* QP value for each layer */
1539 if (p_hevc->hier_qp_enable) {
1540 for (i = 0; i < 7; i++)
1541 writel(p_hevc->hier_qp_layer[i],
1542 mfc_regs->e_hier_qp_layer0 + i * 4);
1543 }
1544 if (p->rc_frame) {
1545 for (i = 0; i < 7; i++)
1546 writel(p_hevc->hier_bit_layer[i],
1547 mfc_regs->e_hier_bit_rate_layer0
1548 + i * 4);
1549 }
1550 }
1551
1552 /* rate control config. */
1553 reg = readl(mfc_regs->e_rc_config);
1554 /* macroblock level rate control */
1555 reg &= ~(0x1 << 8);
1556 reg |= (p->rc_mb << 8);
1557 writel(reg, mfc_regs->e_rc_config);
1558 /* frame QP */
1559 reg &= ~(0xFF);
1560 reg |= p_hevc->rc_frame_qp;
1561 writel(reg, mfc_regs->e_rc_config);
1562
1563 /* frame rate */
1564 if (p->rc_frame) {
1565 reg = 0;
1566 reg &= ~(0xFFFF << 16);
1567 reg |= ((p_hevc->rc_framerate) << 16);
1568 reg &= ~(0xFFFF);
1569 reg |= FRAME_DELTA_DEFAULT;
1570 writel(reg, mfc_regs->e_rc_frame_rate);
1571 }
1572
1573 /* max & min value of QP */
1574 reg = 0;
1575 /* max QP */
1576 reg &= ~(0xFF << 8);
1577 reg |= (p_hevc->rc_max_qp << 8);
1578 /* min QP */
1579 reg &= ~(0xFF);
1580 reg |= p_hevc->rc_min_qp;
1581 writel(reg, mfc_regs->e_rc_qp_bound);
1582
1583 writel(0x0, mfc_regs->e_fixed_picture_qp);
1584 if (!p->rc_frame && !p->rc_mb) {
1585 reg = 0;
1586 reg &= ~(0xFF << 16);
1587 reg |= (p_hevc->rc_b_frame_qp << 16);
1588 reg &= ~(0xFF << 8);
1589 reg |= (p_hevc->rc_p_frame_qp << 8);
1590 reg &= ~(0xFF);
1591 reg |= p_hevc->rc_frame_qp;
1592 writel(reg, mfc_regs->e_fixed_picture_qp);
1593 }
1594 mfc_debug_leave();
1595
1596 return 0;
1597 }
1598
1599 /* Initialize decoding */
1600 static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx)
1601 {
1602 struct s5p_mfc_dev *dev = ctx->dev;
1603 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1604 unsigned int reg = 0;
1605 int fmo_aso_ctrl = 0;
1606
1607 mfc_debug_enter();
1608 mfc_debug(2, "InstNo: %d/%d\n", ctx->inst_no,
1609 S5P_FIMV_CH_SEQ_HEADER_V6);
1610 mfc_debug(2, "BUFs: %08x %08x %08x\n",
1611 readl(mfc_regs->d_cpb_buffer_addr),
1612 readl(mfc_regs->d_cpb_buffer_addr),
1613 readl(mfc_regs->d_cpb_buffer_addr));
1614
1615 /* FMO_ASO_CTRL - 0: Enable, 1: Disable */
1616 reg |= (fmo_aso_ctrl << S5P_FIMV_D_OPT_FMO_ASO_CTRL_MASK_V6);
1617
1618 if (ctx->display_delay_enable) {
1619 reg |= (0x1 << S5P_FIMV_D_OPT_DDELAY_EN_SHIFT_V6);
1620 writel(ctx->display_delay, mfc_regs->d_display_delay);
1621 }
1622
1623 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev)) {
1624 writel(reg, mfc_regs->d_dec_options);
1625 reg = 0;
1626 }
1627
1628 /* Setup loop filter, for decoding this is only valid for MPEG4 */
1629 if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) {
1630 mfc_debug(2, "Set loop filter to: %d\n",
1631 ctx->loop_filter_mpeg4);
1632 reg |= (ctx->loop_filter_mpeg4 <<
1633 S5P_FIMV_D_OPT_LF_CTRL_SHIFT_V6);
1634 }
1635 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV12MT_16X16)
1636 reg |= (0x1 << S5P_FIMV_D_OPT_TILE_MODE_SHIFT_V6);
1637
1638 if (IS_MFCV7_PLUS(dev) || IS_MFCV6_V2(dev))
1639 writel(reg, mfc_regs->d_init_buffer_options);
1640 else
1641 writel(reg, mfc_regs->d_dec_options);
1642
1643 /* 0: NV12(CbCr), 1: NV21(CrCb) */
1644 if (ctx->dst_fmt->fourcc == V4L2_PIX_FMT_NV21M)
1645 writel(0x1, mfc_regs->pixel_format);
1646 else
1647 writel(0x0, mfc_regs->pixel_format);
1648
1649
1650 /* sei parse */
1651 writel(ctx->sei_fp_parse & 0x1, mfc_regs->d_sei_enable);
1652
1653 writel(ctx->inst_no, mfc_regs->instance_id);
1654 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1655 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1656
1657 mfc_debug_leave();
1658 return 0;
1659 }
1660
1661 static inline void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush)
1662 {
1663 struct s5p_mfc_dev *dev = ctx->dev;
1664 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1665
1666 if (flush) {
1667 dev->curr_ctx = ctx->num;
1668 writel(ctx->inst_no, mfc_regs->instance_id);
1669 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1670 S5P_FIMV_H2R_CMD_FLUSH_V6, NULL);
1671 }
1672 }
1673
1674 /* Decode a single frame */
1675 static int s5p_mfc_decode_one_frame_v6(struct s5p_mfc_ctx *ctx,
1676 enum s5p_mfc_decode_arg last_frame)
1677 {
1678 struct s5p_mfc_dev *dev = ctx->dev;
1679 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1680
1681 writel(ctx->dec_dst_flag, mfc_regs->d_available_dpb_flag_lower);
1682 writel(ctx->slice_interface & 0x1, mfc_regs->d_slice_if_enable);
1683
1684 writel(ctx->inst_no, mfc_regs->instance_id);
1685 /* Issue different commands to instance basing on whether it
1686 * is the last frame or not. */
1687 switch (last_frame) {
1688 case 0:
1689 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1690 S5P_FIMV_CH_FRAME_START_V6, NULL);
1691 break;
1692 case 1:
1693 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1694 S5P_FIMV_CH_LAST_FRAME_V6, NULL);
1695 break;
1696 default:
1697 mfc_err("Unsupported last frame arg.\n");
1698 return -EINVAL;
1699 }
1700
1701 mfc_debug(2, "Decoding a usual frame.\n");
1702 return 0;
1703 }
1704
1705 static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx)
1706 {
1707 struct s5p_mfc_dev *dev = ctx->dev;
1708 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1709
1710 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1711 s5p_mfc_set_enc_params_h264(ctx);
1712 else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC)
1713 s5p_mfc_set_enc_params_mpeg4(ctx);
1714 else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC)
1715 s5p_mfc_set_enc_params_h263(ctx);
1716 else if (ctx->codec_mode == S5P_MFC_CODEC_VP8_ENC)
1717 s5p_mfc_set_enc_params_vp8(ctx);
1718 else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC)
1719 s5p_mfc_set_enc_params_hevc(ctx);
1720 else {
1721 mfc_err("Unknown codec for encoding (%x).\n",
1722 ctx->codec_mode);
1723 return -EINVAL;
1724 }
1725
1726 /* Set stride lengths for v7 & above */
1727 if (IS_MFCV7_PLUS(dev)) {
1728 writel(ctx->img_width, mfc_regs->e_source_first_plane_stride);
1729 writel(ctx->img_width, mfc_regs->e_source_second_plane_stride);
1730 }
1731
1732 writel(ctx->inst_no, mfc_regs->instance_id);
1733 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev,
1734 S5P_FIMV_CH_SEQ_HEADER_V6, NULL);
1735
1736 return 0;
1737 }
1738
1739 static int s5p_mfc_h264_set_aso_slice_order_v6(struct s5p_mfc_ctx *ctx)
1740 {
1741 struct s5p_mfc_dev *dev = ctx->dev;
1742 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1743 struct s5p_mfc_enc_params *p = &ctx->enc_params;
1744 struct s5p_mfc_h264_enc_params *p_h264 = &p->codec.h264;
1745 int i;
1746
1747 if (p_h264->aso) {
1748 for (i = 0; i < ARRAY_SIZE(p_h264->aso_slice_order); i++) {
1749 writel(p_h264->aso_slice_order[i],
1750 mfc_regs->e_h264_aso_slice_order_0 + i * 4);
1751 }
1752 }
1753 return 0;
1754 }
1755
1756 /* Encode a single frame */
1757 static int s5p_mfc_encode_one_frame_v6(struct s5p_mfc_ctx *ctx)
1758 {
1759 struct s5p_mfc_dev *dev = ctx->dev;
1760 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
1761 int cmd;
1762
1763 mfc_debug(2, "++\n");
1764
1765 /* memory structure cur. frame */
1766
1767 if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC)
1768 s5p_mfc_h264_set_aso_slice_order_v6(ctx);
1769
1770 s5p_mfc_set_slice_mode(ctx);
1771
1772 if (ctx->state != MFCINST_FINISHING)
1773 cmd = S5P_FIMV_CH_FRAME_START_V6;
1774 else
1775 cmd = S5P_FIMV_CH_LAST_FRAME_V6;
1776
1777 writel(ctx->inst_no, mfc_regs->instance_id);
1778 s5p_mfc_hw_call(dev->mfc_cmds, cmd_host2risc, dev, cmd, NULL);
1779
1780 mfc_debug(2, "--\n");
1781
1782 return 0;
1783 }
1784
1785 static inline void s5p_mfc_run_dec_last_frames(struct s5p_mfc_ctx *ctx)
1786 {
1787 struct s5p_mfc_dev *dev = ctx->dev;
1788
1789 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1790 dev->curr_ctx = ctx->num;
1791 s5p_mfc_decode_one_frame_v6(ctx, MFC_DEC_LAST_FRAME);
1792 }
1793
1794 static inline int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx)
1795 {
1796 struct s5p_mfc_dev *dev = ctx->dev;
1797 struct s5p_mfc_buf *temp_vb;
1798 int last_frame = 0;
1799
1800 if (ctx->state == MFCINST_FINISHING) {
1801 last_frame = MFC_DEC_LAST_FRAME;
1802 s5p_mfc_set_dec_stream_buffer_v6(ctx, 0, 0, 0);
1803 dev->curr_ctx = ctx->num;
1804 s5p_mfc_clean_ctx_int_flags(ctx);
1805 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1806 return 0;
1807 }
1808
1809 /* Frames are being decoded */
1810 if (list_empty(&ctx->src_queue)) {
1811 mfc_debug(2, "No src buffers.\n");
1812 return -EAGAIN;
1813 }
1814 /* Get the next source buffer */
1815 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1816 temp_vb->flags |= MFC_BUF_FLAG_USED;
1817 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1818 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0),
1819 ctx->consumed_stream,
1820 temp_vb->b->vb2_buf.planes[0].bytesused);
1821
1822 dev->curr_ctx = ctx->num;
1823 if (temp_vb->b->vb2_buf.planes[0].bytesused == 0) {
1824 last_frame = 1;
1825 mfc_debug(2, "Setting ctx->state to FINISHING\n");
1826 ctx->state = MFCINST_FINISHING;
1827 }
1828 s5p_mfc_decode_one_frame_v6(ctx, last_frame);
1829
1830 return 0;
1831 }
1832
1833 static inline int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx)
1834 {
1835 struct s5p_mfc_dev *dev = ctx->dev;
1836 struct s5p_mfc_buf *dst_mb;
1837 struct s5p_mfc_buf *src_mb;
1838 unsigned long src_y_addr, src_c_addr, dst_addr;
1839 /*
1840 unsigned int src_y_size, src_c_size;
1841 */
1842 unsigned int dst_size;
1843
1844 if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) {
1845 mfc_debug(2, "no src buffers.\n");
1846 return -EAGAIN;
1847 }
1848
1849 if (list_empty(&ctx->dst_queue)) {
1850 mfc_debug(2, "no dst buffers.\n");
1851 return -EAGAIN;
1852 }
1853
1854 if (list_empty(&ctx->src_queue)) {
1855 /* send null frame */
1856 s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
1857 src_mb = NULL;
1858 } else {
1859 src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1860 src_mb->flags |= MFC_BUF_FLAG_USED;
1861 if (src_mb->b->vb2_buf.planes[0].bytesused == 0) {
1862 s5p_mfc_set_enc_frame_buffer_v6(ctx, 0, 0);
1863 ctx->state = MFCINST_FINISHING;
1864 } else {
1865 src_y_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 0);
1866 src_c_addr = vb2_dma_contig_plane_dma_addr(&src_mb->b->vb2_buf, 1);
1867
1868 mfc_debug(2, "enc src y addr: 0x%08lx\n", src_y_addr);
1869 mfc_debug(2, "enc src c addr: 0x%08lx\n", src_c_addr);
1870
1871 s5p_mfc_set_enc_frame_buffer_v6(ctx, src_y_addr, src_c_addr);
1872 if (src_mb->flags & MFC_BUF_FLAG_EOS)
1873 ctx->state = MFCINST_FINISHING;
1874 }
1875 }
1876
1877 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1878 dst_mb->flags |= MFC_BUF_FLAG_USED;
1879 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1880 dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1881
1882 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1883
1884 dev->curr_ctx = ctx->num;
1885 s5p_mfc_encode_one_frame_v6(ctx);
1886
1887 return 0;
1888 }
1889
1890 static inline void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx)
1891 {
1892 struct s5p_mfc_dev *dev = ctx->dev;
1893 struct s5p_mfc_buf *temp_vb;
1894
1895 /* Initializing decoding - parsing header */
1896 mfc_debug(2, "Preparing to init decoding.\n");
1897 temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
1898 mfc_debug(2, "Header size: %d\n", temp_vb->b->vb2_buf.planes[0].bytesused);
1899 s5p_mfc_set_dec_stream_buffer_v6(ctx,
1900 vb2_dma_contig_plane_dma_addr(&temp_vb->b->vb2_buf, 0), 0,
1901 temp_vb->b->vb2_buf.planes[0].bytesused);
1902 dev->curr_ctx = ctx->num;
1903 s5p_mfc_init_decode_v6(ctx);
1904 }
1905
1906 static inline void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx)
1907 {
1908 struct s5p_mfc_dev *dev = ctx->dev;
1909 struct s5p_mfc_buf *dst_mb;
1910 unsigned long dst_addr;
1911 unsigned int dst_size;
1912
1913 dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list);
1914 dst_addr = vb2_dma_contig_plane_dma_addr(&dst_mb->b->vb2_buf, 0);
1915 dst_size = vb2_plane_size(&dst_mb->b->vb2_buf, 0);
1916 s5p_mfc_set_enc_stream_buffer_v6(ctx, dst_addr, dst_size);
1917 dev->curr_ctx = ctx->num;
1918 s5p_mfc_init_encode_v6(ctx);
1919 }
1920
1921 static inline int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx)
1922 {
1923 struct s5p_mfc_dev *dev = ctx->dev;
1924 int ret;
1925 /* Header was parsed now start processing
1926 * First set the output frame buffers
1927 * s5p_mfc_alloc_dec_buffers(ctx); */
1928
1929 if (ctx->capture_state != QUEUE_BUFS_MMAPED) {
1930 mfc_err("It seems that not all destination buffers were\n"
1931 "mmaped.MFC requires that all destination are mmaped\n"
1932 "before starting processing.\n");
1933 return -EAGAIN;
1934 }
1935
1936 dev->curr_ctx = ctx->num;
1937 ret = s5p_mfc_set_dec_frame_buffer_v6(ctx);
1938 if (ret) {
1939 mfc_err("Failed to alloc frame mem.\n");
1940 ctx->state = MFCINST_ERROR;
1941 }
1942 return ret;
1943 }
1944
1945 static inline int s5p_mfc_run_init_enc_buffers(struct s5p_mfc_ctx *ctx)
1946 {
1947 struct s5p_mfc_dev *dev = ctx->dev;
1948 int ret;
1949
1950 dev->curr_ctx = ctx->num;
1951 ret = s5p_mfc_set_enc_ref_buffer_v6(ctx);
1952 if (ret) {
1953 mfc_err("Failed to alloc frame mem.\n");
1954 ctx->state = MFCINST_ERROR;
1955 }
1956 return ret;
1957 }
1958
1959 /* Try running an operation on hardware */
1960 static void s5p_mfc_try_run_v6(struct s5p_mfc_dev *dev)
1961 {
1962 struct s5p_mfc_ctx *ctx;
1963 int new_ctx;
1964 unsigned int ret = 0;
1965
1966 mfc_debug(1, "Try run dev: %p\n", dev);
1967
1968 /* Check whether hardware is not running */
1969 if (test_and_set_bit(0, &dev->hw_lock) != 0) {
1970 /* This is perfectly ok, the scheduled ctx should wait */
1971 mfc_debug(1, "Couldn't lock HW.\n");
1972 return;
1973 }
1974
1975 /* Choose the context to run */
1976 new_ctx = s5p_mfc_get_new_ctx(dev);
1977 if (new_ctx < 0) {
1978 /* No contexts to run */
1979 if (test_and_clear_bit(0, &dev->hw_lock) == 0) {
1980 mfc_err("Failed to unlock hardware.\n");
1981 return;
1982 }
1983
1984 mfc_debug(1, "No ctx is scheduled to be run.\n");
1985 return;
1986 }
1987
1988 mfc_debug(1, "New context: %d\n", new_ctx);
1989 ctx = dev->ctx[new_ctx];
1990 mfc_debug(1, "Setting new context to %p\n", ctx);
1991 /* Got context to run in ctx */
1992 mfc_debug(1, "ctx->dst_queue_cnt=%d ctx->dpb_count=%d ctx->src_queue_cnt=%d\n",
1993 ctx->dst_queue_cnt, ctx->pb_count, ctx->src_queue_cnt);
1994 mfc_debug(1, "ctx->state=%d\n", ctx->state);
1995 /* Last frame has already been sent to MFC
1996 * Now obtaining frames from MFC buffer */
1997
1998 s5p_mfc_clock_on();
1999 s5p_mfc_clean_ctx_int_flags(ctx);
2000
2001 if (ctx->type == MFCINST_DECODER) {
2002 switch (ctx->state) {
2003 case MFCINST_FINISHING:
2004 s5p_mfc_run_dec_last_frames(ctx);
2005 break;
2006 case MFCINST_RUNNING:
2007 ret = s5p_mfc_run_dec_frame(ctx);
2008 break;
2009 case MFCINST_INIT:
2010 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
2011 ctx);
2012 break;
2013 case MFCINST_RETURN_INST:
2014 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
2015 ctx);
2016 break;
2017 case MFCINST_GOT_INST:
2018 s5p_mfc_run_init_dec(ctx);
2019 break;
2020 case MFCINST_HEAD_PARSED:
2021 ret = s5p_mfc_run_init_dec_buffers(ctx);
2022 break;
2023 case MFCINST_FLUSH:
2024 s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag);
2025 break;
2026 case MFCINST_RES_CHANGE_INIT:
2027 s5p_mfc_run_dec_last_frames(ctx);
2028 break;
2029 case MFCINST_RES_CHANGE_FLUSH:
2030 s5p_mfc_run_dec_last_frames(ctx);
2031 break;
2032 case MFCINST_RES_CHANGE_END:
2033 mfc_debug(2, "Finished remaining frames after resolution change.\n");
2034 ctx->capture_state = QUEUE_FREE;
2035 mfc_debug(2, "Will re-init the codec`.\n");
2036 s5p_mfc_run_init_dec(ctx);
2037 break;
2038 default:
2039 ret = -EAGAIN;
2040 }
2041 } else if (ctx->type == MFCINST_ENCODER) {
2042 switch (ctx->state) {
2043 case MFCINST_FINISHING:
2044 case MFCINST_RUNNING:
2045 ret = s5p_mfc_run_enc_frame(ctx);
2046 break;
2047 case MFCINST_INIT:
2048 ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd,
2049 ctx);
2050 break;
2051 case MFCINST_RETURN_INST:
2052 ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd,
2053 ctx);
2054 break;
2055 case MFCINST_GOT_INST:
2056 s5p_mfc_run_init_enc(ctx);
2057 break;
2058 case MFCINST_HEAD_PRODUCED:
2059 ret = s5p_mfc_run_init_enc_buffers(ctx);
2060 break;
2061 default:
2062 ret = -EAGAIN;
2063 }
2064 } else {
2065 mfc_err("invalid context type: %d\n", ctx->type);
2066 ret = -EAGAIN;
2067 }
2068
2069 if (ret) {
2070 /* Free hardware lock */
2071 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
2072 mfc_err("Failed to unlock hardware.\n");
2073
2074 /* This is in deed imporant, as no operation has been
2075 * scheduled, reduce the clock count as no one will
2076 * ever do this, because no interrupt related to this try_run
2077 * will ever come from hardware. */
2078 s5p_mfc_clock_off();
2079 }
2080 }
2081
2082 static void s5p_mfc_clear_int_flags_v6(struct s5p_mfc_dev *dev)
2083 {
2084 const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs;
2085 writel(0, mfc_regs->risc2host_command);
2086 writel(0, mfc_regs->risc2host_int);
2087 }
2088
2089 static unsigned int
2090 s5p_mfc_read_info_v6(struct s5p_mfc_ctx *ctx, unsigned long ofs)
2091 {
2092 int ret;
2093
2094 s5p_mfc_clock_on();
2095 ret = readl((void __iomem *)ofs);
2096 s5p_mfc_clock_off();
2097
2098 return ret;
2099 }
2100
2101 static int s5p_mfc_get_dspl_y_adr_v6(struct s5p_mfc_dev *dev)
2102 {
2103 return readl(dev->mfc_regs->d_display_first_plane_addr);
2104 }
2105
2106 static int s5p_mfc_get_dec_y_adr_v6(struct s5p_mfc_dev *dev)
2107 {
2108 return readl(dev->mfc_regs->d_decoded_first_plane_addr);
2109 }
2110
2111 static int s5p_mfc_get_dspl_status_v6(struct s5p_mfc_dev *dev)
2112 {
2113 return readl(dev->mfc_regs->d_display_status);
2114 }
2115
2116 static int s5p_mfc_get_dec_status_v6(struct s5p_mfc_dev *dev)
2117 {
2118 return readl(dev->mfc_regs->d_decoded_status);
2119 }
2120
2121 static int s5p_mfc_get_dec_frame_type_v6(struct s5p_mfc_dev *dev)
2122 {
2123 return readl(dev->mfc_regs->d_decoded_frame_type) &
2124 S5P_FIMV_DECODE_FRAME_MASK_V6;
2125 }
2126
2127 static int s5p_mfc_get_disp_frame_type_v6(struct s5p_mfc_ctx *ctx)
2128 {
2129 struct s5p_mfc_dev *dev = ctx->dev;
2130 return readl(dev->mfc_regs->d_display_frame_type) &
2131 S5P_FIMV_DECODE_FRAME_MASK_V6;
2132 }
2133
2134 static int s5p_mfc_get_consumed_stream_v6(struct s5p_mfc_dev *dev)
2135 {
2136 return readl(dev->mfc_regs->d_decoded_nal_size);
2137 }
2138
2139 static int s5p_mfc_get_int_reason_v6(struct s5p_mfc_dev *dev)
2140 {
2141 return readl(dev->mfc_regs->risc2host_command) &
2142 S5P_FIMV_RISC2HOST_CMD_MASK;
2143 }
2144
2145 static int s5p_mfc_get_int_err_v6(struct s5p_mfc_dev *dev)
2146 {
2147 return readl(dev->mfc_regs->error_code);
2148 }
2149
2150 static int s5p_mfc_err_dec_v6(unsigned int err)
2151 {
2152 return (err & S5P_FIMV_ERR_DEC_MASK_V6) >> S5P_FIMV_ERR_DEC_SHIFT_V6;
2153 }
2154
2155 static int s5p_mfc_get_img_width_v6(struct s5p_mfc_dev *dev)
2156 {
2157 return readl(dev->mfc_regs->d_display_frame_width);
2158 }
2159
2160 static int s5p_mfc_get_img_height_v6(struct s5p_mfc_dev *dev)
2161 {
2162 return readl(dev->mfc_regs->d_display_frame_height);
2163 }
2164
2165 static int s5p_mfc_get_dpb_count_v6(struct s5p_mfc_dev *dev)
2166 {
2167 return readl(dev->mfc_regs->d_min_num_dpb);
2168 }
2169
2170 static int s5p_mfc_get_mv_count_v6(struct s5p_mfc_dev *dev)
2171 {
2172 return readl(dev->mfc_regs->d_min_num_mv);
2173 }
2174
2175 static int s5p_mfc_get_min_scratch_buf_size(struct s5p_mfc_dev *dev)
2176 {
2177 return readl(dev->mfc_regs->d_min_scratch_buffer_size);
2178 }
2179
2180 static int s5p_mfc_get_e_min_scratch_buf_size(struct s5p_mfc_dev *dev)
2181 {
2182 return readl(dev->mfc_regs->e_min_scratch_buffer_size);
2183 }
2184
2185 static int s5p_mfc_get_inst_no_v6(struct s5p_mfc_dev *dev)
2186 {
2187 return readl(dev->mfc_regs->ret_instance_id);
2188 }
2189
2190 static int s5p_mfc_get_enc_dpb_count_v6(struct s5p_mfc_dev *dev)
2191 {
2192 return readl(dev->mfc_regs->e_num_dpb);
2193 }
2194
2195 static int s5p_mfc_get_enc_strm_size_v6(struct s5p_mfc_dev *dev)
2196 {
2197 return readl(dev->mfc_regs->e_stream_size);
2198 }
2199
2200 static int s5p_mfc_get_enc_slice_type_v6(struct s5p_mfc_dev *dev)
2201 {
2202 return readl(dev->mfc_regs->e_slice_type);
2203 }
2204
2205 static unsigned int s5p_mfc_get_pic_type_top_v6(struct s5p_mfc_ctx *ctx)
2206 {
2207 return s5p_mfc_read_info_v6(ctx,
2208 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_top);
2209 }
2210
2211 static unsigned int s5p_mfc_get_pic_type_bot_v6(struct s5p_mfc_ctx *ctx)
2212 {
2213 return s5p_mfc_read_info_v6(ctx,
2214 (__force unsigned long) ctx->dev->mfc_regs->d_ret_picture_tag_bot);
2215 }
2216
2217 static unsigned int s5p_mfc_get_crop_info_h_v6(struct s5p_mfc_ctx *ctx)
2218 {
2219 return s5p_mfc_read_info_v6(ctx,
2220 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info1);
2221 }
2222
2223 static unsigned int s5p_mfc_get_crop_info_v_v6(struct s5p_mfc_ctx *ctx)
2224 {
2225 return s5p_mfc_read_info_v6(ctx,
2226 (__force unsigned long) ctx->dev->mfc_regs->d_display_crop_info2);
2227 }
2228
2229 static struct s5p_mfc_regs mfc_regs;
2230
2231 /* Initialize registers for MFC v6 onwards */
2232 const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev)
2233 {
2234 memset(&mfc_regs, 0, sizeof(mfc_regs));
2235
2236 #define S5P_MFC_REG_ADDR(dev, reg) ((dev)->regs_base + (reg))
2237 #define R(m, r) mfc_regs.m = S5P_MFC_REG_ADDR(dev, r)
2238 /* codec common registers */
2239 R(risc_on, S5P_FIMV_RISC_ON_V6);
2240 R(risc2host_int, S5P_FIMV_RISC2HOST_INT_V6);
2241 R(host2risc_int, S5P_FIMV_HOST2RISC_INT_V6);
2242 R(risc_base_address, S5P_FIMV_RISC_BASE_ADDRESS_V6);
2243 R(mfc_reset, S5P_FIMV_MFC_RESET_V6);
2244 R(host2risc_command, S5P_FIMV_HOST2RISC_CMD_V6);
2245 R(risc2host_command, S5P_FIMV_RISC2HOST_CMD_V6);
2246 R(firmware_version, S5P_FIMV_FW_VERSION_V6);
2247 R(instance_id, S5P_FIMV_INSTANCE_ID_V6);
2248 R(codec_type, S5P_FIMV_CODEC_TYPE_V6);
2249 R(context_mem_addr, S5P_FIMV_CONTEXT_MEM_ADDR_V6);
2250 R(context_mem_size, S5P_FIMV_CONTEXT_MEM_SIZE_V6);
2251 R(pixel_format, S5P_FIMV_PIXEL_FORMAT_V6);
2252 R(ret_instance_id, S5P_FIMV_RET_INSTANCE_ID_V6);
2253 R(error_code, S5P_FIMV_ERROR_CODE_V6);
2254
2255 /* decoder registers */
2256 R(d_crc_ctrl, S5P_FIMV_D_CRC_CTRL_V6);
2257 R(d_dec_options, S5P_FIMV_D_DEC_OPTIONS_V6);
2258 R(d_display_delay, S5P_FIMV_D_DISPLAY_DELAY_V6);
2259 R(d_sei_enable, S5P_FIMV_D_SEI_ENABLE_V6);
2260 R(d_min_num_dpb, S5P_FIMV_D_MIN_NUM_DPB_V6);
2261 R(d_min_num_mv, S5P_FIMV_D_MIN_NUM_MV_V6);
2262 R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V6);
2263 R(d_num_dpb, S5P_FIMV_D_NUM_DPB_V6);
2264 R(d_num_mv, S5P_FIMV_D_NUM_MV_V6);
2265 R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V6);
2266 R(d_first_plane_dpb_size, S5P_FIMV_D_LUMA_DPB_SIZE_V6);
2267 R(d_second_plane_dpb_size, S5P_FIMV_D_CHROMA_DPB_SIZE_V6);
2268 R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V6);
2269 R(d_first_plane_dpb, S5P_FIMV_D_LUMA_DPB_V6);
2270 R(d_second_plane_dpb, S5P_FIMV_D_CHROMA_DPB_V6);
2271 R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V6);
2272 R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V6);
2273 R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V6);
2274 R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V6);
2275 R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V6);
2276 R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V6);
2277 R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V6);
2278 R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V6);
2279 R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V6);
2280 R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V6);
2281 R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V6);
2282 R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V6);
2283 R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_LUMA_ADDR_V6);
2284 R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_CHROMA_ADDR_V6);
2285 R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V6);
2286 R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V6);
2287 R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V6);
2288 R(d_display_aspect_ratio, S5P_FIMV_D_DISPLAY_ASPECT_RATIO_V6);
2289 R(d_display_extended_ar, S5P_FIMV_D_DISPLAY_EXTENDED_AR_V6);
2290 R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V6);
2291 R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_LUMA_ADDR_V6);
2292 R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_CHROMA_ADDR_V6);
2293 R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V6);
2294 R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V6);
2295 R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V6);
2296 R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V6);
2297 R(d_h264_info, S5P_FIMV_D_H264_INFO_V6);
2298 R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V6);
2299 R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V6);
2300
2301 /* encoder registers */
2302 R(e_frame_width, S5P_FIMV_E_FRAME_WIDTH_V6);
2303 R(e_frame_height, S5P_FIMV_E_FRAME_HEIGHT_V6);
2304 R(e_cropped_frame_width, S5P_FIMV_E_CROPPED_FRAME_WIDTH_V6);
2305 R(e_cropped_frame_height, S5P_FIMV_E_CROPPED_FRAME_HEIGHT_V6);
2306 R(e_frame_crop_offset, S5P_FIMV_E_FRAME_CROP_OFFSET_V6);
2307 R(e_enc_options, S5P_FIMV_E_ENC_OPTIONS_V6);
2308 R(e_picture_profile, S5P_FIMV_E_PICTURE_PROFILE_V6);
2309 R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V6);
2310 R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V6);
2311 R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V6);
2312 R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V6);
2313 R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V6);
2314 R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V6);
2315 R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V6);
2316 R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V6);
2317 R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V6);
2318 R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V6);
2319 R(e_num_dpb, S5P_FIMV_E_NUM_DPB_V6);
2320 R(e_luma_dpb, S5P_FIMV_E_LUMA_DPB_V6);
2321 R(e_chroma_dpb, S5P_FIMV_E_CHROMA_DPB_V6);
2322 R(e_me_buffer, S5P_FIMV_E_ME_BUFFER_V6);
2323 R(e_scratch_buffer_addr, S5P_FIMV_E_SCRATCH_BUFFER_ADDR_V6);
2324 R(e_scratch_buffer_size, S5P_FIMV_E_SCRATCH_BUFFER_SIZE_V6);
2325 R(e_tmv_buffer0, S5P_FIMV_E_TMV_BUFFER0_V6);
2326 R(e_tmv_buffer1, S5P_FIMV_E_TMV_BUFFER1_V6);
2327 R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_LUMA_ADDR_V6);
2328 R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_CHROMA_ADDR_V6);
2329 R(e_stream_buffer_addr, S5P_FIMV_E_STREAM_BUFFER_ADDR_V6);
2330 R(e_stream_buffer_size, S5P_FIMV_E_STREAM_BUFFER_SIZE_V6);
2331 R(e_roi_buffer_addr, S5P_FIMV_E_ROI_BUFFER_ADDR_V6);
2332 R(e_param_change, S5P_FIMV_E_PARAM_CHANGE_V6);
2333 R(e_ir_size, S5P_FIMV_E_IR_SIZE_V6);
2334 R(e_gop_config, S5P_FIMV_E_GOP_CONFIG_V6);
2335 R(e_mslice_mode, S5P_FIMV_E_MSLICE_MODE_V6);
2336 R(e_mslice_size_mb, S5P_FIMV_E_MSLICE_SIZE_MB_V6);
2337 R(e_mslice_size_bits, S5P_FIMV_E_MSLICE_SIZE_BITS_V6);
2338 R(e_frame_insertion, S5P_FIMV_E_FRAME_INSERTION_V6);
2339 R(e_rc_frame_rate, S5P_FIMV_E_RC_FRAME_RATE_V6);
2340 R(e_rc_bit_rate, S5P_FIMV_E_RC_BIT_RATE_V6);
2341 R(e_rc_roi_ctrl, S5P_FIMV_E_RC_ROI_CTRL_V6);
2342 R(e_picture_tag, S5P_FIMV_E_PICTURE_TAG_V6);
2343 R(e_bit_count_enable, S5P_FIMV_E_BIT_COUNT_ENABLE_V6);
2344 R(e_max_bit_count, S5P_FIMV_E_MAX_BIT_COUNT_V6);
2345 R(e_min_bit_count, S5P_FIMV_E_MIN_BIT_COUNT_V6);
2346 R(e_metadata_buffer_addr, S5P_FIMV_E_METADATA_BUFFER_ADDR_V6);
2347 R(e_metadata_buffer_size, S5P_FIMV_E_METADATA_BUFFER_SIZE_V6);
2348 R(e_encoded_source_first_plane_addr,
2349 S5P_FIMV_E_ENCODED_SOURCE_LUMA_ADDR_V6);
2350 R(e_encoded_source_second_plane_addr,
2351 S5P_FIMV_E_ENCODED_SOURCE_CHROMA_ADDR_V6);
2352 R(e_stream_size, S5P_FIMV_E_STREAM_SIZE_V6);
2353 R(e_slice_type, S5P_FIMV_E_SLICE_TYPE_V6);
2354 R(e_picture_count, S5P_FIMV_E_PICTURE_COUNT_V6);
2355 R(e_ret_picture_tag, S5P_FIMV_E_RET_PICTURE_TAG_V6);
2356 R(e_recon_luma_dpb_addr, S5P_FIMV_E_RECON_LUMA_DPB_ADDR_V6);
2357 R(e_recon_chroma_dpb_addr, S5P_FIMV_E_RECON_CHROMA_DPB_ADDR_V6);
2358 R(e_mpeg4_options, S5P_FIMV_E_MPEG4_OPTIONS_V6);
2359 R(e_mpeg4_hec_period, S5P_FIMV_E_MPEG4_HEC_PERIOD_V6);
2360 R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V6);
2361 R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V6);
2362 R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V6);
2363 R(e_h264_lf_alpha_offset, S5P_FIMV_E_H264_LF_ALPHA_OFFSET_V6);
2364 R(e_h264_lf_beta_offset, S5P_FIMV_E_H264_LF_BETA_OFFSET_V6);
2365 R(e_h264_i_period, S5P_FIMV_E_H264_I_PERIOD_V6);
2366 R(e_h264_fmo_slice_grp_map_type,
2367 S5P_FIMV_E_H264_FMO_SLICE_GRP_MAP_TYPE_V6);
2368 R(e_h264_fmo_num_slice_grp_minus1,
2369 S5P_FIMV_E_H264_FMO_NUM_SLICE_GRP_MINUS1_V6);
2370 R(e_h264_fmo_slice_grp_change_dir,
2371 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_DIR_V6);
2372 R(e_h264_fmo_slice_grp_change_rate_minus1,
2373 S5P_FIMV_E_H264_FMO_SLICE_GRP_CHANGE_RATE_MINUS1_V6);
2374 R(e_h264_fmo_run_length_minus1_0,
2375 S5P_FIMV_E_H264_FMO_RUN_LENGTH_MINUS1_0_V6);
2376 R(e_h264_aso_slice_order_0, S5P_FIMV_E_H264_ASO_SLICE_ORDER_0_V6);
2377 R(e_h264_num_t_layer, S5P_FIMV_E_H264_NUM_T_LAYER_V6);
2378 R(e_h264_hierarchical_qp_layer0,
2379 S5P_FIMV_E_H264_HIERARCHICAL_QP_LAYER0_V6);
2380 R(e_h264_frame_packing_sei_info,
2381 S5P_FIMV_E_H264_FRAME_PACKING_SEI_INFO_V6);
2382
2383 if (!IS_MFCV7_PLUS(dev))
2384 goto done;
2385
2386 /* Initialize registers used in MFC v7+ */
2387 R(e_source_first_plane_addr, S5P_FIMV_E_SOURCE_FIRST_ADDR_V7);
2388 R(e_source_second_plane_addr, S5P_FIMV_E_SOURCE_SECOND_ADDR_V7);
2389 R(e_source_third_plane_addr, S5P_FIMV_E_SOURCE_THIRD_ADDR_V7);
2390 R(e_source_first_plane_stride, S5P_FIMV_E_SOURCE_FIRST_STRIDE_V7);
2391 R(e_source_second_plane_stride, S5P_FIMV_E_SOURCE_SECOND_STRIDE_V7);
2392 R(e_source_third_plane_stride, S5P_FIMV_E_SOURCE_THIRD_STRIDE_V7);
2393 R(e_encoded_source_first_plane_addr,
2394 S5P_FIMV_E_ENCODED_SOURCE_FIRST_ADDR_V7);
2395 R(e_encoded_source_second_plane_addr,
2396 S5P_FIMV_E_ENCODED_SOURCE_SECOND_ADDR_V7);
2397 R(e_vp8_options, S5P_FIMV_E_VP8_OPTIONS_V7);
2398
2399 if (!IS_MFCV8_PLUS(dev))
2400 goto done;
2401
2402 /* Initialize registers used in MFC v8 only.
2403 * Also, over-write the registers which have
2404 * a different offset for MFC v8. */
2405 R(d_stream_data_size, S5P_FIMV_D_STREAM_DATA_SIZE_V8);
2406 R(d_cpb_buffer_addr, S5P_FIMV_D_CPB_BUFFER_ADDR_V8);
2407 R(d_cpb_buffer_size, S5P_FIMV_D_CPB_BUFFER_SIZE_V8);
2408 R(d_cpb_buffer_offset, S5P_FIMV_D_CPB_BUFFER_OFFSET_V8);
2409 R(d_first_plane_dpb_size, S5P_FIMV_D_FIRST_PLANE_DPB_SIZE_V8);
2410 R(d_second_plane_dpb_size, S5P_FIMV_D_SECOND_PLANE_DPB_SIZE_V8);
2411 R(d_scratch_buffer_addr, S5P_FIMV_D_SCRATCH_BUFFER_ADDR_V8);
2412 R(d_scratch_buffer_size, S5P_FIMV_D_SCRATCH_BUFFER_SIZE_V8);
2413 R(d_first_plane_dpb_stride_size,
2414 S5P_FIMV_D_FIRST_PLANE_DPB_STRIDE_SIZE_V8);
2415 R(d_second_plane_dpb_stride_size,
2416 S5P_FIMV_D_SECOND_PLANE_DPB_STRIDE_SIZE_V8);
2417 R(d_mv_buffer_size, S5P_FIMV_D_MV_BUFFER_SIZE_V8);
2418 R(d_num_mv, S5P_FIMV_D_NUM_MV_V8);
2419 R(d_first_plane_dpb, S5P_FIMV_D_FIRST_PLANE_DPB_V8);
2420 R(d_second_plane_dpb, S5P_FIMV_D_SECOND_PLANE_DPB_V8);
2421 R(d_mv_buffer, S5P_FIMV_D_MV_BUFFER_V8);
2422 R(d_init_buffer_options, S5P_FIMV_D_INIT_BUFFER_OPTIONS_V8);
2423 R(d_available_dpb_flag_lower, S5P_FIMV_D_AVAILABLE_DPB_FLAG_LOWER_V8);
2424 R(d_slice_if_enable, S5P_FIMV_D_SLICE_IF_ENABLE_V8);
2425 R(d_display_first_plane_addr, S5P_FIMV_D_DISPLAY_FIRST_PLANE_ADDR_V8);
2426 R(d_display_second_plane_addr, S5P_FIMV_D_DISPLAY_SECOND_PLANE_ADDR_V8);
2427 R(d_decoded_first_plane_addr, S5P_FIMV_D_DECODED_FIRST_PLANE_ADDR_V8);
2428 R(d_decoded_second_plane_addr, S5P_FIMV_D_DECODED_SECOND_PLANE_ADDR_V8);
2429 R(d_display_status, S5P_FIMV_D_DISPLAY_STATUS_V8);
2430 R(d_decoded_status, S5P_FIMV_D_DECODED_STATUS_V8);
2431 R(d_decoded_frame_type, S5P_FIMV_D_DECODED_FRAME_TYPE_V8);
2432 R(d_display_frame_type, S5P_FIMV_D_DISPLAY_FRAME_TYPE_V8);
2433 R(d_decoded_nal_size, S5P_FIMV_D_DECODED_NAL_SIZE_V8);
2434 R(d_display_frame_width, S5P_FIMV_D_DISPLAY_FRAME_WIDTH_V8);
2435 R(d_display_frame_height, S5P_FIMV_D_DISPLAY_FRAME_HEIGHT_V8);
2436 R(d_frame_pack_sei_avail, S5P_FIMV_D_FRAME_PACK_SEI_AVAIL_V8);
2437 R(d_mvc_num_views, S5P_FIMV_D_MVC_NUM_VIEWS_V8);
2438 R(d_mvc_view_id, S5P_FIMV_D_MVC_VIEW_ID_V8);
2439 R(d_ret_picture_tag_top, S5P_FIMV_D_RET_PICTURE_TAG_TOP_V8);
2440 R(d_ret_picture_tag_bot, S5P_FIMV_D_RET_PICTURE_TAG_BOT_V8);
2441 R(d_display_crop_info1, S5P_FIMV_D_DISPLAY_CROP_INFO1_V8);
2442 R(d_display_crop_info2, S5P_FIMV_D_DISPLAY_CROP_INFO2_V8);
2443 R(d_min_scratch_buffer_size, S5P_FIMV_D_MIN_SCRATCH_BUFFER_SIZE_V8);
2444
2445 /* encoder registers */
2446 R(e_padding_ctrl, S5P_FIMV_E_PADDING_CTRL_V8);
2447 R(e_rc_config, S5P_FIMV_E_RC_CONFIG_V8);
2448 R(e_rc_mode, S5P_FIMV_E_RC_RPARAM_V8);
2449 R(e_mv_hor_range, S5P_FIMV_E_MV_HOR_RANGE_V8);
2450 R(e_mv_ver_range, S5P_FIMV_E_MV_VER_RANGE_V8);
2451 R(e_rc_qp_bound, S5P_FIMV_E_RC_QP_BOUND_V8);
2452 R(e_fixed_picture_qp, S5P_FIMV_E_FIXED_PICTURE_QP_V8);
2453 R(e_vbv_buffer_size, S5P_FIMV_E_VBV_BUFFER_SIZE_V8);
2454 R(e_vbv_init_delay, S5P_FIMV_E_VBV_INIT_DELAY_V8);
2455 R(e_mb_rc_config, S5P_FIMV_E_MB_RC_CONFIG_V8);
2456 R(e_aspect_ratio, S5P_FIMV_E_ASPECT_RATIO_V8);
2457 R(e_extended_sar, S5P_FIMV_E_EXTENDED_SAR_V8);
2458 R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8);
2459 R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8);
2460
2461 if (!IS_MFCV10(dev))
2462 goto done;
2463
2464 /* Initialize registers used in MFC v10 only.
2465 * Also, over-write the registers which have
2466 * a different offset for MFC v10.
2467 */
2468
2469 /* decoder registers */
2470 R(d_static_buffer_addr, S5P_FIMV_D_STATIC_BUFFER_ADDR_V10);
2471 R(d_static_buffer_size, S5P_FIMV_D_STATIC_BUFFER_SIZE_V10);
2472
2473 /* encoder registers */
2474 R(e_num_t_layer, S5P_FIMV_E_NUM_T_LAYER_V10);
2475 R(e_hier_qp_layer0, S5P_FIMV_E_HIERARCHICAL_QP_LAYER0_V10);
2476 R(e_hier_bit_rate_layer0, S5P_FIMV_E_HIERARCHICAL_BIT_RATE_LAYER0_V10);
2477 R(e_hevc_options, S5P_FIMV_E_HEVC_OPTIONS_V10);
2478 R(e_hevc_refresh_period, S5P_FIMV_E_HEVC_REFRESH_PERIOD_V10);
2479 R(e_hevc_lf_beta_offset_div2, S5P_FIMV_E_HEVC_LF_BETA_OFFSET_DIV2_V10);
2480 R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10);
2481 R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10);
2482
2483 done:
2484 return &mfc_regs;
2485 #undef S5P_MFC_REG_ADDR
2486 #undef R
2487 }
2488
2489 /* Initialize opr function pointers for MFC v6 */
2490 static struct s5p_mfc_hw_ops s5p_mfc_ops_v6 = {
2491 .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v6,
2492 .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v6,
2493 .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v6,
2494 .release_codec_buffers = s5p_mfc_release_codec_buffers_v6,
2495 .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v6,
2496 .release_instance_buffer = s5p_mfc_release_instance_buffer_v6,
2497 .alloc_dev_context_buffer =
2498 s5p_mfc_alloc_dev_context_buffer_v6,
2499 .release_dev_context_buffer =
2500 s5p_mfc_release_dev_context_buffer_v6,
2501 .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v6,
2502 .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v6,
2503 .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v6,
2504 .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v6,
2505 .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v6,
2506 .try_run = s5p_mfc_try_run_v6,
2507 .clear_int_flags = s5p_mfc_clear_int_flags_v6,
2508 .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v6,
2509 .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v6,
2510 .get_dspl_status = s5p_mfc_get_dspl_status_v6,
2511 .get_dec_status = s5p_mfc_get_dec_status_v6,
2512 .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v6,
2513 .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v6,
2514 .get_consumed_stream = s5p_mfc_get_consumed_stream_v6,
2515 .get_int_reason = s5p_mfc_get_int_reason_v6,
2516 .get_int_err = s5p_mfc_get_int_err_v6,
2517 .err_dec = s5p_mfc_err_dec_v6,
2518 .get_img_width = s5p_mfc_get_img_width_v6,
2519 .get_img_height = s5p_mfc_get_img_height_v6,
2520 .get_dpb_count = s5p_mfc_get_dpb_count_v6,
2521 .get_mv_count = s5p_mfc_get_mv_count_v6,
2522 .get_inst_no = s5p_mfc_get_inst_no_v6,
2523 .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v6,
2524 .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v6,
2525 .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v6,
2526 .get_pic_type_top = s5p_mfc_get_pic_type_top_v6,
2527 .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v6,
2528 .get_crop_info_h = s5p_mfc_get_crop_info_h_v6,
2529 .get_crop_info_v = s5p_mfc_get_crop_info_v_v6,
2530 .get_min_scratch_buf_size = s5p_mfc_get_min_scratch_buf_size,
2531 .get_e_min_scratch_buf_size = s5p_mfc_get_e_min_scratch_buf_size,
2532 };
2533
2534 struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v6(void)
2535 {
2536 return &s5p_mfc_ops_v6;
2537 }
Linux with added FPC-III support