drivers/media/platform/ti-vpe/sc.h

   1 /*
   2  * Copyright (c) 2013 Texas Instruments Inc.
   3  *
   4  * David Griego, <dagriego@biglakesoftware.com>
   5  * Dale Farnsworth, <dale@farnsworth.org>
   6  * Archit Taneja, <archit@ti.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms of the GNU General Public License version 2 as published by
  10  * the Free Software Foundation.
  11  */
  12 #ifndef TI_SC_H
  13 #define TI_SC_H
  14
  15 /* Scaler regs */
  16 #define CFG_SC0                         0x0
  17 #define CFG_INTERLACE_O                 (1 << 0)
  18 #define CFG_LINEAR                      (1 << 1)
  19 #define CFG_SC_BYPASS                   (1 << 2)
  20 #define CFG_INVT_FID                    (1 << 3)
  21 #define CFG_USE_RAV                     (1 << 4)
  22 #define CFG_ENABLE_EV                   (1 << 5)
  23 #define CFG_AUTO_HS                     (1 << 6)
  24 #define CFG_DCM_2X                      (1 << 7)
  25 #define CFG_DCM_4X                      (1 << 8)
  26 #define CFG_HP_BYPASS                   (1 << 9)
  27 #define CFG_INTERLACE_I                 (1 << 10)
  28 #define CFG_ENABLE_SIN2_VER_INTP        (1 << 11)
  29 #define CFG_Y_PK_EN                     (1 << 14)
  30 #define CFG_TRIM                        (1 << 15)
  31 #define CFG_SELFGEN_FID                 (1 << 16)
  32
  33 #define CFG_SC1                         0x4
  34 #define CFG_ROW_ACC_INC_MASK            0x07ffffff
  35 #define CFG_ROW_ACC_INC_SHIFT           0
  36
  37 #define CFG_SC2                         0x08
  38 #define CFG_ROW_ACC_OFFSET_MASK         0x0fffffff
  39 #define CFG_ROW_ACC_OFFSET_SHIFT        0
  40
  41 #define CFG_SC3                         0x0c
  42 #define CFG_ROW_ACC_OFFSET_B_MASK       0x0fffffff
  43 #define CFG_ROW_ACC_OFFSET_B_SHIFT      0
  44
  45 #define CFG_SC4                         0x10
  46 #define CFG_TAR_H_MASK                  0x07ff
  47 #define CFG_TAR_H_SHIFT                 0
  48 #define CFG_TAR_W_MASK                  0x07ff
  49 #define CFG_TAR_W_SHIFT                 12
  50 #define CFG_LIN_ACC_INC_U_MASK          0x07
  51 #define CFG_LIN_ACC_INC_U_SHIFT         24
  52 #define CFG_NLIN_ACC_INIT_U_MASK        0x07
  53 #define CFG_NLIN_ACC_INIT_U_SHIFT       28
  54
  55 #define CFG_SC5                         0x14
  56 #define CFG_SRC_H_MASK                  0x07ff
  57 #define CFG_SRC_H_SHIFT                 0
  58 #define CFG_SRC_W_MASK                  0x07ff
  59 #define CFG_SRC_W_SHIFT                 12
  60 #define CFG_NLIN_ACC_INC_U_MASK         0x07
  61 #define CFG_NLIN_ACC_INC_U_SHIFT        24
  62
  63 #define CFG_SC6                         0x18
  64 #define CFG_ROW_ACC_INIT_RAV_MASK       0x03ff
  65 #define CFG_ROW_ACC_INIT_RAV_SHIFT      0
  66 #define CFG_ROW_ACC_INIT_RAV_B_MASK     0x03ff
  67 #define CFG_ROW_ACC_INIT_RAV_B_SHIFT    10
  68
  69 #define CFG_SC8                         0x20
  70 #define CFG_NLIN_LEFT_MASK              0x07ff
  71 #define CFG_NLIN_LEFT_SHIFT             0
  72 #define CFG_NLIN_RIGHT_MASK             0x07ff
  73 #define CFG_NLIN_RIGHT_SHIFT            12
  74
  75 #define CFG_SC9                         0x24
  76 #define CFG_LIN_ACC_INC                 CFG_SC9
  77
  78 #define CFG_SC10                        0x28
  79 #define CFG_NLIN_ACC_INIT               CFG_SC10
  80
  81 #define CFG_SC11                        0x2c
  82 #define CFG_NLIN_ACC_INC                CFG_SC11
  83
  84 #define CFG_SC12                        0x30
  85 #define CFG_COL_ACC_OFFSET_MASK         0x01ffffff
  86 #define CFG_COL_ACC_OFFSET_SHIFT        0
  87
  88 #define CFG_SC13                        0x34
  89 #define CFG_SC_FACTOR_RAV_MASK          0xff
  90 #define CFG_SC_FACTOR_RAV_SHIFT         0
  91 #define CFG_CHROMA_INTP_THR_MASK        0x03ff
  92 #define CFG_CHROMA_INTP_THR_SHIFT       12
  93 #define CFG_DELTA_CHROMA_THR_MASK       0x0f
  94 #define CFG_DELTA_CHROMA_THR_SHIFT      24
  95
  96 #define CFG_SC17                        0x44
  97 #define CFG_EV_THR_MASK                 0x03ff
  98 #define CFG_EV_THR_SHIFT                12
  99 #define CFG_DELTA_LUMA_THR_MASK         0x0f
 100 #define CFG_DELTA_LUMA_THR_SHIFT        24
 101 #define CFG_DELTA_EV_THR_MASK           0x0f
 102 #define CFG_DELTA_EV_THR_SHIFT          28
 103
 104 #define CFG_SC18                        0x48
 105 #define CFG_HS_FACTOR_MASK              0x03ff
 106 #define CFG_HS_FACTOR_SHIFT             0
 107 #define CFG_CONF_DEFAULT_MASK           0x01ff
 108 #define CFG_CONF_DEFAULT_SHIFT          16
 109
 110 #define CFG_SC19                        0x4c
 111 #define CFG_HPF_COEFF0_MASK             0xff
 112 #define CFG_HPF_COEFF0_SHIFT            0
 113 #define CFG_HPF_COEFF1_MASK             0xff
 114 #define CFG_HPF_COEFF1_SHIFT            8
 115 #define CFG_HPF_COEFF2_MASK             0xff
 116 #define CFG_HPF_COEFF2_SHIFT            16
 117 #define CFG_HPF_COEFF3_MASK             0xff
 118 #define CFG_HPF_COEFF3_SHIFT            23
 119
 120 #define CFG_SC20                        0x50
 121 #define CFG_HPF_COEFF4_MASK             0xff
 122 #define CFG_HPF_COEFF4_SHIFT            0
 123 #define CFG_HPF_COEFF5_MASK             0xff
 124 #define CFG_HPF_COEFF5_SHIFT            8
 125 #define CFG_HPF_NORM_SHIFT_MASK         0x07
 126 #define CFG_HPF_NORM_SHIFT_SHIFT        16
 127 #define CFG_NL_LIMIT_MASK               0x1ff
 128 #define CFG_NL_LIMIT_SHIFT              20
 129
 130 #define CFG_SC21                        0x54
 131 #define CFG_NL_LO_THR_MASK              0x01ff
 132 #define CFG_NL_LO_THR_SHIFT             0
 133 #define CFG_NL_LO_SLOPE_MASK            0xff
 134 #define CFG_NL_LO_SLOPE_SHIFT           16
 135
 136 #define CFG_SC22                        0x58
 137 #define CFG_NL_HI_THR_MASK              0x01ff
 138 #define CFG_NL_HI_THR_SHIFT             0
 139 #define CFG_NL_HI_SLOPE_SH_MASK         0x07
 140 #define CFG_NL_HI_SLOPE_SH_SHIFT        16
 141
 142 #define CFG_SC23                        0x5c
 143 #define CFG_GRADIENT_THR_MASK           0x07ff
 144 #define CFG_GRADIENT_THR_SHIFT          0
 145 #define CFG_GRADIENT_THR_RANGE_MASK     0x0f
 146 #define CFG_GRADIENT_THR_RANGE_SHIFT    12
 147 #define CFG_MIN_GY_THR_MASK             0xff
 148 #define CFG_MIN_GY_THR_SHIFT            16
 149 #define CFG_MIN_GY_THR_RANGE_MASK       0x0f
 150 #define CFG_MIN_GY_THR_RANGE_SHIFT      28
 151
 152 #define CFG_SC24                        0x60
 153 #define CFG_ORG_H_MASK                  0x07ff
 154 #define CFG_ORG_H_SHIFT                 0
 155 #define CFG_ORG_W_MASK                  0x07ff
 156 #define CFG_ORG_W_SHIFT                 16
 157
 158 #define CFG_SC25                        0x64
 159 #define CFG_OFF_H_MASK                  0x07ff
 160 #define CFG_OFF_H_SHIFT                 0
 161 #define CFG_OFF_W_MASK                  0x07ff
 162 #define CFG_OFF_W_SHIFT                 16
 163
 164 /* number of phases supported by the polyphase scalers */
 165 #define SC_NUM_PHASES                   32
 166
 167 /* number of taps used by horizontal polyphase scaler */
 168 #define SC_H_NUM_TAPS                   7
 169
 170 /* number of taps used by vertical polyphase scaler */
 171 #define SC_V_NUM_TAPS                   5
 172
 173 /* number of taps expected by the scaler in it's coefficient memory */
 174 #define SC_NUM_TAPS_MEM_ALIGN           8
 175
 176 /* Maximum frame width the scaler can handle (in pixels) */
 177 #define SC_MAX_PIXEL_WIDTH              2047
 178
 179 /* Maximum frame height the scaler can handle (in lines) */
 180 #define SC_MAX_PIXEL_HEIGHT             2047
 181
 182 /*
 183  * coefficient memory size in bytes:
 184  * num phases x num sets(luma and chroma) x num taps(aligned) x coeff size
 185  */
 186 #define SC_COEF_SRAM_SIZE       (SC_NUM_PHASES * 2 * SC_NUM_TAPS_MEM_ALIGN * 2)
 187
 188 struct sc_data {
 189         void __iomem            *base;
 190         struct resource         *res;
 191
 192         dma_addr_t              loaded_coeff_h; /* loaded h coeffs in SC */
 193         dma_addr_t              loaded_coeff_v; /* loaded v coeffs in SC */
 194
 195         bool                    load_coeff_h;   /* have new h SC coeffs */
 196         bool                    load_coeff_v;   /* have new v SC coeffs */
 197
 198         struct platform_device *pdev;
 199 };
 200
 201 void sc_dump_regs(struct sc_data *sc);
 202 void sc_set_hs_coeffs(struct sc_data *sc, void *addr, unsigned int src_w,
 203                 unsigned int dst_w);
 204 void sc_set_vs_coeffs(struct sc_data *sc, void *addr, unsigned int src_h,
 205                 unsigned int dst_h);
 206 void sc_config_scaler(struct sc_data *sc, u32 *sc_reg0, u32 *sc_reg8,
 207                 u32 *sc_reg17, unsigned int src_w, unsigned int src_h,
 208                 unsigned int dst_w, unsigned int dst_h);
 209 struct sc_data *sc_create(struct platform_device *pdev, const char *res_name);
 210
 211 #endif