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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / media / platform / ti-vpe / vpe.c
blobd70871d0ad2d9654fbf02f7b1977aa2a4e8a7aa3
1 /*
2 * TI VPE mem2mem driver, based on the virtual v4l2-mem2mem example driver
3 *
4 * Copyright (c) 2013 Texas Instruments Inc.
5 * David Griego, <dagriego@biglakesoftware.com>
6 * Dale Farnsworth, <dale@farnsworth.org>
7 * Archit Taneja, <archit@ti.com>
8 *
9 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
10 * Pawel Osciak, <pawel@osciak.com>
11 * Marek Szyprowski, <m.szyprowski@samsung.com>
12 *
13 * Based on the virtual v4l2-mem2mem example device
14 *
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License version 2 as published by
17 * the Free Software Foundation
18 */
19
20 #include <linux/delay.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/err.h>
23 #include <linux/fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/ioctl.h>
27 #include <linux/module.h>
28 #include <linux/of.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/videodev2.h>
34 #include <linux/log2.h>
35 #include <linux/sizes.h>
36
37 #include <media/v4l2-common.h>
38 #include <media/v4l2-ctrls.h>
39 #include <media/v4l2-device.h>
40 #include <media/v4l2-event.h>
41 #include <media/v4l2-ioctl.h>
42 #include <media/v4l2-mem2mem.h>
43 #include <media/videobuf2-v4l2.h>
44 #include <media/videobuf2-dma-contig.h>
45
46 #include "vpdma.h"
47 #include "vpdma_priv.h"
48 #include "vpe_regs.h"
49 #include "sc.h"
50 #include "csc.h"
51
52 #define VPE_MODULE_NAME "vpe"
53
54 /* minimum and maximum frame sizes */
55 #define MIN_W 32
56 #define MIN_H 32
57 #define MAX_W 2048
58 #define MAX_H 1184
59
60 /* required alignments */
61 #define S_ALIGN 0 /* multiple of 1 */
62 #define H_ALIGN 1 /* multiple of 2 */
63
64 /* flags that indicate a format can be used for capture/output */
65 #define VPE_FMT_TYPE_CAPTURE (1 << 0)
66 #define VPE_FMT_TYPE_OUTPUT (1 << 1)
67
68 /* used as plane indices */
69 #define VPE_MAX_PLANES 2
70 #define VPE_LUMA 0
71 #define VPE_CHROMA 1
72
73 /* per m2m context info */
74 #define VPE_MAX_SRC_BUFS 3 /* need 3 src fields to de-interlace */
75
76 #define VPE_DEF_BUFS_PER_JOB 1 /* default one buffer per batch job */
77
78 /*
79 * each VPE context can need up to 3 config descriptors, 7 input descriptors,
80 * 3 output descriptors, and 10 control descriptors
81 */
82 #define VPE_DESC_LIST_SIZE (10 * VPDMA_DTD_DESC_SIZE + \
83 13 * VPDMA_CFD_CTD_DESC_SIZE)
84
85 #define vpe_dbg(vpedev, fmt, arg...) \
86 dev_dbg((vpedev)->v4l2_dev.dev, fmt, ##arg)
87 #define vpe_err(vpedev, fmt, arg...) \
88 dev_err((vpedev)->v4l2_dev.dev, fmt, ##arg)
89
90 struct vpe_us_coeffs {
91 unsigned short anchor_fid0_c0;
92 unsigned short anchor_fid0_c1;
93 unsigned short anchor_fid0_c2;
94 unsigned short anchor_fid0_c3;
95 unsigned short interp_fid0_c0;
96 unsigned short interp_fid0_c1;
97 unsigned short interp_fid0_c2;
98 unsigned short interp_fid0_c3;
99 unsigned short anchor_fid1_c0;
100 unsigned short anchor_fid1_c1;
101 unsigned short anchor_fid1_c2;
102 unsigned short anchor_fid1_c3;
103 unsigned short interp_fid1_c0;
104 unsigned short interp_fid1_c1;
105 unsigned short interp_fid1_c2;
106 unsigned short interp_fid1_c3;
107 };
108
109 /*
110 * Default upsampler coefficients
111 */
112 static const struct vpe_us_coeffs us_coeffs[] = {
113 {
114 /* Coefficients for progressive input */
115 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
116 0x00C8, 0x0348, 0x0018, 0x3FD8, 0x3FB8, 0x0378, 0x00E8, 0x3FE8,
117 },
118 {
119 /* Coefficients for Top Field Interlaced input */
120 0x0051, 0x03D5, 0x3FE3, 0x3FF7, 0x3FB5, 0x02E9, 0x018F, 0x3FD3,
121 /* Coefficients for Bottom Field Interlaced input */
122 0x016B, 0x0247, 0x00B1, 0x3F9D, 0x3FCF, 0x03DB, 0x005D, 0x3FF9,
123 },
124 };
125
126 /*
127 * the following registers are for configuring some of the parameters of the
128 * motion and edge detection blocks inside DEI, these generally remain the same,
129 * these could be passed later via userspace if some one needs to tweak these.
130 */
131 struct vpe_dei_regs {
132 unsigned long mdt_spacial_freq_thr_reg; /* VPE_DEI_REG2 */
133 unsigned long edi_config_reg; /* VPE_DEI_REG3 */
134 unsigned long edi_lut_reg0; /* VPE_DEI_REG4 */
135 unsigned long edi_lut_reg1; /* VPE_DEI_REG5 */
136 unsigned long edi_lut_reg2; /* VPE_DEI_REG6 */
137 unsigned long edi_lut_reg3; /* VPE_DEI_REG7 */
138 };
139
140 /*
141 * default expert DEI register values, unlikely to be modified.
142 */
143 static const struct vpe_dei_regs dei_regs = {
144 .mdt_spacial_freq_thr_reg = 0x020C0804u,
145 .edi_config_reg = 0x0118100Cu,
146 .edi_lut_reg0 = 0x08040200u,
147 .edi_lut_reg1 = 0x1010100Cu,
148 .edi_lut_reg2 = 0x10101010u,
149 .edi_lut_reg3 = 0x10101010u,
150 };
151
152 /*
153 * The port_data structure contains per-port data.
154 */
155 struct vpe_port_data {
156 enum vpdma_channel channel; /* VPDMA channel */
157 u8 vb_index; /* input frame f, f-1, f-2 index */
158 u8 vb_part; /* plane index for co-panar formats */
159 };
160
161 /*
162 * Define indices into the port_data tables
163 */
164 #define VPE_PORT_LUMA1_IN 0
165 #define VPE_PORT_CHROMA1_IN 1
166 #define VPE_PORT_LUMA2_IN 2
167 #define VPE_PORT_CHROMA2_IN 3
168 #define VPE_PORT_LUMA3_IN 4
169 #define VPE_PORT_CHROMA3_IN 5
170 #define VPE_PORT_MV_IN 6
171 #define VPE_PORT_MV_OUT 7
172 #define VPE_PORT_LUMA_OUT 8
173 #define VPE_PORT_CHROMA_OUT 9
174 #define VPE_PORT_RGB_OUT 10
175
176 static const struct vpe_port_data port_data[11] = {
177 [VPE_PORT_LUMA1_IN] = {
178 .channel = VPE_CHAN_LUMA1_IN,
179 .vb_index = 0,
180 .vb_part = VPE_LUMA,
181 },
182 [VPE_PORT_CHROMA1_IN] = {
183 .channel = VPE_CHAN_CHROMA1_IN,
184 .vb_index = 0,
185 .vb_part = VPE_CHROMA,
186 },
187 [VPE_PORT_LUMA2_IN] = {
188 .channel = VPE_CHAN_LUMA2_IN,
189 .vb_index = 1,
190 .vb_part = VPE_LUMA,
191 },
192 [VPE_PORT_CHROMA2_IN] = {
193 .channel = VPE_CHAN_CHROMA2_IN,
194 .vb_index = 1,
195 .vb_part = VPE_CHROMA,
196 },
197 [VPE_PORT_LUMA3_IN] = {
198 .channel = VPE_CHAN_LUMA3_IN,
199 .vb_index = 2,
200 .vb_part = VPE_LUMA,
201 },
202 [VPE_PORT_CHROMA3_IN] = {
203 .channel = VPE_CHAN_CHROMA3_IN,
204 .vb_index = 2,
205 .vb_part = VPE_CHROMA,
206 },
207 [VPE_PORT_MV_IN] = {
208 .channel = VPE_CHAN_MV_IN,
209 },
210 [VPE_PORT_MV_OUT] = {
211 .channel = VPE_CHAN_MV_OUT,
212 },
213 [VPE_PORT_LUMA_OUT] = {
214 .channel = VPE_CHAN_LUMA_OUT,
215 .vb_part = VPE_LUMA,
216 },
217 [VPE_PORT_CHROMA_OUT] = {
218 .channel = VPE_CHAN_CHROMA_OUT,
219 .vb_part = VPE_CHROMA,
220 },
221 [VPE_PORT_RGB_OUT] = {
222 .channel = VPE_CHAN_RGB_OUT,
223 .vb_part = VPE_LUMA,
224 },
225 };
226
227
228 /* driver info for each of the supported video formats */
229 struct vpe_fmt {
230 char *name; /* human-readable name */
231 u32 fourcc; /* standard format identifier */
232 u8 types; /* CAPTURE and/or OUTPUT */
233 u8 coplanar; /* set for unpacked Luma and Chroma */
234 /* vpdma format info for each plane */
235 struct vpdma_data_format const *vpdma_fmt[VPE_MAX_PLANES];
236 };
237
238 static struct vpe_fmt vpe_formats[] = {
239 {
240 .name = "NV16 YUV 422 co-planar",
241 .fourcc = V4L2_PIX_FMT_NV16,
242 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
243 .coplanar = 1,
244 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y444],
245 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C444],
246 },
247 },
248 {
249 .name = "NV12 YUV 420 co-planar",
250 .fourcc = V4L2_PIX_FMT_NV12,
251 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
252 .coplanar = 1,
253 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_Y420],
254 &vpdma_yuv_fmts[VPDMA_DATA_FMT_C420],
255 },
256 },
257 {
258 .name = "YUYV 422 packed",
259 .fourcc = V4L2_PIX_FMT_YUYV,
260 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
261 .coplanar = 0,
262 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_YCB422],
263 },
264 },
265 {
266 .name = "UYVY 422 packed",
267 .fourcc = V4L2_PIX_FMT_UYVY,
268 .types = VPE_FMT_TYPE_CAPTURE | VPE_FMT_TYPE_OUTPUT,
269 .coplanar = 0,
270 .vpdma_fmt = { &vpdma_yuv_fmts[VPDMA_DATA_FMT_CBY422],
271 },
272 },
273 {
274 .name = "RGB888 packed",
275 .fourcc = V4L2_PIX_FMT_RGB24,
276 .types = VPE_FMT_TYPE_CAPTURE,
277 .coplanar = 0,
278 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB24],
279 },
280 },
281 {
282 .name = "ARGB32",
283 .fourcc = V4L2_PIX_FMT_RGB32,
284 .types = VPE_FMT_TYPE_CAPTURE,
285 .coplanar = 0,
286 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ARGB32],
287 },
288 },
289 {
290 .name = "BGR888 packed",
291 .fourcc = V4L2_PIX_FMT_BGR24,
292 .types = VPE_FMT_TYPE_CAPTURE,
293 .coplanar = 0,
294 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_BGR24],
295 },
296 },
297 {
298 .name = "ABGR32",
299 .fourcc = V4L2_PIX_FMT_BGR32,
300 .types = VPE_FMT_TYPE_CAPTURE,
301 .coplanar = 0,
302 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_ABGR32],
303 },
304 },
305 {
306 .name = "RGB565",
307 .fourcc = V4L2_PIX_FMT_RGB565,
308 .types = VPE_FMT_TYPE_CAPTURE,
309 .coplanar = 0,
310 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGB565],
311 },
312 },
313 {
314 .name = "RGB5551",
315 .fourcc = V4L2_PIX_FMT_RGB555,
316 .types = VPE_FMT_TYPE_CAPTURE,
317 .coplanar = 0,
318 .vpdma_fmt = { &vpdma_rgb_fmts[VPDMA_DATA_FMT_RGBA16_5551],
319 },
320 },
321 };
322
323 /*
324 * per-queue, driver-specific private data.
325 * there is one source queue and one destination queue for each m2m context.
326 */
327 struct vpe_q_data {
328 unsigned int width; /* frame width */
329 unsigned int height; /* frame height */
330 unsigned int nplanes; /* Current number of planes */
331 unsigned int bytesperline[VPE_MAX_PLANES]; /* bytes per line in memory */
332 enum v4l2_colorspace colorspace;
333 enum v4l2_field field; /* supported field value */
334 unsigned int flags;
335 unsigned int sizeimage[VPE_MAX_PLANES]; /* image size in memory */
336 struct v4l2_rect c_rect; /* crop/compose rectangle */
337 struct vpe_fmt *fmt; /* format info */
338 };
339
340 /* vpe_q_data flag bits */
341 #define Q_DATA_FRAME_1D BIT(0)
342 #define Q_DATA_MODE_TILED BIT(1)
343 #define Q_DATA_INTERLACED_ALTERNATE BIT(2)
344 #define Q_DATA_INTERLACED_SEQ_TB BIT(3)
345
346 #define Q_IS_INTERLACED (Q_DATA_INTERLACED_ALTERNATE | \
347 Q_DATA_INTERLACED_SEQ_TB)
348
349 enum {
350 Q_DATA_SRC = 0,
351 Q_DATA_DST = 1,
352 };
353
354 /* find our format description corresponding to the passed v4l2_format */
355 static struct vpe_fmt *find_format(struct v4l2_format *f)
356 {
357 struct vpe_fmt *fmt;
358 unsigned int k;
359
360 for (k = 0; k < ARRAY_SIZE(vpe_formats); k++) {
361 fmt = &vpe_formats[k];
362 if (fmt->fourcc == f->fmt.pix.pixelformat)
363 return fmt;
364 }
365
366 return NULL;
367 }
368
369 /*
370 * there is one vpe_dev structure in the driver, it is shared by
371 * all instances.
372 */
373 struct vpe_dev {
374 struct v4l2_device v4l2_dev;
375 struct video_device vfd;
376 struct v4l2_m2m_dev *m2m_dev;
377
378 atomic_t num_instances; /* count of driver instances */
379 dma_addr_t loaded_mmrs; /* shadow mmrs in device */
380 struct mutex dev_mutex;
381 spinlock_t lock;
382
383 int irq;
384 void __iomem *base;
385 struct resource *res;
386
387 struct vpdma_data vpdma_data;
388 struct vpdma_data *vpdma; /* vpdma data handle */
389 struct sc_data *sc; /* scaler data handle */
390 struct csc_data *csc; /* csc data handle */
391 };
392
393 /*
394 * There is one vpe_ctx structure for each m2m context.
395 */
396 struct vpe_ctx {
397 struct v4l2_fh fh;
398 struct vpe_dev *dev;
399 struct v4l2_ctrl_handler hdl;
400
401 unsigned int field; /* current field */
402 unsigned int sequence; /* current frame/field seq */
403 unsigned int aborting; /* abort after next irq */
404
405 unsigned int bufs_per_job; /* input buffers per batch */
406 unsigned int bufs_completed; /* bufs done in this batch */
407
408 struct vpe_q_data q_data[2]; /* src & dst queue data */
409 struct vb2_v4l2_buffer *src_vbs[VPE_MAX_SRC_BUFS];
410 struct vb2_v4l2_buffer *dst_vb;
411
412 dma_addr_t mv_buf_dma[2]; /* dma addrs of motion vector in/out bufs */
413 void *mv_buf[2]; /* virtual addrs of motion vector bufs */
414 size_t mv_buf_size; /* current motion vector buffer size */
415 struct vpdma_buf mmr_adb; /* shadow reg addr/data block */
416 struct vpdma_buf sc_coeff_h; /* h coeff buffer */
417 struct vpdma_buf sc_coeff_v; /* v coeff buffer */
418 struct vpdma_desc_list desc_list; /* DMA descriptor list */
419
420 bool deinterlacing; /* using de-interlacer */
421 bool load_mmrs; /* have new shadow reg values */
422
423 unsigned int src_mv_buf_selector;
424 };
425
426
427 /*
428 * M2M devices get 2 queues.
429 * Return the queue given the type.
430 */
431 static struct vpe_q_data *get_q_data(struct vpe_ctx *ctx,
432 enum v4l2_buf_type type)
433 {
434 switch (type) {
435 case V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE:
436 case V4L2_BUF_TYPE_VIDEO_OUTPUT:
437 return &ctx->q_data[Q_DATA_SRC];
438 case V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE:
439 case V4L2_BUF_TYPE_VIDEO_CAPTURE:
440 return &ctx->q_data[Q_DATA_DST];
441 default:
442 return NULL;
443 }
444 return NULL;
445 }
446
447 static u32 read_reg(struct vpe_dev *dev, int offset)
448 {
449 return ioread32(dev->base + offset);
450 }
451
452 static void write_reg(struct vpe_dev *dev, int offset, u32 value)
453 {
454 iowrite32(value, dev->base + offset);
455 }
456
457 /* register field read/write helpers */
458 static int get_field(u32 value, u32 mask, int shift)
459 {
460 return (value & (mask << shift)) >> shift;
461 }
462
463 static int read_field_reg(struct vpe_dev *dev, int offset, u32 mask, int shift)
464 {
465 return get_field(read_reg(dev, offset), mask, shift);
466 }
467
468 static void write_field(u32 *valp, u32 field, u32 mask, int shift)
469 {
470 u32 val = *valp;
471
472 val &= ~(mask << shift);
473 val |= (field & mask) << shift;
474 *valp = val;
475 }
476
477 static void write_field_reg(struct vpe_dev *dev, int offset, u32 field,
478 u32 mask, int shift)
479 {
480 u32 val = read_reg(dev, offset);
481
482 write_field(&val, field, mask, shift);
483
484 write_reg(dev, offset, val);
485 }
486
487 /*
488 * DMA address/data block for the shadow registers
489 */
490 struct vpe_mmr_adb {
491 struct vpdma_adb_hdr out_fmt_hdr;
492 u32 out_fmt_reg[1];
493 u32 out_fmt_pad[3];
494 struct vpdma_adb_hdr us1_hdr;
495 u32 us1_regs[8];
496 struct vpdma_adb_hdr us2_hdr;
497 u32 us2_regs[8];
498 struct vpdma_adb_hdr us3_hdr;
499 u32 us3_regs[8];
500 struct vpdma_adb_hdr dei_hdr;
501 u32 dei_regs[8];
502 struct vpdma_adb_hdr sc_hdr0;
503 u32 sc_regs0[7];
504 u32 sc_pad0[1];
505 struct vpdma_adb_hdr sc_hdr8;
506 u32 sc_regs8[6];
507 u32 sc_pad8[2];
508 struct vpdma_adb_hdr sc_hdr17;
509 u32 sc_regs17[9];
510 u32 sc_pad17[3];
511 struct vpdma_adb_hdr csc_hdr;
512 u32 csc_regs[6];
513 u32 csc_pad[2];
514 };
515
516 #define GET_OFFSET_TOP(ctx, obj, reg) \
517 ((obj)->res->start - ctx->dev->res->start + reg)
518
519 #define VPE_SET_MMR_ADB_HDR(ctx, hdr, regs, offset_a) \
520 VPDMA_SET_MMR_ADB_HDR(ctx->mmr_adb, vpe_mmr_adb, hdr, regs, offset_a)
521 /*
522 * Set the headers for all of the address/data block structures.
523 */
524 static void init_adb_hdrs(struct vpe_ctx *ctx)
525 {
526 VPE_SET_MMR_ADB_HDR(ctx, out_fmt_hdr, out_fmt_reg, VPE_CLK_FORMAT_SELECT);
527 VPE_SET_MMR_ADB_HDR(ctx, us1_hdr, us1_regs, VPE_US1_R0);
528 VPE_SET_MMR_ADB_HDR(ctx, us2_hdr, us2_regs, VPE_US2_R0);
529 VPE_SET_MMR_ADB_HDR(ctx, us3_hdr, us3_regs, VPE_US3_R0);
530 VPE_SET_MMR_ADB_HDR(ctx, dei_hdr, dei_regs, VPE_DEI_FRAME_SIZE);
531 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr0, sc_regs0,
532 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC0));
533 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr8, sc_regs8,
534 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC8));
535 VPE_SET_MMR_ADB_HDR(ctx, sc_hdr17, sc_regs17,
536 GET_OFFSET_TOP(ctx, ctx->dev->sc, CFG_SC17));
537 VPE_SET_MMR_ADB_HDR(ctx, csc_hdr, csc_regs,
538 GET_OFFSET_TOP(ctx, ctx->dev->csc, CSC_CSC00));
539 };
540
541 /*
542 * Allocate or re-allocate the motion vector DMA buffers
543 * There are two buffers, one for input and one for output.
544 * However, the roles are reversed after each field is processed.
545 * In other words, after each field is processed, the previous
546 * output (dst) MV buffer becomes the new input (src) MV buffer.
547 */
548 static int realloc_mv_buffers(struct vpe_ctx *ctx, size_t size)
549 {
550 struct device *dev = ctx->dev->v4l2_dev.dev;
551
552 if (ctx->mv_buf_size == size)
553 return 0;
554
555 if (ctx->mv_buf[0])
556 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[0],
557 ctx->mv_buf_dma[0]);
558
559 if (ctx->mv_buf[1])
560 dma_free_coherent(dev, ctx->mv_buf_size, ctx->mv_buf[1],
561 ctx->mv_buf_dma[1]);
562
563 if (size == 0)
564 return 0;
565
566 ctx->mv_buf[0] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[0],
567 GFP_KERNEL);
568 if (!ctx->mv_buf[0]) {
569 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
570 return -ENOMEM;
571 }
572
573 ctx->mv_buf[1] = dma_alloc_coherent(dev, size, &ctx->mv_buf_dma[1],
574 GFP_KERNEL);
575 if (!ctx->mv_buf[1]) {
576 vpe_err(ctx->dev, "failed to allocate motion vector buffer\n");
577 dma_free_coherent(dev, size, ctx->mv_buf[0],
578 ctx->mv_buf_dma[0]);
579
580 return -ENOMEM;
581 }
582
583 ctx->mv_buf_size = size;
584 ctx->src_mv_buf_selector = 0;
585
586 return 0;
587 }
588
589 static void free_mv_buffers(struct vpe_ctx *ctx)
590 {
591 realloc_mv_buffers(ctx, 0);
592 }
593
594 /*
595 * While de-interlacing, we keep the two most recent input buffers
596 * around. This function frees those two buffers when we have
597 * finished processing the current stream.
598 */
599 static void free_vbs(struct vpe_ctx *ctx)
600 {
601 struct vpe_dev *dev = ctx->dev;
602 unsigned long flags;
603
604 if (ctx->src_vbs[2] == NULL)
605 return;
606
607 spin_lock_irqsave(&dev->lock, flags);
608 if (ctx->src_vbs[2]) {
609 v4l2_m2m_buf_done(ctx->src_vbs[2], VB2_BUF_STATE_DONE);
610 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
611 v4l2_m2m_buf_done(ctx->src_vbs[1], VB2_BUF_STATE_DONE);
612 ctx->src_vbs[2] = NULL;
613 ctx->src_vbs[1] = NULL;
614 }
615 spin_unlock_irqrestore(&dev->lock, flags);
616 }
617
618 /*
619 * Enable or disable the VPE clocks
620 */
621 static void vpe_set_clock_enable(struct vpe_dev *dev, bool on)
622 {
623 u32 val = 0;
624
625 if (on)
626 val = VPE_DATA_PATH_CLK_ENABLE | VPE_VPEDMA_CLK_ENABLE;
627 write_reg(dev, VPE_CLK_ENABLE, val);
628 }
629
630 static void vpe_top_reset(struct vpe_dev *dev)
631 {
632
633 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_DATA_PATH_CLK_RESET_MASK,
634 VPE_DATA_PATH_CLK_RESET_SHIFT);
635
636 usleep_range(100, 150);
637
638 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_DATA_PATH_CLK_RESET_MASK,
639 VPE_DATA_PATH_CLK_RESET_SHIFT);
640 }
641
642 static void vpe_top_vpdma_reset(struct vpe_dev *dev)
643 {
644 write_field_reg(dev, VPE_CLK_RESET, 1, VPE_VPDMA_CLK_RESET_MASK,
645 VPE_VPDMA_CLK_RESET_SHIFT);
646
647 usleep_range(100, 150);
648
649 write_field_reg(dev, VPE_CLK_RESET, 0, VPE_VPDMA_CLK_RESET_MASK,
650 VPE_VPDMA_CLK_RESET_SHIFT);
651 }
652
653 /*
654 * Load the correct of upsampler coefficients into the shadow MMRs
655 */
656 static void set_us_coefficients(struct vpe_ctx *ctx)
657 {
658 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
659 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
660 u32 *us1_reg = &mmr_adb->us1_regs[0];
661 u32 *us2_reg = &mmr_adb->us2_regs[0];
662 u32 *us3_reg = &mmr_adb->us3_regs[0];
663 const unsigned short *cp, *end_cp;
664
665 cp = &us_coeffs[0].anchor_fid0_c0;
666
667 if (s_q_data->flags & Q_IS_INTERLACED) /* interlaced */
668 cp += sizeof(us_coeffs[0]) / sizeof(*cp);
669
670 end_cp = cp + sizeof(us_coeffs[0]) / sizeof(*cp);
671
672 while (cp < end_cp) {
673 write_field(us1_reg, *cp++, VPE_US_C0_MASK, VPE_US_C0_SHIFT);
674 write_field(us1_reg, *cp++, VPE_US_C1_MASK, VPE_US_C1_SHIFT);
675 *us2_reg++ = *us1_reg;
676 *us3_reg++ = *us1_reg++;
677 }
678 ctx->load_mmrs = true;
679 }
680
681 /*
682 * Set the upsampler config mode and the VPDMA line mode in the shadow MMRs.
683 */
684 static void set_cfg_modes(struct vpe_ctx *ctx)
685 {
686 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
687 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
688 u32 *us1_reg0 = &mmr_adb->us1_regs[0];
689 u32 *us2_reg0 = &mmr_adb->us2_regs[0];
690 u32 *us3_reg0 = &mmr_adb->us3_regs[0];
691 int cfg_mode = 1;
692
693 /*
694 * Cfg Mode 0: YUV420 source, enable upsampler, DEI is de-interlacing.
695 * Cfg Mode 1: YUV422 source, disable upsampler, DEI is de-interlacing.
696 */
697
698 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
699 cfg_mode = 0;
700
701 write_field(us1_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
702 write_field(us2_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
703 write_field(us3_reg0, cfg_mode, VPE_US_MODE_MASK, VPE_US_MODE_SHIFT);
704
705 ctx->load_mmrs = true;
706 }
707
708 static void set_line_modes(struct vpe_ctx *ctx)
709 {
710 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_SRC].fmt;
711 int line_mode = 1;
712
713 if (fmt->fourcc == V4L2_PIX_FMT_NV12)
714 line_mode = 0; /* double lines to line buffer */
715
716 /* regs for now */
717 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA1_IN);
718 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA2_IN);
719 vpdma_set_line_mode(ctx->dev->vpdma, line_mode, VPE_CHAN_CHROMA3_IN);
720
721 /* frame start for input luma */
722 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
723 VPE_CHAN_LUMA1_IN);
724 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
725 VPE_CHAN_LUMA2_IN);
726 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
727 VPE_CHAN_LUMA3_IN);
728
729 /* frame start for input chroma */
730 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
731 VPE_CHAN_CHROMA1_IN);
732 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
733 VPE_CHAN_CHROMA2_IN);
734 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
735 VPE_CHAN_CHROMA3_IN);
736
737 /* frame start for MV in client */
738 vpdma_set_frame_start_event(ctx->dev->vpdma, VPDMA_FSEVENT_CHANNEL_ACTIVE,
739 VPE_CHAN_MV_IN);
740 }
741
742 /*
743 * Set the shadow registers that are modified when the source
744 * format changes.
745 */
746 static void set_src_registers(struct vpe_ctx *ctx)
747 {
748 set_us_coefficients(ctx);
749 }
750
751 /*
752 * Set the shadow registers that are modified when the destination
753 * format changes.
754 */
755 static void set_dst_registers(struct vpe_ctx *ctx)
756 {
757 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
758 enum v4l2_colorspace clrspc = ctx->q_data[Q_DATA_DST].colorspace;
759 struct vpe_fmt *fmt = ctx->q_data[Q_DATA_DST].fmt;
760 u32 val = 0;
761
762 if (clrspc == V4L2_COLORSPACE_SRGB) {
763 val |= VPE_RGB_OUT_SELECT;
764 vpdma_set_bg_color(ctx->dev->vpdma,
765 (struct vpdma_data_format *)fmt->vpdma_fmt[0], 0xff);
766 } else if (fmt->fourcc == V4L2_PIX_FMT_NV16)
767 val |= VPE_COLOR_SEPARATE_422;
768
769 /*
770 * the source of CHR_DS and CSC is always the scaler, irrespective of
771 * whether it's used or not
772 */
773 val |= VPE_DS_SRC_DEI_SCALER | VPE_CSC_SRC_DEI_SCALER;
774
775 if (fmt->fourcc != V4L2_PIX_FMT_NV12)
776 val |= VPE_DS_BYPASS;
777
778 mmr_adb->out_fmt_reg[0] = val;
779
780 ctx->load_mmrs = true;
781 }
782
783 /*
784 * Set the de-interlacer shadow register values
785 */
786 static void set_dei_regs(struct vpe_ctx *ctx)
787 {
788 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
789 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
790 unsigned int src_h = s_q_data->c_rect.height;
791 unsigned int src_w = s_q_data->c_rect.width;
792 u32 *dei_mmr0 = &mmr_adb->dei_regs[0];
793 bool deinterlace = true;
794 u32 val = 0;
795
796 /*
797 * according to TRM, we should set DEI in progressive bypass mode when
798 * the input content is progressive, however, DEI is bypassed correctly
799 * for both progressive and interlace content in interlace bypass mode.
800 * It has been recommended not to use progressive bypass mode.
801 */
802 if (!(s_q_data->flags & Q_IS_INTERLACED) || !ctx->deinterlacing) {
803 deinterlace = false;
804 val = VPE_DEI_INTERLACE_BYPASS;
805 }
806
807 src_h = deinterlace ? src_h * 2 : src_h;
808
809 val |= (src_h << VPE_DEI_HEIGHT_SHIFT) |
810 (src_w << VPE_DEI_WIDTH_SHIFT) |
811 VPE_DEI_FIELD_FLUSH;
812
813 *dei_mmr0 = val;
814
815 ctx->load_mmrs = true;
816 }
817
818 static void set_dei_shadow_registers(struct vpe_ctx *ctx)
819 {
820 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
821 u32 *dei_mmr = &mmr_adb->dei_regs[0];
822 const struct vpe_dei_regs *cur = &dei_regs;
823
824 dei_mmr[2] = cur->mdt_spacial_freq_thr_reg;
825 dei_mmr[3] = cur->edi_config_reg;
826 dei_mmr[4] = cur->edi_lut_reg0;
827 dei_mmr[5] = cur->edi_lut_reg1;
828 dei_mmr[6] = cur->edi_lut_reg2;
829 dei_mmr[7] = cur->edi_lut_reg3;
830
831 ctx->load_mmrs = true;
832 }
833
834 static void config_edi_input_mode(struct vpe_ctx *ctx, int mode)
835 {
836 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
837 u32 *edi_config_reg = &mmr_adb->dei_regs[3];
838
839 if (mode & 0x2)
840 write_field(edi_config_reg, 1, 1, 2); /* EDI_ENABLE_3D */
841
842 if (mode & 0x3)
843 write_field(edi_config_reg, 1, 1, 3); /* EDI_CHROMA_3D */
844
845 write_field(edi_config_reg, mode, VPE_EDI_INP_MODE_MASK,
846 VPE_EDI_INP_MODE_SHIFT);
847
848 ctx->load_mmrs = true;
849 }
850
851 /*
852 * Set the shadow registers whose values are modified when either the
853 * source or destination format is changed.
854 */
855 static int set_srcdst_params(struct vpe_ctx *ctx)
856 {
857 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
858 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
859 struct vpe_mmr_adb *mmr_adb = ctx->mmr_adb.addr;
860 unsigned int src_w = s_q_data->c_rect.width;
861 unsigned int src_h = s_q_data->c_rect.height;
862 unsigned int dst_w = d_q_data->c_rect.width;
863 unsigned int dst_h = d_q_data->c_rect.height;
864 size_t mv_buf_size;
865 int ret;
866
867 ctx->sequence = 0;
868 ctx->field = V4L2_FIELD_TOP;
869
870 if ((s_q_data->flags & Q_IS_INTERLACED) &&
871 !(d_q_data->flags & Q_IS_INTERLACED)) {
872 int bytes_per_line;
873 const struct vpdma_data_format *mv =
874 &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
875
876 /*
877 * we make sure that the source image has a 16 byte aligned
878 * stride, we need to do the same for the motion vector buffer
879 * by aligning it's stride to the next 16 byte boundry. this
880 * extra space will not be used by the de-interlacer, but will
881 * ensure that vpdma operates correctly
882 */
883 bytes_per_line = ALIGN((s_q_data->width * mv->depth) >> 3,
884 VPDMA_STRIDE_ALIGN);
885 mv_buf_size = bytes_per_line * s_q_data->height;
886
887 ctx->deinterlacing = true;
888 src_h <<= 1;
889 } else {
890 ctx->deinterlacing = false;
891 mv_buf_size = 0;
892 }
893
894 free_vbs(ctx);
895 ctx->src_vbs[2] = ctx->src_vbs[1] = ctx->src_vbs[0] = NULL;
896
897 ret = realloc_mv_buffers(ctx, mv_buf_size);
898 if (ret)
899 return ret;
900
901 set_cfg_modes(ctx);
902 set_dei_regs(ctx);
903
904 csc_set_coeff(ctx->dev->csc, &mmr_adb->csc_regs[0],
905 s_q_data->colorspace, d_q_data->colorspace);
906
907 sc_set_hs_coeffs(ctx->dev->sc, ctx->sc_coeff_h.addr, src_w, dst_w);
908 sc_set_vs_coeffs(ctx->dev->sc, ctx->sc_coeff_v.addr, src_h, dst_h);
909
910 sc_config_scaler(ctx->dev->sc, &mmr_adb->sc_regs0[0],
911 &mmr_adb->sc_regs8[0], &mmr_adb->sc_regs17[0],
912 src_w, src_h, dst_w, dst_h);
913
914 return 0;
915 }
916
917 /*
918 * Return the vpe_ctx structure for a given struct file
919 */
920 static struct vpe_ctx *file2ctx(struct file *file)
921 {
922 return container_of(file->private_data, struct vpe_ctx, fh);
923 }
924
925 /*
926 * mem2mem callbacks
927 */
928
929 /*
930 * job_ready() - check whether an instance is ready to be scheduled to run
931 */
932 static int job_ready(void *priv)
933 {
934 struct vpe_ctx *ctx = priv;
935
936 /*
937 * This check is needed as this might be called directly from driver
938 * When called by m2m framework, this will always satisfy, but when
939 * called from vpe_irq, this might fail. (src stream with zero buffers)
940 */
941 if (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) <= 0 ||
942 v4l2_m2m_num_dst_bufs_ready(ctx->fh.m2m_ctx) <= 0)
943 return 0;
944
945 return 1;
946 }
947
948 static void job_abort(void *priv)
949 {
950 struct vpe_ctx *ctx = priv;
951
952 /* Will cancel the transaction in the next interrupt handler */
953 ctx->aborting = 1;
954 }
955
956 static void vpe_dump_regs(struct vpe_dev *dev)
957 {
958 #define DUMPREG(r) vpe_dbg(dev, "%-35s %08x\n", #r, read_reg(dev, VPE_##r))
959
960 vpe_dbg(dev, "VPE Registers:\n");
961
962 DUMPREG(PID);
963 DUMPREG(SYSCONFIG);
964 DUMPREG(INT0_STATUS0_RAW);
965 DUMPREG(INT0_STATUS0);
966 DUMPREG(INT0_ENABLE0);
967 DUMPREG(INT0_STATUS1_RAW);
968 DUMPREG(INT0_STATUS1);
969 DUMPREG(INT0_ENABLE1);
970 DUMPREG(CLK_ENABLE);
971 DUMPREG(CLK_RESET);
972 DUMPREG(CLK_FORMAT_SELECT);
973 DUMPREG(CLK_RANGE_MAP);
974 DUMPREG(US1_R0);
975 DUMPREG(US1_R1);
976 DUMPREG(US1_R2);
977 DUMPREG(US1_R3);
978 DUMPREG(US1_R4);
979 DUMPREG(US1_R5);
980 DUMPREG(US1_R6);
981 DUMPREG(US1_R7);
982 DUMPREG(US2_R0);
983 DUMPREG(US2_R1);
984 DUMPREG(US2_R2);
985 DUMPREG(US2_R3);
986 DUMPREG(US2_R4);
987 DUMPREG(US2_R5);
988 DUMPREG(US2_R6);
989 DUMPREG(US2_R7);
990 DUMPREG(US3_R0);
991 DUMPREG(US3_R1);
992 DUMPREG(US3_R2);
993 DUMPREG(US3_R3);
994 DUMPREG(US3_R4);
995 DUMPREG(US3_R5);
996 DUMPREG(US3_R6);
997 DUMPREG(US3_R7);
998 DUMPREG(DEI_FRAME_SIZE);
999 DUMPREG(MDT_BYPASS);
1000 DUMPREG(MDT_SF_THRESHOLD);
1001 DUMPREG(EDI_CONFIG);
1002 DUMPREG(DEI_EDI_LUT_R0);
1003 DUMPREG(DEI_EDI_LUT_R1);
1004 DUMPREG(DEI_EDI_LUT_R2);
1005 DUMPREG(DEI_EDI_LUT_R3);
1006 DUMPREG(DEI_FMD_WINDOW_R0);
1007 DUMPREG(DEI_FMD_WINDOW_R1);
1008 DUMPREG(DEI_FMD_CONTROL_R0);
1009 DUMPREG(DEI_FMD_CONTROL_R1);
1010 DUMPREG(DEI_FMD_STATUS_R0);
1011 DUMPREG(DEI_FMD_STATUS_R1);
1012 DUMPREG(DEI_FMD_STATUS_R2);
1013 #undef DUMPREG
1014
1015 sc_dump_regs(dev->sc);
1016 csc_dump_regs(dev->csc);
1017 }
1018
1019 static void add_out_dtd(struct vpe_ctx *ctx, int port)
1020 {
1021 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_DST];
1022 const struct vpe_port_data *p_data = &port_data[port];
1023 struct vb2_buffer *vb = &ctx->dst_vb->vb2_buf;
1024 struct vpe_fmt *fmt = q_data->fmt;
1025 const struct vpdma_data_format *vpdma_fmt;
1026 int mv_buf_selector = !ctx->src_mv_buf_selector;
1027 dma_addr_t dma_addr;
1028 u32 flags = 0;
1029 u32 offset = 0;
1030
1031 if (port == VPE_PORT_MV_OUT) {
1032 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1033 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1034 q_data = &ctx->q_data[Q_DATA_SRC];
1035 } else {
1036 /* to incorporate interleaved formats */
1037 int plane = fmt->coplanar ? p_data->vb_part : 0;
1038
1039 vpdma_fmt = fmt->vpdma_fmt[plane];
1040 /*
1041 * If we are using a single plane buffer and
1042 * we need to set a separate vpdma chroma channel.
1043 */
1044 if (q_data->nplanes == 1 && plane) {
1045 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1046 /* Compute required offset */
1047 offset = q_data->bytesperline[0] * q_data->height;
1048 } else {
1049 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1050 /* Use address as is, no offset */
1051 offset = 0;
1052 }
1053 if (!dma_addr) {
1054 vpe_err(ctx->dev,
1055 "acquiring output buffer(%d) dma_addr failed\n",
1056 port);
1057 return;
1058 }
1059 /* Apply the offset */
1060 dma_addr += offset;
1061 }
1062
1063 if (q_data->flags & Q_DATA_FRAME_1D)
1064 flags |= VPDMA_DATA_FRAME_1D;
1065 if (q_data->flags & Q_DATA_MODE_TILED)
1066 flags |= VPDMA_DATA_MODE_TILED;
1067
1068 vpdma_set_max_size(ctx->dev->vpdma, VPDMA_MAX_SIZE1,
1069 MAX_W, MAX_H);
1070
1071 vpdma_add_out_dtd(&ctx->desc_list, q_data->width,
1072 q_data->bytesperline[VPE_LUMA], &q_data->c_rect,
1073 vpdma_fmt, dma_addr, MAX_OUT_WIDTH_REG1,
1074 MAX_OUT_HEIGHT_REG1, p_data->channel, flags);
1075 }
1076
1077 static void add_in_dtd(struct vpe_ctx *ctx, int port)
1078 {
1079 struct vpe_q_data *q_data = &ctx->q_data[Q_DATA_SRC];
1080 const struct vpe_port_data *p_data = &port_data[port];
1081 struct vb2_buffer *vb = &ctx->src_vbs[p_data->vb_index]->vb2_buf;
1082 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1083 struct vpe_fmt *fmt = q_data->fmt;
1084 const struct vpdma_data_format *vpdma_fmt;
1085 int mv_buf_selector = ctx->src_mv_buf_selector;
1086 int field = vbuf->field == V4L2_FIELD_BOTTOM;
1087 int frame_width, frame_height;
1088 dma_addr_t dma_addr;
1089 u32 flags = 0;
1090 u32 offset = 0;
1091
1092 if (port == VPE_PORT_MV_IN) {
1093 vpdma_fmt = &vpdma_misc_fmts[VPDMA_DATA_FMT_MV];
1094 dma_addr = ctx->mv_buf_dma[mv_buf_selector];
1095 } else {
1096 /* to incorporate interleaved formats */
1097 int plane = fmt->coplanar ? p_data->vb_part : 0;
1098
1099 vpdma_fmt = fmt->vpdma_fmt[plane];
1100 /*
1101 * If we are using a single plane buffer and
1102 * we need to set a separate vpdma chroma channel.
1103 */
1104 if (q_data->nplanes == 1 && plane) {
1105 dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
1106 /* Compute required offset */
1107 offset = q_data->bytesperline[0] * q_data->height;
1108 } else {
1109 dma_addr = vb2_dma_contig_plane_dma_addr(vb, plane);
1110 /* Use address as is, no offset */
1111 offset = 0;
1112 }
1113 if (!dma_addr) {
1114 vpe_err(ctx->dev,
1115 "acquiring output buffer(%d) dma_addr failed\n",
1116 port);
1117 return;
1118 }
1119 /* Apply the offset */
1120 dma_addr += offset;
1121
1122 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB) {
1123 /*
1124 * Use top or bottom field from same vb alternately
1125 * f,f-1,f-2 = TBT when seq is even
1126 * f,f-1,f-2 = BTB when seq is odd
1127 */
1128 field = (p_data->vb_index + (ctx->sequence % 2)) % 2;
1129
1130 if (field) {
1131 /*
1132 * bottom field of a SEQ_TB buffer
1133 * Skip the top field data by
1134 */
1135 int height = q_data->height / 2;
1136 int bpp = fmt->fourcc == V4L2_PIX_FMT_NV12 ?
1137 1 : (vpdma_fmt->depth >> 3);
1138 if (plane)
1139 height /= 2;
1140 dma_addr += q_data->width * height * bpp;
1141 }
1142 }
1143 }
1144
1145 if (q_data->flags & Q_DATA_FRAME_1D)
1146 flags |= VPDMA_DATA_FRAME_1D;
1147 if (q_data->flags & Q_DATA_MODE_TILED)
1148 flags |= VPDMA_DATA_MODE_TILED;
1149
1150 frame_width = q_data->c_rect.width;
1151 frame_height = q_data->c_rect.height;
1152
1153 if (p_data->vb_part && fmt->fourcc == V4L2_PIX_FMT_NV12)
1154 frame_height /= 2;
1155
1156 vpdma_add_in_dtd(&ctx->desc_list, q_data->width,
1157 q_data->bytesperline[VPE_LUMA], &q_data->c_rect,
1158 vpdma_fmt, dma_addr, p_data->channel, field, flags, frame_width,
1159 frame_height, 0, 0);
1160 }
1161
1162 /*
1163 * Enable the expected IRQ sources
1164 */
1165 static void enable_irqs(struct vpe_ctx *ctx)
1166 {
1167 write_reg(ctx->dev, VPE_INT0_ENABLE0_SET, VPE_INT0_LIST0_COMPLETE);
1168 write_reg(ctx->dev, VPE_INT0_ENABLE1_SET, VPE_DEI_ERROR_INT |
1169 VPE_DS1_UV_ERROR_INT);
1170
1171 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, true);
1172 }
1173
1174 static void disable_irqs(struct vpe_ctx *ctx)
1175 {
1176 write_reg(ctx->dev, VPE_INT0_ENABLE0_CLR, 0xffffffff);
1177 write_reg(ctx->dev, VPE_INT0_ENABLE1_CLR, 0xffffffff);
1178
1179 vpdma_enable_list_complete_irq(ctx->dev->vpdma, 0, 0, false);
1180 }
1181
1182 /* device_run() - prepares and starts the device
1183 *
1184 * This function is only called when both the source and destination
1185 * buffers are in place.
1186 */
1187 static void device_run(void *priv)
1188 {
1189 struct vpe_ctx *ctx = priv;
1190 struct sc_data *sc = ctx->dev->sc;
1191 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
1192 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
1193
1194 if (ctx->deinterlacing && s_q_data->flags & Q_DATA_INTERLACED_SEQ_TB &&
1195 ctx->sequence % 2 == 0) {
1196 /* When using SEQ_TB buffers, When using it first time,
1197 * No need to remove the buffer as the next field is present
1198 * in the same buffer. (so that job_ready won't fail)
1199 * It will be removed when using bottom field
1200 */
1201 ctx->src_vbs[0] = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
1202 WARN_ON(ctx->src_vbs[0] == NULL);
1203 } else {
1204 ctx->src_vbs[0] = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
1205 WARN_ON(ctx->src_vbs[0] == NULL);
1206 }
1207
1208 ctx->dst_vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
1209 WARN_ON(ctx->dst_vb == NULL);
1210
1211 if (ctx->deinterlacing) {
1212
1213 if (ctx->src_vbs[2] == NULL) {
1214 ctx->src_vbs[2] = ctx->src_vbs[0];
1215 WARN_ON(ctx->src_vbs[2] == NULL);
1216 ctx->src_vbs[1] = ctx->src_vbs[0];
1217 WARN_ON(ctx->src_vbs[1] == NULL);
1218 }
1219
1220 /*
1221 * we have output the first 2 frames through line average, we
1222 * now switch to EDI de-interlacer
1223 */
1224 if (ctx->sequence == 2)
1225 config_edi_input_mode(ctx, 0x3); /* EDI (Y + UV) */
1226 }
1227
1228 /* config descriptors */
1229 if (ctx->dev->loaded_mmrs != ctx->mmr_adb.dma_addr || ctx->load_mmrs) {
1230 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->mmr_adb);
1231 vpdma_add_cfd_adb(&ctx->desc_list, CFD_MMR_CLIENT, &ctx->mmr_adb);
1232
1233 set_line_modes(ctx);
1234
1235 ctx->dev->loaded_mmrs = ctx->mmr_adb.dma_addr;
1236 ctx->load_mmrs = false;
1237 }
1238
1239 if (sc->loaded_coeff_h != ctx->sc_coeff_h.dma_addr ||
1240 sc->load_coeff_h) {
1241 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_h);
1242 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1243 &ctx->sc_coeff_h, 0);
1244
1245 sc->loaded_coeff_h = ctx->sc_coeff_h.dma_addr;
1246 sc->load_coeff_h = false;
1247 }
1248
1249 if (sc->loaded_coeff_v != ctx->sc_coeff_v.dma_addr ||
1250 sc->load_coeff_v) {
1251 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->sc_coeff_v);
1252 vpdma_add_cfd_block(&ctx->desc_list, CFD_SC_CLIENT,
1253 &ctx->sc_coeff_v, SC_COEF_SRAM_SIZE >> 4);
1254
1255 sc->loaded_coeff_v = ctx->sc_coeff_v.dma_addr;
1256 sc->load_coeff_v = false;
1257 }
1258
1259 /* output data descriptors */
1260 if (ctx->deinterlacing)
1261 add_out_dtd(ctx, VPE_PORT_MV_OUT);
1262
1263 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1264 add_out_dtd(ctx, VPE_PORT_RGB_OUT);
1265 } else {
1266 add_out_dtd(ctx, VPE_PORT_LUMA_OUT);
1267 if (d_q_data->fmt->coplanar)
1268 add_out_dtd(ctx, VPE_PORT_CHROMA_OUT);
1269 }
1270
1271 /* input data descriptors */
1272 if (ctx->deinterlacing) {
1273 add_in_dtd(ctx, VPE_PORT_LUMA3_IN);
1274 add_in_dtd(ctx, VPE_PORT_CHROMA3_IN);
1275
1276 add_in_dtd(ctx, VPE_PORT_LUMA2_IN);
1277 add_in_dtd(ctx, VPE_PORT_CHROMA2_IN);
1278 }
1279
1280 add_in_dtd(ctx, VPE_PORT_LUMA1_IN);
1281 add_in_dtd(ctx, VPE_PORT_CHROMA1_IN);
1282
1283 if (ctx->deinterlacing)
1284 add_in_dtd(ctx, VPE_PORT_MV_IN);
1285
1286 /* sync on channel control descriptors for input ports */
1287 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_LUMA1_IN);
1288 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_CHROMA1_IN);
1289
1290 if (ctx->deinterlacing) {
1291 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1292 VPE_CHAN_LUMA2_IN);
1293 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1294 VPE_CHAN_CHROMA2_IN);
1295
1296 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1297 VPE_CHAN_LUMA3_IN);
1298 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1299 VPE_CHAN_CHROMA3_IN);
1300
1301 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_IN);
1302 }
1303
1304 /* sync on channel control descriptors for output ports */
1305 if (d_q_data->colorspace == V4L2_COLORSPACE_SRGB) {
1306 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1307 VPE_CHAN_RGB_OUT);
1308 } else {
1309 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1310 VPE_CHAN_LUMA_OUT);
1311 if (d_q_data->fmt->coplanar)
1312 vpdma_add_sync_on_channel_ctd(&ctx->desc_list,
1313 VPE_CHAN_CHROMA_OUT);
1314 }
1315
1316 if (ctx->deinterlacing)
1317 vpdma_add_sync_on_channel_ctd(&ctx->desc_list, VPE_CHAN_MV_OUT);
1318
1319 enable_irqs(ctx);
1320
1321 vpdma_map_desc_buf(ctx->dev->vpdma, &ctx->desc_list.buf);
1322 vpdma_submit_descs(ctx->dev->vpdma, &ctx->desc_list, 0);
1323 }
1324
1325 static void dei_error(struct vpe_ctx *ctx)
1326 {
1327 dev_warn(ctx->dev->v4l2_dev.dev,
1328 "received DEI error interrupt\n");
1329 }
1330
1331 static void ds1_uv_error(struct vpe_ctx *ctx)
1332 {
1333 dev_warn(ctx->dev->v4l2_dev.dev,
1334 "received downsampler error interrupt\n");
1335 }
1336
1337 static irqreturn_t vpe_irq(int irq_vpe, void *data)
1338 {
1339 struct vpe_dev *dev = (struct vpe_dev *)data;
1340 struct vpe_ctx *ctx;
1341 struct vpe_q_data *d_q_data;
1342 struct vb2_v4l2_buffer *s_vb, *d_vb;
1343 unsigned long flags;
1344 u32 irqst0, irqst1;
1345 bool list_complete = false;
1346
1347 irqst0 = read_reg(dev, VPE_INT0_STATUS0);
1348 if (irqst0) {
1349 write_reg(dev, VPE_INT0_STATUS0_CLR, irqst0);
1350 vpe_dbg(dev, "INT0_STATUS0 = 0x%08x\n", irqst0);
1351 }
1352
1353 irqst1 = read_reg(dev, VPE_INT0_STATUS1);
1354 if (irqst1) {
1355 write_reg(dev, VPE_INT0_STATUS1_CLR, irqst1);
1356 vpe_dbg(dev, "INT0_STATUS1 = 0x%08x\n", irqst1);
1357 }
1358
1359 ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
1360 if (!ctx) {
1361 vpe_err(dev, "instance released before end of transaction\n");
1362 goto handled;
1363 }
1364
1365 if (irqst1) {
1366 if (irqst1 & VPE_DEI_ERROR_INT) {
1367 irqst1 &= ~VPE_DEI_ERROR_INT;
1368 dei_error(ctx);
1369 }
1370 if (irqst1 & VPE_DS1_UV_ERROR_INT) {
1371 irqst1 &= ~VPE_DS1_UV_ERROR_INT;
1372 ds1_uv_error(ctx);
1373 }
1374 }
1375
1376 if (irqst0) {
1377 if (irqst0 & VPE_INT0_LIST0_COMPLETE)
1378 vpdma_clear_list_stat(ctx->dev->vpdma, 0, 0);
1379
1380 irqst0 &= ~(VPE_INT0_LIST0_COMPLETE);
1381 list_complete = true;
1382 }
1383
1384 if (irqst0 | irqst1) {
1385 dev_warn(dev->v4l2_dev.dev, "Unexpected interrupt: INT0_STATUS0 = 0x%08x, INT0_STATUS1 = 0x%08x\n",
1386 irqst0, irqst1);
1387 }
1388
1389 /*
1390 * Setup next operation only when list complete IRQ occurs
1391 * otherwise, skip the following code
1392 */
1393 if (!list_complete)
1394 goto handled;
1395
1396 disable_irqs(ctx);
1397
1398 vpdma_unmap_desc_buf(dev->vpdma, &ctx->desc_list.buf);
1399 vpdma_unmap_desc_buf(dev->vpdma, &ctx->mmr_adb);
1400 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_h);
1401 vpdma_unmap_desc_buf(dev->vpdma, &ctx->sc_coeff_v);
1402
1403 vpdma_reset_desc_list(&ctx->desc_list);
1404
1405 /* the previous dst mv buffer becomes the next src mv buffer */
1406 ctx->src_mv_buf_selector = !ctx->src_mv_buf_selector;
1407
1408 if (ctx->aborting)
1409 goto finished;
1410
1411 s_vb = ctx->src_vbs[0];
1412 d_vb = ctx->dst_vb;
1413
1414 d_vb->flags = s_vb->flags;
1415 d_vb->vb2_buf.timestamp = s_vb->vb2_buf.timestamp;
1416
1417 if (s_vb->flags & V4L2_BUF_FLAG_TIMECODE)
1418 d_vb->timecode = s_vb->timecode;
1419
1420 d_vb->sequence = ctx->sequence;
1421
1422 d_q_data = &ctx->q_data[Q_DATA_DST];
1423 if (d_q_data->flags & Q_IS_INTERLACED) {
1424 d_vb->field = ctx->field;
1425 if (ctx->field == V4L2_FIELD_BOTTOM) {
1426 ctx->sequence++;
1427 ctx->field = V4L2_FIELD_TOP;
1428 } else {
1429 WARN_ON(ctx->field != V4L2_FIELD_TOP);
1430 ctx->field = V4L2_FIELD_BOTTOM;
1431 }
1432 } else {
1433 d_vb->field = V4L2_FIELD_NONE;
1434 ctx->sequence++;
1435 }
1436
1437 if (ctx->deinterlacing) {
1438 /*
1439 * Allow source buffer to be dequeued only if it won't be used
1440 * in the next iteration. All vbs are initialized to first
1441 * buffer and we are shifting buffers every iteration, for the
1442 * first two iterations, no buffer will be dequeued.
1443 * This ensures that driver will keep (n-2)th (n-1)th and (n)th
1444 * field when deinterlacing is enabled
1445 */
1446 if (ctx->src_vbs[2] != ctx->src_vbs[1])
1447 s_vb = ctx->src_vbs[2];
1448 else
1449 s_vb = NULL;
1450 }
1451
1452 spin_lock_irqsave(&dev->lock, flags);
1453
1454 if (s_vb)
1455 v4l2_m2m_buf_done(s_vb, VB2_BUF_STATE_DONE);
1456
1457 v4l2_m2m_buf_done(d_vb, VB2_BUF_STATE_DONE);
1458
1459 spin_unlock_irqrestore(&dev->lock, flags);
1460
1461 if (ctx->deinterlacing) {
1462 ctx->src_vbs[2] = ctx->src_vbs[1];
1463 ctx->src_vbs[1] = ctx->src_vbs[0];
1464 }
1465
1466 /*
1467 * Since the vb2_buf_done has already been called fir therse
1468 * buffer we can now NULL them out so that we won't try
1469 * to clean out stray pointer later on.
1470 */
1471 ctx->src_vbs[0] = NULL;
1472 ctx->dst_vb = NULL;
1473
1474 ctx->bufs_completed++;
1475 if (ctx->bufs_completed < ctx->bufs_per_job && job_ready(ctx)) {
1476 device_run(ctx);
1477 goto handled;
1478 }
1479
1480 finished:
1481 vpe_dbg(ctx->dev, "finishing transaction\n");
1482 ctx->bufs_completed = 0;
1483 v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
1484 handled:
1485 return IRQ_HANDLED;
1486 }
1487
1488 /*
1489 * video ioctls
1490 */
1491 static int vpe_querycap(struct file *file, void *priv,
1492 struct v4l2_capability *cap)
1493 {
1494 strncpy(cap->driver, VPE_MODULE_NAME, sizeof(cap->driver) - 1);
1495 strncpy(cap->card, VPE_MODULE_NAME, sizeof(cap->card) - 1);
1496 snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
1497 VPE_MODULE_NAME);
1498 cap->device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING;
1499 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1500 return 0;
1501 }
1502
1503 static int __enum_fmt(struct v4l2_fmtdesc *f, u32 type)
1504 {
1505 int i, index;
1506 struct vpe_fmt *fmt = NULL;
1507
1508 index = 0;
1509 for (i = 0; i < ARRAY_SIZE(vpe_formats); ++i) {
1510 if (vpe_formats[i].types & type) {
1511 if (index == f->index) {
1512 fmt = &vpe_formats[i];
1513 break;
1514 }
1515 index++;
1516 }
1517 }
1518
1519 if (!fmt)
1520 return -EINVAL;
1521
1522 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
1523 f->pixelformat = fmt->fourcc;
1524 return 0;
1525 }
1526
1527 static int vpe_enum_fmt(struct file *file, void *priv,
1528 struct v4l2_fmtdesc *f)
1529 {
1530 if (V4L2_TYPE_IS_OUTPUT(f->type))
1531 return __enum_fmt(f, VPE_FMT_TYPE_OUTPUT);
1532
1533 return __enum_fmt(f, VPE_FMT_TYPE_CAPTURE);
1534 }
1535
1536 static int vpe_g_fmt(struct file *file, void *priv, struct v4l2_format *f)
1537 {
1538 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1539 struct vpe_ctx *ctx = file2ctx(file);
1540 struct vb2_queue *vq;
1541 struct vpe_q_data *q_data;
1542 int i;
1543
1544 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1545 if (!vq)
1546 return -EINVAL;
1547
1548 q_data = get_q_data(ctx, f->type);
1549
1550 pix->width = q_data->width;
1551 pix->height = q_data->height;
1552 pix->pixelformat = q_data->fmt->fourcc;
1553 pix->field = q_data->field;
1554
1555 if (V4L2_TYPE_IS_OUTPUT(f->type)) {
1556 pix->colorspace = q_data->colorspace;
1557 } else {
1558 struct vpe_q_data *s_q_data;
1559
1560 /* get colorspace from the source queue */
1561 s_q_data = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE);
1562
1563 pix->colorspace = s_q_data->colorspace;
1564 }
1565
1566 pix->num_planes = q_data->nplanes;
1567
1568 for (i = 0; i < pix->num_planes; i++) {
1569 pix->plane_fmt[i].bytesperline = q_data->bytesperline[i];
1570 pix->plane_fmt[i].sizeimage = q_data->sizeimage[i];
1571 }
1572
1573 return 0;
1574 }
1575
1576 static int __vpe_try_fmt(struct vpe_ctx *ctx, struct v4l2_format *f,
1577 struct vpe_fmt *fmt, int type)
1578 {
1579 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1580 struct v4l2_plane_pix_format *plane_fmt;
1581 unsigned int w_align;
1582 int i, depth, depth_bytes, height;
1583 unsigned int stride = 0;
1584
1585 if (!fmt || !(fmt->types & type)) {
1586 vpe_err(ctx->dev, "Fourcc format (0x%08x) invalid.\n",
1587 pix->pixelformat);
1588 return -EINVAL;
1589 }
1590
1591 if (pix->field != V4L2_FIELD_NONE && pix->field != V4L2_FIELD_ALTERNATE
1592 && pix->field != V4L2_FIELD_SEQ_TB)
1593 pix->field = V4L2_FIELD_NONE;
1594
1595 depth = fmt->vpdma_fmt[VPE_LUMA]->depth;
1596
1597 /*
1598 * the line stride should 16 byte aligned for VPDMA to work, based on
1599 * the bytes per pixel, figure out how much the width should be aligned
1600 * to make sure line stride is 16 byte aligned
1601 */
1602 depth_bytes = depth >> 3;
1603
1604 if (depth_bytes == 3) {
1605 /*
1606 * if bpp is 3(as in some RGB formats), the pixel width doesn't
1607 * really help in ensuring line stride is 16 byte aligned
1608 */
1609 w_align = 4;
1610 } else {
1611 /*
1612 * for the remainder bpp(4, 2 and 1), the pixel width alignment
1613 * can ensure a line stride alignment of 16 bytes. For example,
1614 * if bpp is 2, then the line stride can be 16 byte aligned if
1615 * the width is 8 byte aligned
1616 */
1617
1618 /*
1619 * HACK: using order_base_2() here causes lots of asm output
1620 * errors with smatch, on i386:
1621 * ./arch/x86/include/asm/bitops.h:457:22:
1622 * warning: asm output is not an lvalue
1623 * Perhaps some gcc optimization is doing the wrong thing
1624 * there.
1625 * Let's get rid of them by doing the calculus on two steps
1626 */
1627 w_align = roundup_pow_of_two(VPDMA_DESC_ALIGN / depth_bytes);
1628 w_align = ilog2(w_align);
1629 }
1630
1631 v4l_bound_align_image(&pix->width, MIN_W, MAX_W, w_align,
1632 &pix->height, MIN_H, MAX_H, H_ALIGN,
1633 S_ALIGN);
1634
1635 if (!pix->num_planes)
1636 pix->num_planes = fmt->coplanar ? 2 : 1;
1637 else if (pix->num_planes > 1 && !fmt->coplanar)
1638 pix->num_planes = 1;
1639
1640 pix->pixelformat = fmt->fourcc;
1641
1642 /*
1643 * For the actual image parameters, we need to consider the field
1644 * height of the image for SEQ_TB buffers.
1645 */
1646 if (pix->field == V4L2_FIELD_SEQ_TB)
1647 height = pix->height / 2;
1648 else
1649 height = pix->height;
1650
1651 if (!pix->colorspace) {
1652 if (fmt->fourcc == V4L2_PIX_FMT_RGB24 ||
1653 fmt->fourcc == V4L2_PIX_FMT_BGR24 ||
1654 fmt->fourcc == V4L2_PIX_FMT_RGB32 ||
1655 fmt->fourcc == V4L2_PIX_FMT_BGR32) {
1656 pix->colorspace = V4L2_COLORSPACE_SRGB;
1657 } else {
1658 if (height > 1280) /* HD */
1659 pix->colorspace = V4L2_COLORSPACE_REC709;
1660 else /* SD */
1661 pix->colorspace = V4L2_COLORSPACE_SMPTE170M;
1662 }
1663 }
1664
1665 memset(pix->reserved, 0, sizeof(pix->reserved));
1666 for (i = 0; i < pix->num_planes; i++) {
1667 plane_fmt = &pix->plane_fmt[i];
1668 depth = fmt->vpdma_fmt[i]->depth;
1669
1670 stride = (pix->width * fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
1671 if (stride > plane_fmt->bytesperline)
1672 plane_fmt->bytesperline = stride;
1673
1674 plane_fmt->bytesperline = ALIGN(plane_fmt->bytesperline,
1675 VPDMA_STRIDE_ALIGN);
1676
1677 if (i == VPE_LUMA) {
1678 plane_fmt->sizeimage = pix->height *
1679 plane_fmt->bytesperline;
1680
1681 if (pix->num_planes == 1 && fmt->coplanar)
1682 plane_fmt->sizeimage += pix->height *
1683 plane_fmt->bytesperline *
1684 fmt->vpdma_fmt[VPE_CHROMA]->depth >> 3;
1685
1686 } else { /* i == VIP_CHROMA */
1687 plane_fmt->sizeimage = (pix->height *
1688 plane_fmt->bytesperline *
1689 depth) >> 3;
1690 }
1691 memset(plane_fmt->reserved, 0, sizeof(plane_fmt->reserved));
1692 }
1693
1694 return 0;
1695 }
1696
1697 static int vpe_try_fmt(struct file *file, void *priv, struct v4l2_format *f)
1698 {
1699 struct vpe_ctx *ctx = file2ctx(file);
1700 struct vpe_fmt *fmt = find_format(f);
1701
1702 if (V4L2_TYPE_IS_OUTPUT(f->type))
1703 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_OUTPUT);
1704 else
1705 return __vpe_try_fmt(ctx, f, fmt, VPE_FMT_TYPE_CAPTURE);
1706 }
1707
1708 static int __vpe_s_fmt(struct vpe_ctx *ctx, struct v4l2_format *f)
1709 {
1710 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1711 struct v4l2_plane_pix_format *plane_fmt;
1712 struct vpe_q_data *q_data;
1713 struct vb2_queue *vq;
1714 int i;
1715
1716 vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
1717 if (!vq)
1718 return -EINVAL;
1719
1720 if (vb2_is_busy(vq)) {
1721 vpe_err(ctx->dev, "queue busy\n");
1722 return -EBUSY;
1723 }
1724
1725 q_data = get_q_data(ctx, f->type);
1726 if (!q_data)
1727 return -EINVAL;
1728
1729 q_data->fmt = find_format(f);
1730 q_data->width = pix->width;
1731 q_data->height = pix->height;
1732 q_data->colorspace = pix->colorspace;
1733 q_data->field = pix->field;
1734 q_data->nplanes = pix->num_planes;
1735
1736 for (i = 0; i < pix->num_planes; i++) {
1737 plane_fmt = &pix->plane_fmt[i];
1738
1739 q_data->bytesperline[i] = plane_fmt->bytesperline;
1740 q_data->sizeimage[i] = plane_fmt->sizeimage;
1741 }
1742
1743 q_data->c_rect.left = 0;
1744 q_data->c_rect.top = 0;
1745 q_data->c_rect.width = q_data->width;
1746 q_data->c_rect.height = q_data->height;
1747
1748 if (q_data->field == V4L2_FIELD_ALTERNATE)
1749 q_data->flags |= Q_DATA_INTERLACED_ALTERNATE;
1750 else if (q_data->field == V4L2_FIELD_SEQ_TB)
1751 q_data->flags |= Q_DATA_INTERLACED_SEQ_TB;
1752 else
1753 q_data->flags &= ~Q_IS_INTERLACED;
1754
1755 /* the crop height is halved for the case of SEQ_TB buffers */
1756 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1757 q_data->c_rect.height /= 2;
1758
1759 vpe_dbg(ctx->dev, "Setting format for type %d, wxh: %dx%d, fmt: %d bpl_y %d",
1760 f->type, q_data->width, q_data->height, q_data->fmt->fourcc,
1761 q_data->bytesperline[VPE_LUMA]);
1762 if (q_data->nplanes == 2)
1763 vpe_dbg(ctx->dev, " bpl_uv %d\n",
1764 q_data->bytesperline[VPE_CHROMA]);
1765
1766 return 0;
1767 }
1768
1769 static int vpe_s_fmt(struct file *file, void *priv, struct v4l2_format *f)
1770 {
1771 int ret;
1772 struct vpe_ctx *ctx = file2ctx(file);
1773
1774 ret = vpe_try_fmt(file, priv, f);
1775 if (ret)
1776 return ret;
1777
1778 ret = __vpe_s_fmt(ctx, f);
1779 if (ret)
1780 return ret;
1781
1782 if (V4L2_TYPE_IS_OUTPUT(f->type))
1783 set_src_registers(ctx);
1784 else
1785 set_dst_registers(ctx);
1786
1787 return set_srcdst_params(ctx);
1788 }
1789
1790 static int __vpe_try_selection(struct vpe_ctx *ctx, struct v4l2_selection *s)
1791 {
1792 struct vpe_q_data *q_data;
1793 int height;
1794
1795 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1796 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1797 return -EINVAL;
1798
1799 q_data = get_q_data(ctx, s->type);
1800 if (!q_data)
1801 return -EINVAL;
1802
1803 switch (s->target) {
1804 case V4L2_SEL_TGT_COMPOSE:
1805 /*
1806 * COMPOSE target is only valid for capture buffer type, return
1807 * error for output buffer type
1808 */
1809 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1810 return -EINVAL;
1811 break;
1812 case V4L2_SEL_TGT_CROP:
1813 /*
1814 * CROP target is only valid for output buffer type, return
1815 * error for capture buffer type
1816 */
1817 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1818 return -EINVAL;
1819 break;
1820 /*
1821 * bound and default crop/compose targets are invalid targets to
1822 * try/set
1823 */
1824 default:
1825 return -EINVAL;
1826 }
1827
1828 /*
1829 * For SEQ_TB buffers, crop height should be less than the height of
1830 * the field height, not the buffer height
1831 */
1832 if (q_data->flags & Q_DATA_INTERLACED_SEQ_TB)
1833 height = q_data->height / 2;
1834 else
1835 height = q_data->height;
1836
1837 if (s->r.top < 0 || s->r.left < 0) {
1838 vpe_err(ctx->dev, "negative values for top and left\n");
1839 s->r.top = s->r.left = 0;
1840 }
1841
1842 v4l_bound_align_image(&s->r.width, MIN_W, q_data->width, 1,
1843 &s->r.height, MIN_H, height, H_ALIGN, S_ALIGN);
1844
1845 /* adjust left/top if cropping rectangle is out of bounds */
1846 if (s->r.left + s->r.width > q_data->width)
1847 s->r.left = q_data->width - s->r.width;
1848 if (s->r.top + s->r.height > q_data->height)
1849 s->r.top = q_data->height - s->r.height;
1850
1851 return 0;
1852 }
1853
1854 static int vpe_g_selection(struct file *file, void *fh,
1855 struct v4l2_selection *s)
1856 {
1857 struct vpe_ctx *ctx = file2ctx(file);
1858 struct vpe_q_data *q_data;
1859 bool use_c_rect = false;
1860
1861 if ((s->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
1862 (s->type != V4L2_BUF_TYPE_VIDEO_OUTPUT))
1863 return -EINVAL;
1864
1865 q_data = get_q_data(ctx, s->type);
1866 if (!q_data)
1867 return -EINVAL;
1868
1869 switch (s->target) {
1870 case V4L2_SEL_TGT_COMPOSE_DEFAULT:
1871 case V4L2_SEL_TGT_COMPOSE_BOUNDS:
1872 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1873 return -EINVAL;
1874 break;
1875 case V4L2_SEL_TGT_CROP_BOUNDS:
1876 case V4L2_SEL_TGT_CROP_DEFAULT:
1877 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1878 return -EINVAL;
1879 break;
1880 case V4L2_SEL_TGT_COMPOSE:
1881 if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
1882 return -EINVAL;
1883 use_c_rect = true;
1884 break;
1885 case V4L2_SEL_TGT_CROP:
1886 if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
1887 return -EINVAL;
1888 use_c_rect = true;
1889 break;
1890 default:
1891 return -EINVAL;
1892 }
1893
1894 if (use_c_rect) {
1895 /*
1896 * for CROP/COMPOSE target type, return c_rect params from the
1897 * respective buffer type
1898 */
1899 s->r = q_data->c_rect;
1900 } else {
1901 /*
1902 * for DEFAULT/BOUNDS target type, return width and height from
1903 * S_FMT of the respective buffer type
1904 */
1905 s->r.left = 0;
1906 s->r.top = 0;
1907 s->r.width = q_data->width;
1908 s->r.height = q_data->height;
1909 }
1910
1911 return 0;
1912 }
1913
1914
1915 static int vpe_s_selection(struct file *file, void *fh,
1916 struct v4l2_selection *s)
1917 {
1918 struct vpe_ctx *ctx = file2ctx(file);
1919 struct vpe_q_data *q_data;
1920 struct v4l2_selection sel = *s;
1921 int ret;
1922
1923 ret = __vpe_try_selection(ctx, &sel);
1924 if (ret)
1925 return ret;
1926
1927 q_data = get_q_data(ctx, sel.type);
1928 if (!q_data)
1929 return -EINVAL;
1930
1931 if ((q_data->c_rect.left == sel.r.left) &&
1932 (q_data->c_rect.top == sel.r.top) &&
1933 (q_data->c_rect.width == sel.r.width) &&
1934 (q_data->c_rect.height == sel.r.height)) {
1935 vpe_dbg(ctx->dev,
1936 "requested crop/compose values are already set\n");
1937 return 0;
1938 }
1939
1940 q_data->c_rect = sel.r;
1941
1942 return set_srcdst_params(ctx);
1943 }
1944
1945 /*
1946 * defines number of buffers/frames a context can process with VPE before
1947 * switching to a different context. default value is 1 buffer per context
1948 */
1949 #define V4L2_CID_VPE_BUFS_PER_JOB (V4L2_CID_USER_TI_VPE_BASE + 0)
1950
1951 static int vpe_s_ctrl(struct v4l2_ctrl *ctrl)
1952 {
1953 struct vpe_ctx *ctx =
1954 container_of(ctrl->handler, struct vpe_ctx, hdl);
1955
1956 switch (ctrl->id) {
1957 case V4L2_CID_VPE_BUFS_PER_JOB:
1958 ctx->bufs_per_job = ctrl->val;
1959 break;
1960
1961 default:
1962 vpe_err(ctx->dev, "Invalid control\n");
1963 return -EINVAL;
1964 }
1965
1966 return 0;
1967 }
1968
1969 static const struct v4l2_ctrl_ops vpe_ctrl_ops = {
1970 .s_ctrl = vpe_s_ctrl,
1971 };
1972
1973 static const struct v4l2_ioctl_ops vpe_ioctl_ops = {
1974 .vidioc_querycap = vpe_querycap,
1975
1976 .vidioc_enum_fmt_vid_cap_mplane = vpe_enum_fmt,
1977 .vidioc_g_fmt_vid_cap_mplane = vpe_g_fmt,
1978 .vidioc_try_fmt_vid_cap_mplane = vpe_try_fmt,
1979 .vidioc_s_fmt_vid_cap_mplane = vpe_s_fmt,
1980
1981 .vidioc_enum_fmt_vid_out_mplane = vpe_enum_fmt,
1982 .vidioc_g_fmt_vid_out_mplane = vpe_g_fmt,
1983 .vidioc_try_fmt_vid_out_mplane = vpe_try_fmt,
1984 .vidioc_s_fmt_vid_out_mplane = vpe_s_fmt,
1985
1986 .vidioc_g_selection = vpe_g_selection,
1987 .vidioc_s_selection = vpe_s_selection,
1988
1989 .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
1990 .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
1991 .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
1992 .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
1993 .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
1994 .vidioc_streamon = v4l2_m2m_ioctl_streamon,
1995 .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
1996
1997 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1998 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1999 };
2000
2001 /*
2002 * Queue operations
2003 */
2004 static int vpe_queue_setup(struct vb2_queue *vq,
2005 unsigned int *nbuffers, unsigned int *nplanes,
2006 unsigned int sizes[], struct device *alloc_devs[])
2007 {
2008 int i;
2009 struct vpe_ctx *ctx = vb2_get_drv_priv(vq);
2010 struct vpe_q_data *q_data;
2011
2012 q_data = get_q_data(ctx, vq->type);
2013
2014 *nplanes = q_data->nplanes;
2015
2016 for (i = 0; i < *nplanes; i++)
2017 sizes[i] = q_data->sizeimage[i];
2018
2019 vpe_dbg(ctx->dev, "get %d buffer(s) of size %d", *nbuffers,
2020 sizes[VPE_LUMA]);
2021 if (q_data->nplanes == 2)
2022 vpe_dbg(ctx->dev, " and %d\n", sizes[VPE_CHROMA]);
2023
2024 return 0;
2025 }
2026
2027 static int vpe_buf_prepare(struct vb2_buffer *vb)
2028 {
2029 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2030 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2031 struct vpe_q_data *q_data;
2032 int i, num_planes;
2033
2034 vpe_dbg(ctx->dev, "type: %d\n", vb->vb2_queue->type);
2035
2036 q_data = get_q_data(ctx, vb->vb2_queue->type);
2037 num_planes = q_data->nplanes;
2038
2039 if (vb->vb2_queue->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
2040 if (!(q_data->flags & Q_IS_INTERLACED)) {
2041 vbuf->field = V4L2_FIELD_NONE;
2042 } else {
2043 if (vbuf->field != V4L2_FIELD_TOP &&
2044 vbuf->field != V4L2_FIELD_BOTTOM &&
2045 vbuf->field != V4L2_FIELD_SEQ_TB)
2046 return -EINVAL;
2047 }
2048 }
2049
2050 for (i = 0; i < num_planes; i++) {
2051 if (vb2_plane_size(vb, i) < q_data->sizeimage[i]) {
2052 vpe_err(ctx->dev,
2053 "data will not fit into plane (%lu < %lu)\n",
2054 vb2_plane_size(vb, i),
2055 (long) q_data->sizeimage[i]);
2056 return -EINVAL;
2057 }
2058 }
2059
2060 for (i = 0; i < num_planes; i++)
2061 vb2_set_plane_payload(vb, i, q_data->sizeimage[i]);
2062
2063 return 0;
2064 }
2065
2066 static void vpe_buf_queue(struct vb2_buffer *vb)
2067 {
2068 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2069 struct vpe_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
2070
2071 v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
2072 }
2073
2074 static int check_srcdst_sizes(struct vpe_ctx *ctx)
2075 {
2076 struct vpe_q_data *s_q_data = &ctx->q_data[Q_DATA_SRC];
2077 struct vpe_q_data *d_q_data = &ctx->q_data[Q_DATA_DST];
2078 unsigned int src_w = s_q_data->c_rect.width;
2079 unsigned int src_h = s_q_data->c_rect.height;
2080 unsigned int dst_w = d_q_data->c_rect.width;
2081 unsigned int dst_h = d_q_data->c_rect.height;
2082
2083 if (src_w == dst_w && src_h == dst_h)
2084 return 0;
2085
2086 if (src_h <= SC_MAX_PIXEL_HEIGHT &&
2087 src_w <= SC_MAX_PIXEL_WIDTH &&
2088 dst_h <= SC_MAX_PIXEL_HEIGHT &&
2089 dst_w <= SC_MAX_PIXEL_WIDTH)
2090 return 0;
2091
2092 return -1;
2093 }
2094
2095 static void vpe_return_all_buffers(struct vpe_ctx *ctx, struct vb2_queue *q,
2096 enum vb2_buffer_state state)
2097 {
2098 struct vb2_v4l2_buffer *vb;
2099 unsigned long flags;
2100
2101 for (;;) {
2102 if (V4L2_TYPE_IS_OUTPUT(q->type))
2103 vb = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
2104 else
2105 vb = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
2106 if (!vb)
2107 break;
2108 spin_lock_irqsave(&ctx->dev->lock, flags);
2109 v4l2_m2m_buf_done(vb, state);
2110 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2111 }
2112
2113 /*
2114 * Cleanup the in-transit vb2 buffers that have been
2115 * removed from their respective queue already but for
2116 * which procecessing has not been completed yet.
2117 */
2118 if (V4L2_TYPE_IS_OUTPUT(q->type)) {
2119 spin_lock_irqsave(&ctx->dev->lock, flags);
2120
2121 if (ctx->src_vbs[2])
2122 v4l2_m2m_buf_done(ctx->src_vbs[2], state);
2123
2124 if (ctx->src_vbs[1] && (ctx->src_vbs[1] != ctx->src_vbs[2]))
2125 v4l2_m2m_buf_done(ctx->src_vbs[1], state);
2126
2127 if (ctx->src_vbs[0] &&
2128 (ctx->src_vbs[0] != ctx->src_vbs[1]) &&
2129 (ctx->src_vbs[0] != ctx->src_vbs[2]))
2130 v4l2_m2m_buf_done(ctx->src_vbs[0], state);
2131
2132 ctx->src_vbs[2] = NULL;
2133 ctx->src_vbs[1] = NULL;
2134 ctx->src_vbs[0] = NULL;
2135
2136 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2137 } else {
2138 if (ctx->dst_vb) {
2139 spin_lock_irqsave(&ctx->dev->lock, flags);
2140
2141 v4l2_m2m_buf_done(ctx->dst_vb, state);
2142 ctx->dst_vb = NULL;
2143 spin_unlock_irqrestore(&ctx->dev->lock, flags);
2144 }
2145 }
2146 }
2147
2148 static int vpe_start_streaming(struct vb2_queue *q, unsigned int count)
2149 {
2150 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2151
2152 /* Check any of the size exceed maximum scaling sizes */
2153 if (check_srcdst_sizes(ctx)) {
2154 vpe_err(ctx->dev,
2155 "Conversion setup failed, check source and destination parameters\n"
2156 );
2157 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_QUEUED);
2158 return -EINVAL;
2159 }
2160
2161 if (ctx->deinterlacing)
2162 config_edi_input_mode(ctx, 0x0);
2163
2164 if (ctx->sequence != 0)
2165 set_srcdst_params(ctx);
2166
2167 return 0;
2168 }
2169
2170 static void vpe_stop_streaming(struct vb2_queue *q)
2171 {
2172 struct vpe_ctx *ctx = vb2_get_drv_priv(q);
2173
2174 vpe_dump_regs(ctx->dev);
2175 vpdma_dump_regs(ctx->dev->vpdma);
2176
2177 vpe_return_all_buffers(ctx, q, VB2_BUF_STATE_ERROR);
2178 }
2179
2180 static const struct vb2_ops vpe_qops = {
2181 .queue_setup = vpe_queue_setup,
2182 .buf_prepare = vpe_buf_prepare,
2183 .buf_queue = vpe_buf_queue,
2184 .wait_prepare = vb2_ops_wait_prepare,
2185 .wait_finish = vb2_ops_wait_finish,
2186 .start_streaming = vpe_start_streaming,
2187 .stop_streaming = vpe_stop_streaming,
2188 };
2189
2190 static int queue_init(void *priv, struct vb2_queue *src_vq,
2191 struct vb2_queue *dst_vq)
2192 {
2193 struct vpe_ctx *ctx = priv;
2194 struct vpe_dev *dev = ctx->dev;
2195 int ret;
2196
2197 memset(src_vq, 0, sizeof(*src_vq));
2198 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
2199 src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2200 src_vq->drv_priv = ctx;
2201 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2202 src_vq->ops = &vpe_qops;
2203 src_vq->mem_ops = &vb2_dma_contig_memops;
2204 src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2205 src_vq->lock = &dev->dev_mutex;
2206 src_vq->dev = dev->v4l2_dev.dev;
2207
2208 ret = vb2_queue_init(src_vq);
2209 if (ret)
2210 return ret;
2211
2212 memset(dst_vq, 0, sizeof(*dst_vq));
2213 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
2214 dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
2215 dst_vq->drv_priv = ctx;
2216 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
2217 dst_vq->ops = &vpe_qops;
2218 dst_vq->mem_ops = &vb2_dma_contig_memops;
2219 dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
2220 dst_vq->lock = &dev->dev_mutex;
2221 dst_vq->dev = dev->v4l2_dev.dev;
2222
2223 return vb2_queue_init(dst_vq);
2224 }
2225
2226 static const struct v4l2_ctrl_config vpe_bufs_per_job = {
2227 .ops = &vpe_ctrl_ops,
2228 .id = V4L2_CID_VPE_BUFS_PER_JOB,
2229 .name = "Buffers Per Transaction",
2230 .type = V4L2_CTRL_TYPE_INTEGER,
2231 .def = VPE_DEF_BUFS_PER_JOB,
2232 .min = 1,
2233 .max = VIDEO_MAX_FRAME,
2234 .step = 1,
2235 };
2236
2237 /*
2238 * File operations
2239 */
2240 static int vpe_open(struct file *file)
2241 {
2242 struct vpe_dev *dev = video_drvdata(file);
2243 struct vpe_q_data *s_q_data;
2244 struct v4l2_ctrl_handler *hdl;
2245 struct vpe_ctx *ctx;
2246 int ret;
2247
2248 vpe_dbg(dev, "vpe_open\n");
2249
2250 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2251 if (!ctx)
2252 return -ENOMEM;
2253
2254 ctx->dev = dev;
2255
2256 if (mutex_lock_interruptible(&dev->dev_mutex)) {
2257 ret = -ERESTARTSYS;
2258 goto free_ctx;
2259 }
2260
2261 ret = vpdma_create_desc_list(&ctx->desc_list, VPE_DESC_LIST_SIZE,
2262 VPDMA_LIST_TYPE_NORMAL);
2263 if (ret != 0)
2264 goto unlock;
2265
2266 ret = vpdma_alloc_desc_buf(&ctx->mmr_adb, sizeof(struct vpe_mmr_adb));
2267 if (ret != 0)
2268 goto free_desc_list;
2269
2270 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_h, SC_COEF_SRAM_SIZE);
2271 if (ret != 0)
2272 goto free_mmr_adb;
2273
2274 ret = vpdma_alloc_desc_buf(&ctx->sc_coeff_v, SC_COEF_SRAM_SIZE);
2275 if (ret != 0)
2276 goto free_sc_h;
2277
2278 init_adb_hdrs(ctx);
2279
2280 v4l2_fh_init(&ctx->fh, video_devdata(file));
2281 file->private_data = &ctx->fh;
2282
2283 hdl = &ctx->hdl;
2284 v4l2_ctrl_handler_init(hdl, 1);
2285 v4l2_ctrl_new_custom(hdl, &vpe_bufs_per_job, NULL);
2286 if (hdl->error) {
2287 ret = hdl->error;
2288 goto exit_fh;
2289 }
2290 ctx->fh.ctrl_handler = hdl;
2291 v4l2_ctrl_handler_setup(hdl);
2292
2293 s_q_data = &ctx->q_data[Q_DATA_SRC];
2294 s_q_data->fmt = &vpe_formats[2];
2295 s_q_data->width = 1920;
2296 s_q_data->height = 1080;
2297 s_q_data->nplanes = 1;
2298 s_q_data->bytesperline[VPE_LUMA] = (s_q_data->width *
2299 s_q_data->fmt->vpdma_fmt[VPE_LUMA]->depth) >> 3;
2300 s_q_data->sizeimage[VPE_LUMA] = (s_q_data->bytesperline[VPE_LUMA] *
2301 s_q_data->height);
2302 s_q_data->colorspace = V4L2_COLORSPACE_REC709;
2303 s_q_data->field = V4L2_FIELD_NONE;
2304 s_q_data->c_rect.left = 0;
2305 s_q_data->c_rect.top = 0;
2306 s_q_data->c_rect.width = s_q_data->width;
2307 s_q_data->c_rect.height = s_q_data->height;
2308 s_q_data->flags = 0;
2309
2310 ctx->q_data[Q_DATA_DST] = *s_q_data;
2311
2312 set_dei_shadow_registers(ctx);
2313 set_src_registers(ctx);
2314 set_dst_registers(ctx);
2315 ret = set_srcdst_params(ctx);
2316 if (ret)
2317 goto exit_fh;
2318
2319 ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
2320
2321 if (IS_ERR(ctx->fh.m2m_ctx)) {
2322 ret = PTR_ERR(ctx->fh.m2m_ctx);
2323 goto exit_fh;
2324 }
2325
2326 v4l2_fh_add(&ctx->fh);
2327
2328 /*
2329 * for now, just report the creation of the first instance, we can later
2330 * optimize the driver to enable or disable clocks when the first
2331 * instance is created or the last instance released
2332 */
2333 if (atomic_inc_return(&dev->num_instances) == 1)
2334 vpe_dbg(dev, "first instance created\n");
2335
2336 ctx->bufs_per_job = VPE_DEF_BUFS_PER_JOB;
2337
2338 ctx->load_mmrs = true;
2339
2340 vpe_dbg(dev, "created instance %p, m2m_ctx: %p\n",
2341 ctx, ctx->fh.m2m_ctx);
2342
2343 mutex_unlock(&dev->dev_mutex);
2344
2345 return 0;
2346 exit_fh:
2347 v4l2_ctrl_handler_free(hdl);
2348 v4l2_fh_exit(&ctx->fh);
2349 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2350 free_sc_h:
2351 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2352 free_mmr_adb:
2353 vpdma_free_desc_buf(&ctx->mmr_adb);
2354 free_desc_list:
2355 vpdma_free_desc_list(&ctx->desc_list);
2356 unlock:
2357 mutex_unlock(&dev->dev_mutex);
2358 free_ctx:
2359 kfree(ctx);
2360 return ret;
2361 }
2362
2363 static int vpe_release(struct file *file)
2364 {
2365 struct vpe_dev *dev = video_drvdata(file);
2366 struct vpe_ctx *ctx = file2ctx(file);
2367
2368 vpe_dbg(dev, "releasing instance %p\n", ctx);
2369
2370 mutex_lock(&dev->dev_mutex);
2371 free_mv_buffers(ctx);
2372 vpdma_free_desc_list(&ctx->desc_list);
2373 vpdma_free_desc_buf(&ctx->mmr_adb);
2374
2375 vpdma_free_desc_buf(&ctx->sc_coeff_v);
2376 vpdma_free_desc_buf(&ctx->sc_coeff_h);
2377
2378 v4l2_fh_del(&ctx->fh);
2379 v4l2_fh_exit(&ctx->fh);
2380 v4l2_ctrl_handler_free(&ctx->hdl);
2381 v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
2382
2383 kfree(ctx);
2384
2385 /*
2386 * for now, just report the release of the last instance, we can later
2387 * optimize the driver to enable or disable clocks when the first
2388 * instance is created or the last instance released
2389 */
2390 if (atomic_dec_return(&dev->num_instances) == 0)
2391 vpe_dbg(dev, "last instance released\n");
2392
2393 mutex_unlock(&dev->dev_mutex);
2394
2395 return 0;
2396 }
2397
2398 static const struct v4l2_file_operations vpe_fops = {
2399 .owner = THIS_MODULE,
2400 .open = vpe_open,
2401 .release = vpe_release,
2402 .poll = v4l2_m2m_fop_poll,
2403 .unlocked_ioctl = video_ioctl2,
2404 .mmap = v4l2_m2m_fop_mmap,
2405 };
2406
2407 static const struct video_device vpe_videodev = {
2408 .name = VPE_MODULE_NAME,
2409 .fops = &vpe_fops,
2410 .ioctl_ops = &vpe_ioctl_ops,
2411 .minor = -1,
2412 .release = video_device_release_empty,
2413 .vfl_dir = VFL_DIR_M2M,
2414 };
2415
2416 static const struct v4l2_m2m_ops m2m_ops = {
2417 .device_run = device_run,
2418 .job_ready = job_ready,
2419 .job_abort = job_abort,
2420 };
2421
2422 static int vpe_runtime_get(struct platform_device *pdev)
2423 {
2424 int r;
2425
2426 dev_dbg(&pdev->dev, "vpe_runtime_get\n");
2427
2428 r = pm_runtime_get_sync(&pdev->dev);
2429 WARN_ON(r < 0);
2430 return r < 0 ? r : 0;
2431 }
2432
2433 static void vpe_runtime_put(struct platform_device *pdev)
2434 {
2435
2436 int r;
2437
2438 dev_dbg(&pdev->dev, "vpe_runtime_put\n");
2439
2440 r = pm_runtime_put_sync(&pdev->dev);
2441 WARN_ON(r < 0 && r != -ENOSYS);
2442 }
2443
2444 static void vpe_fw_cb(struct platform_device *pdev)
2445 {
2446 struct vpe_dev *dev = platform_get_drvdata(pdev);
2447 struct video_device *vfd;
2448 int ret;
2449
2450 vfd = &dev->vfd;
2451 *vfd = vpe_videodev;
2452 vfd->lock = &dev->dev_mutex;
2453 vfd->v4l2_dev = &dev->v4l2_dev;
2454
2455 ret = video_register_device(vfd, VFL_TYPE_GRABBER, 0);
2456 if (ret) {
2457 vpe_err(dev, "Failed to register video device\n");
2458
2459 vpe_set_clock_enable(dev, 0);
2460 vpe_runtime_put(pdev);
2461 pm_runtime_disable(&pdev->dev);
2462 v4l2_m2m_release(dev->m2m_dev);
2463 v4l2_device_unregister(&dev->v4l2_dev);
2464
2465 return;
2466 }
2467
2468 video_set_drvdata(vfd, dev);
2469 dev_info(dev->v4l2_dev.dev, "Device registered as /dev/video%d\n",
2470 vfd->num);
2471 }
2472
2473 static int vpe_probe(struct platform_device *pdev)
2474 {
2475 struct vpe_dev *dev;
2476 int ret, irq, func;
2477
2478 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
2479 if (!dev)
2480 return -ENOMEM;
2481
2482 spin_lock_init(&dev->lock);
2483
2484 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
2485 if (ret)
2486 return ret;
2487
2488 atomic_set(&dev->num_instances, 0);
2489 mutex_init(&dev->dev_mutex);
2490
2491 dev->res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2492 "vpe_top");
2493 /*
2494 * HACK: we get resource info from device tree in the form of a list of
2495 * VPE sub blocks, the driver currently uses only the base of vpe_top
2496 * for register access, the driver should be changed later to access
2497 * registers based on the sub block base addresses
2498 */
2499 dev->base = devm_ioremap(&pdev->dev, dev->res->start, SZ_32K);
2500 if (!dev->base) {
2501 ret = -ENOMEM;
2502 goto v4l2_dev_unreg;
2503 }
2504
2505 irq = platform_get_irq(pdev, 0);
2506 ret = devm_request_irq(&pdev->dev, irq, vpe_irq, 0, VPE_MODULE_NAME,
2507 dev);
2508 if (ret)
2509 goto v4l2_dev_unreg;
2510
2511 platform_set_drvdata(pdev, dev);
2512
2513 dev->m2m_dev = v4l2_m2m_init(&m2m_ops);
2514 if (IS_ERR(dev->m2m_dev)) {
2515 vpe_err(dev, "Failed to init mem2mem device\n");
2516 ret = PTR_ERR(dev->m2m_dev);
2517 goto v4l2_dev_unreg;
2518 }
2519
2520 pm_runtime_enable(&pdev->dev);
2521
2522 ret = vpe_runtime_get(pdev);
2523 if (ret)
2524 goto rel_m2m;
2525
2526 /* Perform clk enable followed by reset */
2527 vpe_set_clock_enable(dev, 1);
2528
2529 vpe_top_reset(dev);
2530
2531 func = read_field_reg(dev, VPE_PID, VPE_PID_FUNC_MASK,
2532 VPE_PID_FUNC_SHIFT);
2533 vpe_dbg(dev, "VPE PID function %x\n", func);
2534
2535 vpe_top_vpdma_reset(dev);
2536
2537 dev->sc = sc_create(pdev, "sc");
2538 if (IS_ERR(dev->sc)) {
2539 ret = PTR_ERR(dev->sc);
2540 goto runtime_put;
2541 }
2542
2543 dev->csc = csc_create(pdev, "csc");
2544 if (IS_ERR(dev->csc)) {
2545 ret = PTR_ERR(dev->csc);
2546 goto runtime_put;
2547 }
2548
2549 dev->vpdma = &dev->vpdma_data;
2550 ret = vpdma_create(pdev, dev->vpdma, vpe_fw_cb);
2551 if (ret)
2552 goto runtime_put;
2553
2554 return 0;
2555
2556 runtime_put:
2557 vpe_runtime_put(pdev);
2558 rel_m2m:
2559 pm_runtime_disable(&pdev->dev);
2560 v4l2_m2m_release(dev->m2m_dev);
2561 v4l2_dev_unreg:
2562 v4l2_device_unregister(&dev->v4l2_dev);
2563
2564 return ret;
2565 }
2566
2567 static int vpe_remove(struct platform_device *pdev)
2568 {
2569 struct vpe_dev *dev = platform_get_drvdata(pdev);
2570
2571 v4l2_info(&dev->v4l2_dev, "Removing " VPE_MODULE_NAME);
2572
2573 v4l2_m2m_release(dev->m2m_dev);
2574 video_unregister_device(&dev->vfd);
2575 v4l2_device_unregister(&dev->v4l2_dev);
2576
2577 vpe_set_clock_enable(dev, 0);
2578 vpe_runtime_put(pdev);
2579 pm_runtime_disable(&pdev->dev);
2580
2581 return 0;
2582 }
2583
2584 #if defined(CONFIG_OF)
2585 static const struct of_device_id vpe_of_match[] = {
2586 {
2587 .compatible = "ti,vpe",
2588 },
2589 {},
2590 };
2591 MODULE_DEVICE_TABLE(of, vpe_of_match);
2592 #endif
2593
2594 static struct platform_driver vpe_pdrv = {
2595 .probe = vpe_probe,
2596 .remove = vpe_remove,
2597 .driver = {
2598 .name = VPE_MODULE_NAME,
2599 .of_match_table = of_match_ptr(vpe_of_match),
2600 },
2601 };
2602
2603 module_platform_driver(vpe_pdrv);
2604
2605 MODULE_DESCRIPTION("TI VPE driver");
2606 MODULE_AUTHOR("Dale Farnsworth, <dale@farnsworth.org>");
2607 MODULE_LICENSE("GPL");
Linux with added FPC-III support