drivers/misc/cxl/cxl.h

   1 /*
   2  * Copyright 2014 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #ifndef _CXL_H_
  11 #define _CXL_H_
  12
  13 #include <linux/interrupt.h>
  14 #include <linux/semaphore.h>
  15 #include <linux/device.h>
  16 #include <linux/types.h>
  17 #include <linux/cdev.h>
  18 #include <linux/pid.h>
  19 #include <linux/io.h>
  20 #include <linux/pci.h>
  21 #include <linux/fs.h>
  22 #include <asm/cputable.h>
  23 #include <asm/mmu.h>
  24 #include <asm/reg.h>
  25 #include <misc/cxl-base.h>
  26
  27 #include <misc/cxl.h>
  28 #include <uapi/misc/cxl.h>
  29
  30 extern uint cxl_verbose;
  31
  32 #define CXL_TIMEOUT 5
  33
  34 /*
  35  * Bump version each time a user API change is made, whether it is
  36  * backwards compatible ot not.
  37  */
  38 #define CXL_API_VERSION 3
  39 #define CXL_API_VERSION_COMPATIBLE 1
  40
  41 /*
  42  * Opaque types to avoid accidentally passing registers for the wrong MMIO
  43  *
  44  * At the end of the day, I'm not married to using typedef here, but it might
  45  * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
  46  * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
  47  *
  48  * I'm quite happy if these are changed back to #defines before upstreaming, it
  49  * should be little more than a regexp search+replace operation in this file.
  50  */
  51 typedef struct {
  52         const int x;
  53 } cxl_p1_reg_t;
  54 typedef struct {
  55         const int x;
  56 } cxl_p1n_reg_t;
  57 typedef struct {
  58         const int x;
  59 } cxl_p2n_reg_t;
  60 #define cxl_reg_off(reg) \
  61         (reg.x)
  62
  63 /* Memory maps. Ref CXL Appendix A */
  64
  65 /* PSL Privilege 1 Memory Map */
  66 /* Configuration and Control area - CAIA 1&2 */
  67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
  68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
  69 static const cxl_p1_reg_t CXL_PSL_KEY1    = {0x0010};
  70 static const cxl_p1_reg_t CXL_PSL_KEY2    = {0x0018};
  71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
  72 /* Downloading */
  73 static const cxl_p1_reg_t CXL_PSL_DLCNTL  = {0x0060};
  74 static const cxl_p1_reg_t CXL_PSL_DLADDR  = {0x0068};
  75
  76 /* PSL Lookaside Buffer Management Area - CAIA 1 */
  77 static const cxl_p1_reg_t CXL_PSL_LBISEL  = {0x0080};
  78 static const cxl_p1_reg_t CXL_PSL_SLBIE   = {0x0088};
  79 static const cxl_p1_reg_t CXL_PSL_SLBIA   = {0x0090};
  80 static const cxl_p1_reg_t CXL_PSL_TLBIE   = {0x00A0};
  81 static const cxl_p1_reg_t CXL_PSL_TLBIA   = {0x00A8};
  82 static const cxl_p1_reg_t CXL_PSL_AFUSEL  = {0x00B0};
  83
  84 /* 0x00C0:7EFF Implementation dependent area */
  85 /* PSL registers - CAIA 1 */
  86 static const cxl_p1_reg_t CXL_PSL_FIR1      = {0x0100};
  87 static const cxl_p1_reg_t CXL_PSL_FIR2      = {0x0108};
  88 static const cxl_p1_reg_t CXL_PSL_Timebase  = {0x0110};
  89 static const cxl_p1_reg_t CXL_PSL_VERSION   = {0x0118};
  90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO  = {0x0128};
  91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
  92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL  = {0x0148};
  93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL   = {0x0150};
  94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
  95 static const cxl_p1_reg_t CXL_PSL_TRACE     = {0x0170};
  96 /* PSL registers - CAIA 2 */
  97 static const cxl_p1_reg_t CXL_PSL9_CONTROL  = {0x0020};
  98 static const cxl_p1_reg_t CXL_XSL9_INV      = {0x0110};
  99 static const cxl_p1_reg_t CXL_XSL9_DBG      = {0x0130};
 100 static const cxl_p1_reg_t CXL_XSL9_DEF      = {0x0140};
 101 static const cxl_p1_reg_t CXL_XSL9_DSNCTL   = {0x0168};
 102 static const cxl_p1_reg_t CXL_PSL9_FIR1     = {0x0300};
 103 static const cxl_p1_reg_t CXL_PSL9_FIR_MASK = {0x0308};
 104 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
 105 static const cxl_p1_reg_t CXL_PSL9_DEBUG    = {0x0320};
 106 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
 107 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL  = {0x0350};
 108 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
 109 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
 110 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
 111 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
 112 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
 113 static const cxl_p1_reg_t CXL_PSL9_CTCCFG = {0x0390};
 114 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
 115 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
 116 static const cxl_p1_reg_t CXL_XSL9_ILPP  = {0x0590};
 117
 118 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
 119 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
 120
 121 /* PSL Slice Privilege 1 Memory Map */
 122 /* Configuration Area - CAIA 1&2 */
 123 static const cxl_p1n_reg_t CXL_PSL_SR_An          = {0x00};
 124 static const cxl_p1n_reg_t CXL_PSL_LPID_An        = {0x08};
 125 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An       = {0x10};
 126 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An    = {0x18};
 127 static const cxl_p1n_reg_t CXL_PSL_ID_An          = {0x20};
 128 static const cxl_p1n_reg_t CXL_PSL_SERR_An        = {0x28};
 129 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
 130 static const cxl_p1n_reg_t CXL_PSL_SDR_An         = {0x30};
 131 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
 132 static const cxl_p1n_reg_t CXL_PSL_AMOR_An        = {0x38};
 133 /* Pointer Area - CAIA 1&2 */
 134 static const cxl_p1n_reg_t CXL_HAURP_An           = {0x80};
 135 static const cxl_p1n_reg_t CXL_PSL_SPAP_An        = {0x88};
 136 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An       = {0x90};
 137 /* Control Area - CAIA 1&2 */
 138 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An       = {0xA0};
 139 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An     = {0xA8};
 140 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
 141 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An  = {0xB8};
 142 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
 143 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An   = {0xC0};
 144 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An       = {0xC8};
 145 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
 146 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A     = {0xD0};
 147 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A      = {0xD8};
 148 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A        = {0xE0};
 149 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE    = {0xE8};
 150
 151 /* PSL Slice Privilege 2 Memory Map */
 152 /* Configuration and Control Area - CAIA 1&2 */
 153 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
 154 static const cxl_p2n_reg_t CXL_CSRP_An        = {0x008};
 155 /* Configuration and Control Area - CAIA 1 */
 156 static const cxl_p2n_reg_t CXL_AURP0_An       = {0x010};
 157 static const cxl_p2n_reg_t CXL_AURP1_An       = {0x018};
 158 static const cxl_p2n_reg_t CXL_SSTP0_An       = {0x020};
 159 static const cxl_p2n_reg_t CXL_SSTP1_An       = {0x028};
 160 /* Configuration and Control Area - CAIA 1 */
 161 static const cxl_p2n_reg_t CXL_PSL_AMR_An     = {0x030};
 162 /* Segment Lookaside Buffer Management - CAIA 1 */
 163 static const cxl_p2n_reg_t CXL_SLBIE_An       = {0x040};
 164 static const cxl_p2n_reg_t CXL_SLBIA_An       = {0x048};
 165 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
 166 /* Interrupt Registers - CAIA 1&2 */
 167 static const cxl_p2n_reg_t CXL_PSL_DSISR_An   = {0x060};
 168 static const cxl_p2n_reg_t CXL_PSL_DAR_An     = {0x068};
 169 static const cxl_p2n_reg_t CXL_PSL_DSR_An     = {0x070};
 170 static const cxl_p2n_reg_t CXL_PSL_TFC_An     = {0x078};
 171 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
 172 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
 173 /* AFU Registers - CAIA 1&2 */
 174 static const cxl_p2n_reg_t CXL_AFU_Cntl_An    = {0x090};
 175 static const cxl_p2n_reg_t CXL_AFU_ERR_An     = {0x098};
 176 /* Work Element Descriptor - CAIA 1&2 */
 177 static const cxl_p2n_reg_t CXL_PSL_WED_An     = {0x0A0};
 178 /* 0x0C0:FFF Implementation Dependent Area */
 179
 180 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
 181 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
 182 #define CXL_PSL_SPAP_Size_Shift 4
 183 #define CXL_PSL_SPAP_V    0x0000000000000001ULL
 184
 185 /****** CXL_PSL_Control ****************************************************/
 186 #define CXL_PSL_Control_tb              (0x1ull << (63-63))
 187 #define CXL_PSL_Control_Fr              (0x1ull << (63-31))
 188 #define CXL_PSL_Control_Fs_MASK         (0x3ull << (63-29))
 189 #define CXL_PSL_Control_Fs_Complete     (0x3ull << (63-29))
 190
 191 /****** CXL_PSL_DLCNTL *****************************************************/
 192 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
 193 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
 194 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
 195 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
 196 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
 197 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
 198
 199 /****** CXL_PSL_SR_An ******************************************************/
 200 #define CXL_PSL_SR_An_SF  MSR_SF            /* 64bit */
 201 #define CXL_PSL_SR_An_TA  (1ull << (63-1))  /* Tags active,   GA1: 0 */
 202 #define CXL_PSL_SR_An_HV  MSR_HV            /* Hypervisor,    GA1: 0 */
 203 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
 204 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
 205 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
 206 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
 207 #define CXL_PSL_SR_An_PR  MSR_PR            /* Problem state, GA1: 1 */
 208 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
 209 #define CXL_PSL_SR_An_TC  (1ull << (63-54)) /* Page Table secondary hash */
 210 #define CXL_PSL_SR_An_US  (1ull << (63-56)) /* User state,    GA1: X */
 211 #define CXL_PSL_SR_An_SC  (1ull << (63-58)) /* Segment Table secondary hash */
 212 #define CXL_PSL_SR_An_R   MSR_DR            /* Relocate,      GA1: 1 */
 213 #define CXL_PSL_SR_An_MP  (1ull << (63-62)) /* Master Process */
 214 #define CXL_PSL_SR_An_LE  (1ull << (63-63)) /* Little Endian */
 215
 216 /****** CXL_PSL_ID_An ****************************************************/
 217 #define CXL_PSL_ID_An_F (1ull << (63-31))
 218 #define CXL_PSL_ID_An_L (1ull << (63-30))
 219
 220 /****** CXL_PSL_SERR_An ****************************************************/
 221 #define CXL_PSL_SERR_An_afuto   (1ull << (63-0))
 222 #define CXL_PSL_SERR_An_afudis  (1ull << (63-1))
 223 #define CXL_PSL_SERR_An_afuov   (1ull << (63-2))
 224 #define CXL_PSL_SERR_An_badsrc  (1ull << (63-3))
 225 #define CXL_PSL_SERR_An_badctx  (1ull << (63-4))
 226 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
 227 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
 228 #define CXL_PSL_SERR_An_afupar  (1ull << (63-7))
 229 #define CXL_PSL_SERR_An_afudup  (1ull << (63-8))
 230 #define CXL_PSL_SERR_An_IRQS    ( \
 231         CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
 232         CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
 233         CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
 234 #define CXL_PSL_SERR_An_afuto_mask      (1ull << (63-32))
 235 #define CXL_PSL_SERR_An_afudis_mask     (1ull << (63-33))
 236 #define CXL_PSL_SERR_An_afuov_mask      (1ull << (63-34))
 237 #define CXL_PSL_SERR_An_badsrc_mask     (1ull << (63-35))
 238 #define CXL_PSL_SERR_An_badctx_mask     (1ull << (63-36))
 239 #define CXL_PSL_SERR_An_llcmdis_mask    (1ull << (63-37))
 240 #define CXL_PSL_SERR_An_llcmdto_mask    (1ull << (63-38))
 241 #define CXL_PSL_SERR_An_afupar_mask     (1ull << (63-39))
 242 #define CXL_PSL_SERR_An_afudup_mask     (1ull << (63-40))
 243 #define CXL_PSL_SERR_An_IRQ_MASKS       ( \
 244         CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
 245         CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
 246         CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
 247
 248 #define CXL_PSL_SERR_An_AE      (1ull << (63-30))
 249
 250 /****** CXL_PSL_SCNTL_An ****************************************************/
 251 #define CXL_PSL_SCNTL_An_CR          (0x1ull << (63-15))
 252 /* Programming Modes: */
 253 #define CXL_PSL_SCNTL_An_PM_MASK     (0xffffull << (63-31))
 254 #define CXL_PSL_SCNTL_An_PM_Shared   (0x0000ull << (63-31))
 255 #define CXL_PSL_SCNTL_An_PM_OS       (0x0001ull << (63-31))
 256 #define CXL_PSL_SCNTL_An_PM_Process  (0x0002ull << (63-31))
 257 #define CXL_PSL_SCNTL_An_PM_AFU      (0x0004ull << (63-31))
 258 #define CXL_PSL_SCNTL_An_PM_AFU_PBT  (0x0104ull << (63-31))
 259 /* Purge Status (ro) */
 260 #define CXL_PSL_SCNTL_An_Ps_MASK     (0x3ull << (63-39))
 261 #define CXL_PSL_SCNTL_An_Ps_Pending  (0x1ull << (63-39))
 262 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
 263 /* Purge */
 264 #define CXL_PSL_SCNTL_An_Pc          (0x1ull << (63-48))
 265 /* Suspend Status (ro) */
 266 #define CXL_PSL_SCNTL_An_Ss_MASK     (0x3ull << (63-55))
 267 #define CXL_PSL_SCNTL_An_Ss_Pending  (0x1ull << (63-55))
 268 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
 269 /* Suspend Control */
 270 #define CXL_PSL_SCNTL_An_Sc          (0x1ull << (63-63))
 271
 272 /* AFU Slice Enable Status (ro) */
 273 #define CXL_AFU_Cntl_An_ES_MASK     (0x7ull << (63-2))
 274 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
 275 #define CXL_AFU_Cntl_An_ES_Enabled  (0x4ull << (63-2))
 276 /* AFU Slice Enable */
 277 #define CXL_AFU_Cntl_An_E           (0x1ull << (63-3))
 278 /* AFU Slice Reset status (ro) */
 279 #define CXL_AFU_Cntl_An_RS_MASK     (0x3ull << (63-5))
 280 #define CXL_AFU_Cntl_An_RS_Pending  (0x1ull << (63-5))
 281 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
 282 /* AFU Slice Reset */
 283 #define CXL_AFU_Cntl_An_RA          (0x1ull << (63-7))
 284
 285 /****** CXL_SSTP0/1_An ******************************************************/
 286 /* These top bits are for the segment that CONTAINS the segment table */
 287 #define CXL_SSTP0_An_B_SHIFT    SLB_VSID_SSIZE_SHIFT
 288 #define CXL_SSTP0_An_KS             (1ull << (63-2))
 289 #define CXL_SSTP0_An_KP             (1ull << (63-3))
 290 #define CXL_SSTP0_An_N              (1ull << (63-4))
 291 #define CXL_SSTP0_An_L              (1ull << (63-5))
 292 #define CXL_SSTP0_An_C              (1ull << (63-6))
 293 #define CXL_SSTP0_An_TA             (1ull << (63-7))
 294 #define CXL_SSTP0_An_LP_SHIFT                (63-9)  /* 2 Bits */
 295 /* And finally, the virtual address & size of the segment table: */
 296 #define CXL_SSTP0_An_SegTableSize_SHIFT      (63-31) /* 12 Bits */
 297 #define CXL_SSTP0_An_SegTableSize_MASK \
 298         (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
 299 #define CXL_SSTP0_An_STVA_U_MASK   ((1ull << (63-49))-1)
 300 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
 301 #define CXL_SSTP1_An_V              (1ull << (63-63))
 302
 303 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
 304 /* write: */
 305 #define CXL_SLBIE_C        PPC_BIT(36)         /* Class */
 306 #define CXL_SLBIE_SS       PPC_BITMASK(37, 38) /* Segment Size */
 307 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
 308 #define CXL_SLBIE_TA       PPC_BIT(38)         /* Tags Active */
 309 /* read: */
 310 #define CXL_SLBIE_MAX      PPC_BITMASK(24, 31)
 311 #define CXL_SLBIE_PENDING  PPC_BITMASK(56, 63)
 312
 313 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
 314 #define CXL_TLB_SLB_P          (1ull) /* Pending (read) */
 315
 316 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
 317 #define CXL_TLB_SLB_IQ_ALL     (0ull) /* Inv qualifier */
 318 #define CXL_TLB_SLB_IQ_LPID    (1ull) /* Inv qualifier */
 319 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
 320
 321 /****** CXL_PSL_AFUSEL ******************************************************/
 322 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
 323
 324 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
 325 #define CXL_PSL_DSISR_An_DS (1ull << (63-0))  /* Segment not found */
 326 #define CXL_PSL_DSISR_An_DM (1ull << (63-1))  /* PTE not found (See also: M) or protection fault */
 327 #define CXL_PSL_DSISR_An_ST (1ull << (63-2))  /* Segment Table PTE not found */
 328 #define CXL_PSL_DSISR_An_UR (1ull << (63-3))  /* AURP PTE not found */
 329 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
 330 #define CXL_PSL_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 331 #define CXL_PSL_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 332 #define CXL_PSL_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 333 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
 334 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
 335 #define CXL_PSL_DSISR_An_M  DSISR_NOHPTE      /* PTE not found */
 336 #define CXL_PSL_DSISR_An_P  DSISR_PROTFAULT   /* Storage protection violation */
 337 #define CXL_PSL_DSISR_An_A  (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
 338 #define CXL_PSL_DSISR_An_S  DSISR_ISSTORE     /* Access was afu_wr or afu_zero */
 339 #define CXL_PSL_DSISR_An_K  DSISR_KEYFAULT    /* Access not permitted by virtual page class key protection */
 340
 341 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
 342 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3))  /* Translation fault */
 343 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4))  /* PSL Error (implementation specific) */
 344 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5))  /* AFU Error */
 345 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6))  /* OS Context Warning */
 346 #define CXL_PSL9_DSISR_An_S (1ull << (63-38))  /* TF for a write operation */
 347 #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
 348 /*
 349  * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
 350  * Status (0:7) Encoding
 351  */
 352 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
 353 #define CXL_PSL9_DSISR_An_SF      0x0000000000000080ULL  /* Segment Fault                        0b10000000 */
 354 #define CXL_PSL9_DSISR_An_PF_SLR  0x0000000000000088ULL  /* PTE not found (Single Level Radix)   0b10001000 */
 355 #define CXL_PSL9_DSISR_An_PF_RGC  0x000000000000008CULL  /* PTE not found (Radix Guest (child))  0b10001100 */
 356 #define CXL_PSL9_DSISR_An_PF_RGP  0x0000000000000090ULL  /* PTE not found (Radix Guest (parent)) 0b10010000 */
 357 #define CXL_PSL9_DSISR_An_PF_HRH  0x0000000000000094ULL  /* PTE not found (HPT/Radix Host)       0b10010100 */
 358 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL  /* PTE not found (STEG VA)              0b10011100 */
 359 #define CXL_PSL9_DSISR_An_URTCH   0x00000000000000B4ULL  /* Unsupported Radix Tree Configuration 0b10110100 */
 360
 361 /****** CXL_PSL_TFC_An ******************************************************/
 362 #define CXL_PSL_TFC_An_A  (1ull << (63-28)) /* Acknowledge non-translation fault */
 363 #define CXL_PSL_TFC_An_C  (1ull << (63-29)) /* Continue (abort transaction) */
 364 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
 365 #define CXL_PSL_TFC_An_R  (1ull << (63-31)) /* Restart PSL transaction */
 366
 367 /****** CXL_PSL_DEBUG *****************************************************/
 368 #define CXL_PSL_DEBUG_CDC  (1ull << (63-27)) /* Coherent Data cache support */
 369
 370 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
 371 #define CXL_XSL9_IERAT_MLPID    (1ull << (63-0))  /* Match LPID */
 372 #define CXL_XSL9_IERAT_MPID     (1ull << (63-1))  /* Match PID */
 373 #define CXL_XSL9_IERAT_PRS      (1ull << (63-4))  /* PRS bit for Radix invalidations */
 374 #define CXL_XSL9_IERAT_INVR     (1ull << (63-3))  /* Invalidate Radix */
 375 #define CXL_XSL9_IERAT_IALL     (1ull << (63-8))  /* Invalidate All */
 376 #define CXL_XSL9_IERAT_IINPROG  (1ull << (63-63)) /* Invalidate in progress */
 377
 378 /* cxl_process_element->software_status */
 379 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 -  0)) /* Valid */
 380 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
 381 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
 382 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
 383
 384 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
 385  * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
 386  * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
 387  * of the hang pulse frequency.
 388  */
 389 #define CXL_PSL_RXCTL_AFUHP_4S      0x7000000000000000ULL
 390
 391 /* SPA->sw_command_status */
 392 #define CXL_SPA_SW_CMD_MASK         0xffff000000000000ULL
 393 #define CXL_SPA_SW_CMD_TERMINATE    0x0001000000000000ULL
 394 #define CXL_SPA_SW_CMD_REMOVE       0x0002000000000000ULL
 395 #define CXL_SPA_SW_CMD_SUSPEND      0x0003000000000000ULL
 396 #define CXL_SPA_SW_CMD_RESUME       0x0004000000000000ULL
 397 #define CXL_SPA_SW_CMD_ADD          0x0005000000000000ULL
 398 #define CXL_SPA_SW_CMD_UPDATE       0x0006000000000000ULL
 399 #define CXL_SPA_SW_STATE_MASK       0x0000ffff00000000ULL
 400 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
 401 #define CXL_SPA_SW_STATE_REMOVED    0x0000000200000000ULL
 402 #define CXL_SPA_SW_STATE_SUSPENDED  0x0000000300000000ULL
 403 #define CXL_SPA_SW_STATE_RESUMED    0x0000000400000000ULL
 404 #define CXL_SPA_SW_STATE_ADDED      0x0000000500000000ULL
 405 #define CXL_SPA_SW_STATE_UPDATED    0x0000000600000000ULL
 406 #define CXL_SPA_SW_PSL_ID_MASK      0x00000000ffff0000ULL
 407 #define CXL_SPA_SW_LINK_MASK        0x000000000000ffffULL
 408
 409 #define CXL_MAX_SLICES 4
 410 #define MAX_AFU_MMIO_REGS 3
 411
 412 #define CXL_MODE_TIME_SLICED 0x4
 413 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
 414
 415 #define CXL_DEV_MINORS 13   /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
 416 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
 417 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
 418
 419 #define CXL_PSL9_TRACEID_MAX 0xAU
 420 #define CXL_PSL9_TRACESTATE_FIN 0x3U
 421
 422 enum cxl_context_status {
 423         CLOSED,
 424         OPENED,
 425         STARTED
 426 };
 427
 428 enum prefault_modes {
 429         CXL_PREFAULT_NONE,
 430         CXL_PREFAULT_WED,
 431         CXL_PREFAULT_ALL,
 432 };
 433
 434 enum cxl_attrs {
 435         CXL_ADAPTER_ATTRS,
 436         CXL_AFU_MASTER_ATTRS,
 437         CXL_AFU_ATTRS,
 438 };
 439
 440 struct cxl_sste {
 441         __be64 esid_data;
 442         __be64 vsid_data;
 443 };
 444
 445 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
 446 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
 447
 448 struct cxl_afu_native {
 449         void __iomem *p1n_mmio;
 450         void __iomem *afu_desc_mmio;
 451         irq_hw_number_t psl_hwirq;
 452         unsigned int psl_virq;
 453         struct mutex spa_mutex;
 454         /*
 455          * Only the first part of the SPA is used for the process element
 456          * linked list. The only other part that software needs to worry about
 457          * is sw_command_status, which we store a separate pointer to.
 458          * Everything else in the SPA is only used by hardware
 459          */
 460         struct cxl_process_element *spa;
 461         __be64 *sw_command_status;
 462         unsigned int spa_size;
 463         int spa_order;
 464         int spa_max_procs;
 465         u64 pp_offset;
 466 };
 467
 468 struct cxl_afu_guest {
 469         struct cxl_afu *parent;
 470         u64 handle;
 471         phys_addr_t p2n_phys;
 472         u64 p2n_size;
 473         int max_ints;
 474         bool handle_err;
 475         struct delayed_work work_err;
 476         int previous_state;
 477 };
 478
 479 struct cxl_afu {
 480         struct cxl_afu_native *native;
 481         struct cxl_afu_guest *guest;
 482         irq_hw_number_t serr_hwirq;
 483         unsigned int serr_virq;
 484         char *psl_irq_name;
 485         char *err_irq_name;
 486         void __iomem *p2n_mmio;
 487         phys_addr_t psn_phys;
 488         u64 pp_size;
 489
 490         struct cxl *adapter;
 491         struct device dev;
 492         struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
 493         struct device *chardev_s, *chardev_m, *chardev_d;
 494         struct idr contexts_idr;
 495         struct dentry *debugfs;
 496         struct mutex contexts_lock;
 497         spinlock_t afu_cntl_lock;
 498
 499         /* -1: AFU deconfigured/locked, >= 0: number of readers */
 500         atomic_t configured_state;
 501
 502         /* AFU error buffer fields and bin attribute for sysfs */
 503         u64 eb_len, eb_offset;
 504         struct bin_attribute attr_eb;
 505
 506         /* pointer to the vphb */
 507         struct pci_controller *phb;
 508
 509         int pp_irqs;
 510         int irqs_max;
 511         int num_procs;
 512         int max_procs_virtualised;
 513         int slice;
 514         int modes_supported;
 515         int current_mode;
 516         int crs_num;
 517         u64 crs_len;
 518         u64 crs_offset;
 519         struct list_head crs;
 520         enum prefault_modes prefault_mode;
 521         bool psa;
 522         bool pp_psa;
 523         bool enabled;
 524 };
 525
 526
 527 struct cxl_irq_name {
 528         struct list_head list;
 529         char *name;
 530 };
 531
 532 struct irq_avail {
 533         irq_hw_number_t offset;
 534         irq_hw_number_t range;
 535         unsigned long   *bitmap;
 536 };
 537
 538 /*
 539  * This is a cxl context.  If the PSL is in dedicated mode, there will be one
 540  * of these per AFU.  If in AFU directed there can be lots of these.
 541  */
 542 struct cxl_context {
 543         struct cxl_afu *afu;
 544
 545         /* Problem state MMIO */
 546         phys_addr_t psn_phys;
 547         u64 psn_size;
 548
 549         /* Used to unmap any mmaps when force detaching */
 550         struct address_space *mapping;
 551         struct mutex mapping_lock;
 552         struct page *ff_page;
 553         bool mmio_err_ff;
 554         bool kernelapi;
 555
 556         spinlock_t sste_lock; /* Protects segment table entries */
 557         struct cxl_sste *sstp;
 558         u64 sstp0, sstp1;
 559         unsigned int sst_size, sst_lru;
 560
 561         wait_queue_head_t wq;
 562         /* use mm context associated with this pid for ds faults */
 563         struct pid *pid;
 564         spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
 565         /* Only used in PR mode */
 566         u64 process_token;
 567
 568         /* driver private data */
 569         void *priv;
 570
 571         unsigned long *irq_bitmap; /* Accessed from IRQ context */
 572         struct cxl_irq_ranges irqs;
 573         struct list_head irq_names;
 574         u64 fault_addr;
 575         u64 fault_dsisr;
 576         u64 afu_err;
 577
 578         /*
 579          * This status and it's lock pretects start and detach context
 580          * from racing.  It also prevents detach from racing with
 581          * itself
 582          */
 583         enum cxl_context_status status;
 584         struct mutex status_mutex;
 585
 586
 587         /* XXX: Is it possible to need multiple work items at once? */
 588         struct work_struct fault_work;
 589         u64 dsisr;
 590         u64 dar;
 591
 592         struct cxl_process_element *elem;
 593
 594         /*
 595          * pe is the process element handle, assigned by this driver when the
 596          * context is initialized.
 597          *
 598          * external_pe is the PE shown outside of cxl.
 599          * On bare-metal, pe=external_pe, because we decide what the handle is.
 600          * In a guest, we only find out about the pe used by pHyp when the
 601          * context is attached, and that's the value we want to report outside
 602          * of cxl.
 603          */
 604         int pe;
 605         int external_pe;
 606
 607         u32 irq_count;
 608         bool pe_inserted;
 609         bool master;
 610         bool kernel;
 611         bool pending_irq;
 612         bool pending_fault;
 613         bool pending_afu_err;
 614
 615         /* Used by AFU drivers for driver specific event delivery */
 616         struct cxl_afu_driver_ops *afu_driver_ops;
 617         atomic_t afu_driver_events;
 618
 619         struct rcu_head rcu;
 620
 621         struct mm_struct *mm;
 622
 623         u16 tidr;
 624         bool assign_tidr;
 625 };
 626
 627 struct cxl_irq_info;
 628
 629 struct cxl_service_layer_ops {
 630         int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
 631         int (*invalidate_all)(struct cxl *adapter);
 632         int (*afu_regs_init)(struct cxl_afu *afu);
 633         int (*sanitise_afu_regs)(struct cxl_afu *afu);
 634         int (*register_serr_irq)(struct cxl_afu *afu);
 635         void (*release_serr_irq)(struct cxl_afu *afu);
 636         irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
 637         irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
 638         int (*activate_dedicated_process)(struct cxl_afu *afu);
 639         int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
 640         int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
 641         void (*update_dedicated_ivtes)(struct cxl_context *ctx);
 642         void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
 643         void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
 644         void (*psl_irq_dump_registers)(struct cxl_context *ctx);
 645         void (*err_irq_dump_registers)(struct cxl *adapter);
 646         void (*debugfs_stop_trace)(struct cxl *adapter);
 647         void (*write_timebase_ctrl)(struct cxl *adapter);
 648         u64 (*timebase_read)(struct cxl *adapter);
 649         int capi_mode;
 650         bool needs_reset_before_disable;
 651 };
 652
 653 struct cxl_native {
 654         u64 afu_desc_off;
 655         u64 afu_desc_size;
 656         void __iomem *p1_mmio;
 657         void __iomem *p2_mmio;
 658         irq_hw_number_t err_hwirq;
 659         unsigned int err_virq;
 660         u64 ps_off;
 661         bool no_data_cache; /* set if no data cache on the card */
 662         const struct cxl_service_layer_ops *sl_ops;
 663 };
 664
 665 struct cxl_guest {
 666         struct platform_device *pdev;
 667         int irq_nranges;
 668         struct cdev cdev;
 669         irq_hw_number_t irq_base_offset;
 670         struct irq_avail *irq_avail;
 671         spinlock_t irq_alloc_lock;
 672         u64 handle;
 673         char *status;
 674         u16 vendor;
 675         u16 device;
 676         u16 subsystem_vendor;
 677         u16 subsystem;
 678 };
 679
 680 struct cxl {
 681         struct cxl_native *native;
 682         struct cxl_guest *guest;
 683         spinlock_t afu_list_lock;
 684         struct cxl_afu *afu[CXL_MAX_SLICES];
 685         struct device dev;
 686         struct dentry *trace;
 687         struct dentry *psl_err_chk;
 688         struct dentry *debugfs;
 689         char *irq_name;
 690         struct bin_attribute cxl_attr;
 691         int adapter_num;
 692         int user_irqs;
 693         u64 ps_size;
 694         u16 psl_rev;
 695         u16 base_image;
 696         u8 vsec_status;
 697         u8 caia_major;
 698         u8 caia_minor;
 699         u8 slices;
 700         bool user_image_loaded;
 701         bool perst_loads_image;
 702         bool perst_select_user;
 703         bool perst_same_image;
 704         bool psl_timebase_synced;
 705         bool tunneled_ops_supported;
 706
 707         /*
 708          * number of contexts mapped on to this card. Possible values are:
 709          * >0: Number of contexts mapped and new one can be mapped.
 710          *  0: No active contexts and new ones can be mapped.
 711          * -1: No contexts mapped and new ones cannot be mapped.
 712          */
 713         atomic_t contexts_num;
 714 };
 715
 716 int cxl_pci_alloc_one_irq(struct cxl *adapter);
 717 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
 718 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
 719 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
 720 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
 721 int cxl_update_image_control(struct cxl *adapter);
 722 int cxl_pci_reset(struct cxl *adapter);
 723 void cxl_pci_release_afu(struct device *dev);
 724 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
 725
 726 /* common == phyp + powernv - CAIA 1&2 */
 727 struct cxl_process_element_common {
 728         __be32 tid;
 729         __be32 pid;
 730         __be64 csrp;
 731         union {
 732                 struct {
 733                         __be64 aurp0;
 734                         __be64 aurp1;
 735                         __be64 sstp0;
 736                         __be64 sstp1;
 737                 } psl8;  /* CAIA 1 */
 738                 struct {
 739                         u8     reserved2[8];
 740                         u8     reserved3[8];
 741                         u8     reserved4[8];
 742                         u8     reserved5[8];
 743                 } psl9;  /* CAIA 2 */
 744         } u;
 745         __be64 amr;
 746         u8     reserved6[4];
 747         __be64 wed;
 748 } __packed;
 749
 750 /* just powernv - CAIA 1&2 */
 751 struct cxl_process_element {
 752         __be64 sr;
 753         __be64 SPOffset;
 754         union {
 755                 __be64 sdr;          /* CAIA 1 */
 756                 u8     reserved1[8]; /* CAIA 2 */
 757         } u;
 758         __be64 haurp;
 759         __be32 ctxtime;
 760         __be16 ivte_offsets[4];
 761         __be16 ivte_ranges[4];
 762         __be32 lpid;
 763         struct cxl_process_element_common common;
 764         __be32 software_state;
 765 } __packed;
 766
 767 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
 768 {
 769         struct pci_dev *pdev;
 770
 771         if (cpu_has_feature(CPU_FTR_HVMODE)) {
 772                 pdev = to_pci_dev(cxl->dev.parent);
 773                 return !pci_channel_offline(pdev);
 774         }
 775         return true;
 776 }
 777
 778 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
 779 {
 780         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 781         return cxl->native->p1_mmio + cxl_reg_off(reg);
 782 }
 783
 784 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
 785 {
 786         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 787                 out_be64(_cxl_p1_addr(cxl, reg), val);
 788 }
 789
 790 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
 791 {
 792         if (likely(cxl_adapter_link_ok(cxl, NULL)))
 793                 return in_be64(_cxl_p1_addr(cxl, reg));
 794         else
 795                 return ~0ULL;
 796 }
 797
 798 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 799 {
 800         WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
 801         return afu->native->p1n_mmio + cxl_reg_off(reg);
 802 }
 803
 804 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
 805 {
 806         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 807                 out_be64(_cxl_p1n_addr(afu, reg), val);
 808 }
 809
 810 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
 811 {
 812         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 813                 return in_be64(_cxl_p1n_addr(afu, reg));
 814         else
 815                 return ~0ULL;
 816 }
 817
 818 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 819 {
 820         return afu->p2n_mmio + cxl_reg_off(reg);
 821 }
 822
 823 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
 824 {
 825         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 826                 out_be64(_cxl_p2n_addr(afu, reg), val);
 827 }
 828
 829 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
 830 {
 831         if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
 832                 return in_be64(_cxl_p2n_addr(afu, reg));
 833         else
 834                 return ~0ULL;
 835 }
 836
 837 static inline bool cxl_is_power8(void)
 838 {
 839         if ((pvr_version_is(PVR_POWER8E)) ||
 840             (pvr_version_is(PVR_POWER8NVL)) ||
 841             (pvr_version_is(PVR_POWER8)))
 842                 return true;
 843         return false;
 844 }
 845
 846 static inline bool cxl_is_power9(void)
 847 {
 848         if (pvr_version_is(PVR_POWER9))
 849                 return true;
 850         return false;
 851 }
 852
 853 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
 854                                 loff_t off, size_t count);
 855
 856
 857 struct cxl_calls {
 858         void (*cxl_slbia)(struct mm_struct *mm);
 859         struct module *owner;
 860 };
 861 int register_cxl_calls(struct cxl_calls *calls);
 862 void unregister_cxl_calls(struct cxl_calls *calls);
 863 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
 864
 865 void cxl_remove_adapter_nr(struct cxl *adapter);
 866
 867 void cxl_release_spa(struct cxl_afu *afu);
 868
 869 dev_t cxl_get_dev(void);
 870 int cxl_file_init(void);
 871 void cxl_file_exit(void);
 872 int cxl_register_adapter(struct cxl *adapter);
 873 int cxl_register_afu(struct cxl_afu *afu);
 874 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
 875 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
 876 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
 877 void cxl_chardev_afu_remove(struct cxl_afu *afu);
 878
 879 void cxl_context_detach_all(struct cxl_afu *afu);
 880 void cxl_context_free(struct cxl_context *ctx);
 881 void cxl_context_detach(struct cxl_context *ctx);
 882
 883 int cxl_sysfs_adapter_add(struct cxl *adapter);
 884 void cxl_sysfs_adapter_remove(struct cxl *adapter);
 885 int cxl_sysfs_afu_add(struct cxl_afu *afu);
 886 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
 887 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
 888 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
 889
 890 struct cxl *cxl_alloc_adapter(void);
 891 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
 892 int cxl_afu_select_best_mode(struct cxl_afu *afu);
 893
 894 int cxl_native_register_psl_irq(struct cxl_afu *afu);
 895 void cxl_native_release_psl_irq(struct cxl_afu *afu);
 896 int cxl_native_register_psl_err_irq(struct cxl *adapter);
 897 void cxl_native_release_psl_err_irq(struct cxl *adapter);
 898 int cxl_native_register_serr_irq(struct cxl_afu *afu);
 899 void cxl_native_release_serr_irq(struct cxl_afu *afu);
 900 int afu_register_irqs(struct cxl_context *ctx, u32 count);
 901 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
 902 void afu_irq_name_free(struct cxl_context *ctx);
 903
 904 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 905 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 906 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
 907 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
 908 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
 909 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
 910 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
 911 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
 912
 913 #ifdef CONFIG_DEBUG_FS
 914
 915 int cxl_debugfs_init(void);
 916 void cxl_debugfs_exit(void);
 917 int cxl_debugfs_adapter_add(struct cxl *adapter);
 918 void cxl_debugfs_adapter_remove(struct cxl *adapter);
 919 int cxl_debugfs_afu_add(struct cxl_afu *afu);
 920 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
 921 void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
 922 void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
 923 void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
 924 void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
 925
 926 #else /* CONFIG_DEBUG_FS */
 927
 928 static inline int __init cxl_debugfs_init(void)
 929 {
 930         return 0;
 931 }
 932
 933 static inline void cxl_debugfs_exit(void)
 934 {
 935 }
 936
 937 static inline int cxl_debugfs_adapter_add(struct cxl *adapter)
 938 {
 939         return 0;
 940 }
 941
 942 static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
 943 {
 944 }
 945
 946 static inline int cxl_debugfs_afu_add(struct cxl_afu *afu)
 947 {
 948         return 0;
 949 }
 950
 951 static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
 952 {
 953 }
 954
 955 static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
 956                                                     struct dentry *dir)
 957 {
 958 }
 959
 960 static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
 961                                                     struct dentry *dir)
 962 {
 963 }
 964
 965 static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
 966 {
 967 }
 968
 969 static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
 970 {
 971 }
 972
 973 #endif /* CONFIG_DEBUG_FS */
 974
 975 void cxl_handle_fault(struct work_struct *work);
 976 void cxl_prefault(struct cxl_context *ctx, u64 wed);
 977 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
 978
 979 struct cxl *get_cxl_adapter(int num);
 980 int cxl_alloc_sst(struct cxl_context *ctx);
 981 void cxl_dump_debug_buffer(void *addr, size_t size);
 982
 983 void init_cxl_native(void);
 984
 985 struct cxl_context *cxl_context_alloc(void);
 986 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
 987 void cxl_context_set_mapping(struct cxl_context *ctx,
 988                         struct address_space *mapping);
 989 void cxl_context_free(struct cxl_context *ctx);
 990 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
 991 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
 992                          irq_handler_t handler, void *cookie, const char *name);
 993 void cxl_unmap_irq(unsigned int virq, void *cookie);
 994 int __detach_context(struct cxl_context *ctx);
 995
 996 /*
 997  * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
 998  * in PAPR.
 999  * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1000  * On a guest environment, PSL_PID_An is located on the upper 32 bits and
1001  * PSL_TID_An register in the lower 32 bits.
1002  */
1003 struct cxl_irq_info {
1004         u64 dsisr;
1005         u64 dar;
1006         u64 dsr;
1007         u64 reserved;
1008         u64 afu_err;
1009         u64 errstat;
1010         u64 proc_handle;
1011         u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1012 };
1013
1014 void cxl_assign_psn_space(struct cxl_context *ctx);
1015 int cxl_invalidate_all_psl9(struct cxl *adapter);
1016 int cxl_invalidate_all_psl8(struct cxl *adapter);
1017 irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1018 irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1019 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1020 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1021                         void *cookie, irq_hw_number_t *dest_hwirq,
1022                         unsigned int *dest_virq, const char *name);
1023
1024 int cxl_check_error(struct cxl_afu *afu);
1025 int cxl_afu_slbia(struct cxl_afu *afu);
1026 int cxl_data_cache_flush(struct cxl *adapter);
1027 int cxl_afu_disable(struct cxl_afu *afu);
1028 int cxl_psl_purge(struct cxl_afu *afu);
1029 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1030                           u32 *phb_index, u64 *capp_unit_id);
1031 int cxl_slot_is_switched(struct pci_dev *dev);
1032 int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
1033 u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1034
1035 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1036 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1037 void cxl_native_err_irq_dump_regs_psl8(struct cxl *adapter);
1038 void cxl_native_err_irq_dump_regs_psl9(struct cxl *adapter);
1039 int cxl_pci_vphb_add(struct cxl_afu *afu);
1040 void cxl_pci_vphb_remove(struct cxl_afu *afu);
1041 void cxl_release_mapping(struct cxl_context *ctx);
1042
1043 extern struct pci_driver cxl_pci_driver;
1044 extern struct platform_driver cxl_of_driver;
1045 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1046
1047 int afu_open(struct inode *inode, struct file *file);
1048 int afu_release(struct inode *inode, struct file *file);
1049 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1050 int afu_mmap(struct file *file, struct vm_area_struct *vm);
1051 __poll_t afu_poll(struct file *file, struct poll_table_struct *poll);
1052 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1053 extern const struct file_operations afu_fops;
1054
1055 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1056 void cxl_guest_remove_adapter(struct cxl *adapter);
1057 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1058 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1059 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1060 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1061 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1062 void cxl_guest_remove_afu(struct cxl_afu *afu);
1063 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1064 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1065 int cxl_guest_add_chardev(struct cxl *adapter);
1066 void cxl_guest_remove_chardev(struct cxl *adapter);
1067 void cxl_guest_reload_module(struct cxl *adapter);
1068 int cxl_of_probe(struct platform_device *pdev);
1069
1070 struct cxl_backend_ops {
1071         struct module *module;
1072         int (*adapter_reset)(struct cxl *adapter);
1073         int (*alloc_one_irq)(struct cxl *adapter);
1074         void (*release_one_irq)(struct cxl *adapter, int hwirq);
1075         int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1076                                 struct cxl *adapter, unsigned int num);
1077         void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1078                                 struct cxl *adapter);
1079         int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1080                         unsigned int virq);
1081         irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1082                                         u64 dsisr, u64 errstat);
1083         irqreturn_t (*psl_interrupt)(int irq, void *data);
1084         int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1085         void (*irq_wait)(struct cxl_context *ctx);
1086         int (*attach_process)(struct cxl_context *ctx, bool kernel,
1087                         u64 wed, u64 amr);
1088         int (*detach_process)(struct cxl_context *ctx);
1089         void (*update_ivtes)(struct cxl_context *ctx);
1090         bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1091         bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1092         void (*release_afu)(struct device *dev);
1093         ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1094                                 loff_t off, size_t count);
1095         int (*afu_check_and_enable)(struct cxl_afu *afu);
1096         int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1097         int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1098         int (*afu_reset)(struct cxl_afu *afu);
1099         int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1100         int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1101         int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1102         int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1103         int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1104         int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1105         int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1106         ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1107 };
1108 extern const struct cxl_backend_ops cxl_native_ops;
1109 extern const struct cxl_backend_ops cxl_guest_ops;
1110 extern const struct cxl_backend_ops *cxl_ops;
1111
1112 /* check if the given pci_dev is on the the cxl vphb bus */
1113 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1114
1115 /* decode AFU error bits in the PSL register PSL_SERR_An */
1116 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1117
1118 /*
1119  * Increments the number of attached contexts on an adapter.
1120  * In case an adapter_context_lock is taken the return -EBUSY.
1121  */
1122 int cxl_adapter_context_get(struct cxl *adapter);
1123
1124 /* Decrements the number of attached contexts on an adapter */
1125 void cxl_adapter_context_put(struct cxl *adapter);
1126
1127 /* If no active contexts then prevents contexts from being attached */
1128 int cxl_adapter_context_lock(struct cxl *adapter);
1129
1130 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1131 void cxl_adapter_context_unlock(struct cxl *adapter);
1132
1133 /* Increases the reference count to "struct mm_struct" */
1134 void cxl_context_mm_count_get(struct cxl_context *ctx);
1135
1136 /* Decrements the reference count to "struct mm_struct" */
1137 void cxl_context_mm_count_put(struct cxl_context *ctx);
1138
1139 #endif