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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / mmc / host / mmci.c
blob82bab35fff41f1e7ead0e78852d842a293c684f0
1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/of.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/dmaengine.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/amba/mmci.h>
36 #include <linux/pm_runtime.h>
37 #include <linux/types.h>
38 #include <linux/pinctrl/consumer.h>
39 #include <linux/reset.h>
40
41 #include <asm/div64.h>
42 #include <asm/io.h>
43
44 #include "mmci.h"
45 #include "mmci_qcom_dml.h"
46
47 #define DRIVER_NAME "mmci-pl18x"
48
49 #ifdef CONFIG_DMA_ENGINE
50 void mmci_variant_init(struct mmci_host *host);
51 #else
52 static inline void mmci_variant_init(struct mmci_host *host) {}
53 #endif
54
55 #ifdef CONFIG_MMC_STM32_SDMMC
56 void sdmmc_variant_init(struct mmci_host *host);
57 #else
58 static inline void sdmmc_variant_init(struct mmci_host *host) {}
59 #endif
60
61 static unsigned int fmax = 515633;
62
63 static struct variant_data variant_arm = {
64 .fifosize = 16 * 4,
65 .fifohalfsize = 8 * 4,
66 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
67 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
68 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
69 .cmdreg_srsp = MCI_CPSM_RESPONSE,
70 .datalength_bits = 16,
71 .datactrl_blocksz = 11,
72 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
73 .pwrreg_powerup = MCI_PWR_UP,
74 .f_max = 100000000,
75 .reversed_irq_handling = true,
76 .mmcimask1 = true,
77 .irq_pio_mask = MCI_IRQ_PIO_MASK,
78 .start_err = MCI_STARTBITERR,
79 .opendrain = MCI_ROD,
80 .init = mmci_variant_init,
81 };
82
83 static struct variant_data variant_arm_extended_fifo = {
84 .fifosize = 128 * 4,
85 .fifohalfsize = 64 * 4,
86 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
87 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
88 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
89 .cmdreg_srsp = MCI_CPSM_RESPONSE,
90 .datalength_bits = 16,
91 .datactrl_blocksz = 11,
92 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
93 .pwrreg_powerup = MCI_PWR_UP,
94 .f_max = 100000000,
95 .mmcimask1 = true,
96 .irq_pio_mask = MCI_IRQ_PIO_MASK,
97 .start_err = MCI_STARTBITERR,
98 .opendrain = MCI_ROD,
99 .init = mmci_variant_init,
100 };
101
102 static struct variant_data variant_arm_extended_fifo_hwfc = {
103 .fifosize = 128 * 4,
104 .fifohalfsize = 64 * 4,
105 .clkreg_enable = MCI_ARM_HWFCEN,
106 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
107 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
108 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
109 .cmdreg_srsp = MCI_CPSM_RESPONSE,
110 .datalength_bits = 16,
111 .datactrl_blocksz = 11,
112 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
113 .pwrreg_powerup = MCI_PWR_UP,
114 .f_max = 100000000,
115 .mmcimask1 = true,
116 .irq_pio_mask = MCI_IRQ_PIO_MASK,
117 .start_err = MCI_STARTBITERR,
118 .opendrain = MCI_ROD,
119 .init = mmci_variant_init,
120 };
121
122 static struct variant_data variant_u300 = {
123 .fifosize = 16 * 4,
124 .fifohalfsize = 8 * 4,
125 .clkreg_enable = MCI_ST_U300_HWFCEN,
126 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
127 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
128 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
129 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
130 .cmdreg_srsp = MCI_CPSM_RESPONSE,
131 .datalength_bits = 16,
132 .datactrl_blocksz = 11,
133 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
134 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
135 .st_sdio = true,
136 .pwrreg_powerup = MCI_PWR_ON,
137 .f_max = 100000000,
138 .signal_direction = true,
139 .pwrreg_clkgate = true,
140 .pwrreg_nopower = true,
141 .mmcimask1 = true,
142 .irq_pio_mask = MCI_IRQ_PIO_MASK,
143 .start_err = MCI_STARTBITERR,
144 .opendrain = MCI_OD,
145 .init = mmci_variant_init,
146 };
147
148 static struct variant_data variant_nomadik = {
149 .fifosize = 16 * 4,
150 .fifohalfsize = 8 * 4,
151 .clkreg = MCI_CLK_ENABLE,
152 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
153 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
154 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
155 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
156 .cmdreg_srsp = MCI_CPSM_RESPONSE,
157 .datalength_bits = 24,
158 .datactrl_blocksz = 11,
159 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
160 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
161 .st_sdio = true,
162 .st_clkdiv = true,
163 .pwrreg_powerup = MCI_PWR_ON,
164 .f_max = 100000000,
165 .signal_direction = true,
166 .pwrreg_clkgate = true,
167 .pwrreg_nopower = true,
168 .mmcimask1 = true,
169 .irq_pio_mask = MCI_IRQ_PIO_MASK,
170 .start_err = MCI_STARTBITERR,
171 .opendrain = MCI_OD,
172 .init = mmci_variant_init,
173 };
174
175 static struct variant_data variant_ux500 = {
176 .fifosize = 30 * 4,
177 .fifohalfsize = 8 * 4,
178 .clkreg = MCI_CLK_ENABLE,
179 .clkreg_enable = MCI_ST_UX500_HWFCEN,
180 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
181 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
182 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
183 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
184 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
185 .cmdreg_srsp = MCI_CPSM_RESPONSE,
186 .datalength_bits = 24,
187 .datactrl_blocksz = 11,
188 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
189 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
190 .st_sdio = true,
191 .st_clkdiv = true,
192 .pwrreg_powerup = MCI_PWR_ON,
193 .f_max = 100000000,
194 .signal_direction = true,
195 .pwrreg_clkgate = true,
196 .busy_detect = true,
197 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
198 .busy_detect_flag = MCI_ST_CARDBUSY,
199 .busy_detect_mask = MCI_ST_BUSYENDMASK,
200 .pwrreg_nopower = true,
201 .mmcimask1 = true,
202 .irq_pio_mask = MCI_IRQ_PIO_MASK,
203 .start_err = MCI_STARTBITERR,
204 .opendrain = MCI_OD,
205 .init = mmci_variant_init,
206 };
207
208 static struct variant_data variant_ux500v2 = {
209 .fifosize = 30 * 4,
210 .fifohalfsize = 8 * 4,
211 .clkreg = MCI_CLK_ENABLE,
212 .clkreg_enable = MCI_ST_UX500_HWFCEN,
213 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
214 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
215 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
216 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
217 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
218 .cmdreg_srsp = MCI_CPSM_RESPONSE,
219 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
220 .datalength_bits = 24,
221 .datactrl_blocksz = 11,
222 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
223 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
224 .st_sdio = true,
225 .st_clkdiv = true,
226 .blksz_datactrl16 = true,
227 .pwrreg_powerup = MCI_PWR_ON,
228 .f_max = 100000000,
229 .signal_direction = true,
230 .pwrreg_clkgate = true,
231 .busy_detect = true,
232 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
233 .busy_detect_flag = MCI_ST_CARDBUSY,
234 .busy_detect_mask = MCI_ST_BUSYENDMASK,
235 .pwrreg_nopower = true,
236 .mmcimask1 = true,
237 .irq_pio_mask = MCI_IRQ_PIO_MASK,
238 .start_err = MCI_STARTBITERR,
239 .opendrain = MCI_OD,
240 .init = mmci_variant_init,
241 };
242
243 static struct variant_data variant_stm32 = {
244 .fifosize = 32 * 4,
245 .fifohalfsize = 8 * 4,
246 .clkreg = MCI_CLK_ENABLE,
247 .clkreg_enable = MCI_ST_UX500_HWFCEN,
248 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
249 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
250 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
251 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
252 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
253 .cmdreg_srsp = MCI_CPSM_RESPONSE,
254 .irq_pio_mask = MCI_IRQ_PIO_MASK,
255 .datalength_bits = 24,
256 .datactrl_blocksz = 11,
257 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
258 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
259 .st_sdio = true,
260 .st_clkdiv = true,
261 .pwrreg_powerup = MCI_PWR_ON,
262 .f_max = 48000000,
263 .pwrreg_clkgate = true,
264 .pwrreg_nopower = true,
265 .init = mmci_variant_init,
266 };
267
268 static struct variant_data variant_stm32_sdmmc = {
269 .fifosize = 16 * 4,
270 .fifohalfsize = 8 * 4,
271 .f_max = 208000000,
272 .stm32_clkdiv = true,
273 .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE,
274 .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC,
275 .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC,
276 .cmdreg_srsp = MCI_CPSM_STM32_SRSP,
277 .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS,
278 .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK,
279 .datactrl_first = true,
280 .datacnt_useless = true,
281 .datalength_bits = 25,
282 .datactrl_blocksz = 14,
283 .stm32_idmabsize_mask = GENMASK(12, 5),
284 .init = sdmmc_variant_init,
285 };
286
287 static struct variant_data variant_qcom = {
288 .fifosize = 16 * 4,
289 .fifohalfsize = 8 * 4,
290 .clkreg = MCI_CLK_ENABLE,
291 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
292 MCI_QCOM_CLK_SELECT_IN_FBCLK,
293 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
294 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
295 .cmdreg_cpsm_enable = MCI_CPSM_ENABLE,
296 .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP,
297 .cmdreg_srsp_crc = MCI_CPSM_RESPONSE,
298 .cmdreg_srsp = MCI_CPSM_RESPONSE,
299 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
300 .blksz_datactrl4 = true,
301 .datalength_bits = 24,
302 .datactrl_blocksz = 11,
303 .datactrl_dpsm_enable = MCI_DPSM_ENABLE,
304 .pwrreg_powerup = MCI_PWR_UP,
305 .f_max = 208000000,
306 .explicit_mclk_control = true,
307 .qcom_fifo = true,
308 .qcom_dml = true,
309 .mmcimask1 = true,
310 .irq_pio_mask = MCI_IRQ_PIO_MASK,
311 .start_err = MCI_STARTBITERR,
312 .opendrain = MCI_ROD,
313 .init = qcom_variant_init,
314 };
315
316 /* Busy detection for the ST Micro variant */
317 static int mmci_card_busy(struct mmc_host *mmc)
318 {
319 struct mmci_host *host = mmc_priv(mmc);
320 unsigned long flags;
321 int busy = 0;
322
323 spin_lock_irqsave(&host->lock, flags);
324 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
325 busy = 1;
326 spin_unlock_irqrestore(&host->lock, flags);
327
328 return busy;
329 }
330
331 static void mmci_reg_delay(struct mmci_host *host)
332 {
333 /*
334 * According to the spec, at least three feedback clock cycles
335 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
336 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
337 * Worst delay time during card init is at 100 kHz => 30 us.
338 * Worst delay time when up and running is at 25 MHz => 120 ns.
339 */
340 if (host->cclk < 25000000)
341 udelay(30);
342 else
343 ndelay(120);
344 }
345
346 /*
347 * This must be called with host->lock held
348 */
349 void mmci_write_clkreg(struct mmci_host *host, u32 clk)
350 {
351 if (host->clk_reg != clk) {
352 host->clk_reg = clk;
353 writel(clk, host->base + MMCICLOCK);
354 }
355 }
356
357 /*
358 * This must be called with host->lock held
359 */
360 void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
361 {
362 if (host->pwr_reg != pwr) {
363 host->pwr_reg = pwr;
364 writel(pwr, host->base + MMCIPOWER);
365 }
366 }
367
368 /*
369 * This must be called with host->lock held
370 */
371 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
372 {
373 /* Keep busy mode in DPSM if enabled */
374 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
375
376 if (host->datactrl_reg != datactrl) {
377 host->datactrl_reg = datactrl;
378 writel(datactrl, host->base + MMCIDATACTRL);
379 }
380 }
381
382 /*
383 * This must be called with host->lock held
384 */
385 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
386 {
387 struct variant_data *variant = host->variant;
388 u32 clk = variant->clkreg;
389
390 /* Make sure cclk reflects the current calculated clock */
391 host->cclk = 0;
392
393 if (desired) {
394 if (variant->explicit_mclk_control) {
395 host->cclk = host->mclk;
396 } else if (desired >= host->mclk) {
397 clk = MCI_CLK_BYPASS;
398 if (variant->st_clkdiv)
399 clk |= MCI_ST_UX500_NEG_EDGE;
400 host->cclk = host->mclk;
401 } else if (variant->st_clkdiv) {
402 /*
403 * DB8500 TRM says f = mclk / (clkdiv + 2)
404 * => clkdiv = (mclk / f) - 2
405 * Round the divider up so we don't exceed the max
406 * frequency
407 */
408 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
409 if (clk >= 256)
410 clk = 255;
411 host->cclk = host->mclk / (clk + 2);
412 } else {
413 /*
414 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
415 * => clkdiv = mclk / (2 * f) - 1
416 */
417 clk = host->mclk / (2 * desired) - 1;
418 if (clk >= 256)
419 clk = 255;
420 host->cclk = host->mclk / (2 * (clk + 1));
421 }
422
423 clk |= variant->clkreg_enable;
424 clk |= MCI_CLK_ENABLE;
425 /* This hasn't proven to be worthwhile */
426 /* clk |= MCI_CLK_PWRSAVE; */
427 }
428
429 /* Set actual clock for debug */
430 host->mmc->actual_clock = host->cclk;
431
432 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
433 clk |= MCI_4BIT_BUS;
434 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
435 clk |= variant->clkreg_8bit_bus_enable;
436
437 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
438 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
439 clk |= variant->clkreg_neg_edge_enable;
440
441 mmci_write_clkreg(host, clk);
442 }
443
444 void mmci_dma_release(struct mmci_host *host)
445 {
446 if (host->ops && host->ops->dma_release)
447 host->ops->dma_release(host);
448
449 host->use_dma = false;
450 }
451
452 void mmci_dma_setup(struct mmci_host *host)
453 {
454 if (!host->ops || !host->ops->dma_setup)
455 return;
456
457 if (host->ops->dma_setup(host))
458 return;
459
460 /* initialize pre request cookie */
461 host->next_cookie = 1;
462
463 host->use_dma = true;
464 }
465
466 /*
467 * Validate mmc prerequisites
468 */
469 static int mmci_validate_data(struct mmci_host *host,
470 struct mmc_data *data)
471 {
472 if (!data)
473 return 0;
474
475 if (!is_power_of_2(data->blksz)) {
476 dev_err(mmc_dev(host->mmc),
477 "unsupported block size (%d bytes)\n", data->blksz);
478 return -EINVAL;
479 }
480
481 if (host->ops && host->ops->validate_data)
482 return host->ops->validate_data(host, data);
483
484 return 0;
485 }
486
487 int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next)
488 {
489 int err;
490
491 if (!host->ops || !host->ops->prep_data)
492 return 0;
493
494 err = host->ops->prep_data(host, data, next);
495
496 if (next && !err)
497 data->host_cookie = ++host->next_cookie < 0 ?
498 1 : host->next_cookie;
499
500 return err;
501 }
502
503 void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data,
504 int err)
505 {
506 if (host->ops && host->ops->unprep_data)
507 host->ops->unprep_data(host, data, err);
508
509 data->host_cookie = 0;
510 }
511
512 void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
513 {
514 WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie);
515
516 if (host->ops && host->ops->get_next_data)
517 host->ops->get_next_data(host, data);
518 }
519
520 int mmci_dma_start(struct mmci_host *host, unsigned int datactrl)
521 {
522 struct mmc_data *data = host->data;
523 int ret;
524
525 if (!host->use_dma)
526 return -EINVAL;
527
528 ret = mmci_prep_data(host, data, false);
529 if (ret)
530 return ret;
531
532 if (!host->ops || !host->ops->dma_start)
533 return -EINVAL;
534
535 /* Okay, go for it. */
536 dev_vdbg(mmc_dev(host->mmc),
537 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
538 data->sg_len, data->blksz, data->blocks, data->flags);
539
540 host->ops->dma_start(host, &datactrl);
541
542 /* Trigger the DMA transfer */
543 mmci_write_datactrlreg(host, datactrl);
544
545 /*
546 * Let the MMCI say when the data is ended and it's time
547 * to fire next DMA request. When that happens, MMCI will
548 * call mmci_data_end()
549 */
550 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
551 host->base + MMCIMASK0);
552 return 0;
553 }
554
555 void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
556 {
557 if (!host->use_dma)
558 return;
559
560 if (host->ops && host->ops->dma_finalize)
561 host->ops->dma_finalize(host, data);
562 }
563
564 void mmci_dma_error(struct mmci_host *host)
565 {
566 if (!host->use_dma)
567 return;
568
569 if (host->ops && host->ops->dma_error)
570 host->ops->dma_error(host);
571 }
572
573 static void
574 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
575 {
576 writel(0, host->base + MMCICOMMAND);
577
578 BUG_ON(host->data);
579
580 host->mrq = NULL;
581 host->cmd = NULL;
582
583 mmc_request_done(host->mmc, mrq);
584 }
585
586 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
587 {
588 void __iomem *base = host->base;
589 struct variant_data *variant = host->variant;
590
591 if (host->singleirq) {
592 unsigned int mask0 = readl(base + MMCIMASK0);
593
594 mask0 &= ~variant->irq_pio_mask;
595 mask0 |= mask;
596
597 writel(mask0, base + MMCIMASK0);
598 }
599
600 if (variant->mmcimask1)
601 writel(mask, base + MMCIMASK1);
602
603 host->mask1_reg = mask;
604 }
605
606 static void mmci_stop_data(struct mmci_host *host)
607 {
608 mmci_write_datactrlreg(host, 0);
609 mmci_set_mask1(host, 0);
610 host->data = NULL;
611 }
612
613 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
614 {
615 unsigned int flags = SG_MITER_ATOMIC;
616
617 if (data->flags & MMC_DATA_READ)
618 flags |= SG_MITER_TO_SG;
619 else
620 flags |= SG_MITER_FROM_SG;
621
622 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
623 }
624
625 /*
626 * All the DMA operation mode stuff goes inside this ifdef.
627 * This assumes that you have a generic DMA device interface,
628 * no custom DMA interfaces are supported.
629 */
630 #ifdef CONFIG_DMA_ENGINE
631 struct mmci_dmae_next {
632 struct dma_async_tx_descriptor *desc;
633 struct dma_chan *chan;
634 };
635
636 struct mmci_dmae_priv {
637 struct dma_chan *cur;
638 struct dma_chan *rx_channel;
639 struct dma_chan *tx_channel;
640 struct dma_async_tx_descriptor *desc_current;
641 struct mmci_dmae_next next_data;
642 };
643
644 int mmci_dmae_setup(struct mmci_host *host)
645 {
646 const char *rxname, *txname;
647 struct mmci_dmae_priv *dmae;
648
649 dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL);
650 if (!dmae)
651 return -ENOMEM;
652
653 host->dma_priv = dmae;
654
655 dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
656 "rx");
657 dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc),
658 "tx");
659
660 /*
661 * If only an RX channel is specified, the driver will
662 * attempt to use it bidirectionally, however if it is
663 * is specified but cannot be located, DMA will be disabled.
664 */
665 if (dmae->rx_channel && !dmae->tx_channel)
666 dmae->tx_channel = dmae->rx_channel;
667
668 if (dmae->rx_channel)
669 rxname = dma_chan_name(dmae->rx_channel);
670 else
671 rxname = "none";
672
673 if (dmae->tx_channel)
674 txname = dma_chan_name(dmae->tx_channel);
675 else
676 txname = "none";
677
678 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
679 rxname, txname);
680
681 /*
682 * Limit the maximum segment size in any SG entry according to
683 * the parameters of the DMA engine device.
684 */
685 if (dmae->tx_channel) {
686 struct device *dev = dmae->tx_channel->device->dev;
687 unsigned int max_seg_size = dma_get_max_seg_size(dev);
688
689 if (max_seg_size < host->mmc->max_seg_size)
690 host->mmc->max_seg_size = max_seg_size;
691 }
692 if (dmae->rx_channel) {
693 struct device *dev = dmae->rx_channel->device->dev;
694 unsigned int max_seg_size = dma_get_max_seg_size(dev);
695
696 if (max_seg_size < host->mmc->max_seg_size)
697 host->mmc->max_seg_size = max_seg_size;
698 }
699
700 if (!dmae->tx_channel || !dmae->rx_channel) {
701 mmci_dmae_release(host);
702 return -EINVAL;
703 }
704
705 return 0;
706 }
707
708 /*
709 * This is used in or so inline it
710 * so it can be discarded.
711 */
712 void mmci_dmae_release(struct mmci_host *host)
713 {
714 struct mmci_dmae_priv *dmae = host->dma_priv;
715
716 if (dmae->rx_channel)
717 dma_release_channel(dmae->rx_channel);
718 if (dmae->tx_channel)
719 dma_release_channel(dmae->tx_channel);
720 dmae->rx_channel = dmae->tx_channel = NULL;
721 }
722
723 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
724 {
725 struct mmci_dmae_priv *dmae = host->dma_priv;
726 struct dma_chan *chan;
727
728 if (data->flags & MMC_DATA_READ)
729 chan = dmae->rx_channel;
730 else
731 chan = dmae->tx_channel;
732
733 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
734 mmc_get_dma_dir(data));
735 }
736
737 void mmci_dmae_error(struct mmci_host *host)
738 {
739 struct mmci_dmae_priv *dmae = host->dma_priv;
740
741 if (!dma_inprogress(host))
742 return;
743
744 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
745 dmaengine_terminate_all(dmae->cur);
746 host->dma_in_progress = false;
747 dmae->cur = NULL;
748 dmae->desc_current = NULL;
749 host->data->host_cookie = 0;
750
751 mmci_dma_unmap(host, host->data);
752 }
753
754 void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data)
755 {
756 struct mmci_dmae_priv *dmae = host->dma_priv;
757 u32 status;
758 int i;
759
760 if (!dma_inprogress(host))
761 return;
762
763 /* Wait up to 1ms for the DMA to complete */
764 for (i = 0; ; i++) {
765 status = readl(host->base + MMCISTATUS);
766 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
767 break;
768 udelay(10);
769 }
770
771 /*
772 * Check to see whether we still have some data left in the FIFO -
773 * this catches DMA controllers which are unable to monitor the
774 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
775 * contiguous buffers. On TX, we'll get a FIFO underrun error.
776 */
777 if (status & MCI_RXDATAAVLBLMASK) {
778 mmci_dma_error(host);
779 if (!data->error)
780 data->error = -EIO;
781 } else if (!data->host_cookie) {
782 mmci_dma_unmap(host, data);
783 }
784
785 /*
786 * Use of DMA with scatter-gather is impossible.
787 * Give up with DMA and switch back to PIO mode.
788 */
789 if (status & MCI_RXDATAAVLBLMASK) {
790 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
791 mmci_dma_release(host);
792 }
793
794 host->dma_in_progress = false;
795 dmae->cur = NULL;
796 dmae->desc_current = NULL;
797 }
798
799 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
800 static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data,
801 struct dma_chan **dma_chan,
802 struct dma_async_tx_descriptor **dma_desc)
803 {
804 struct mmci_dmae_priv *dmae = host->dma_priv;
805 struct variant_data *variant = host->variant;
806 struct dma_slave_config conf = {
807 .src_addr = host->phybase + MMCIFIFO,
808 .dst_addr = host->phybase + MMCIFIFO,
809 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
810 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
811 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
812 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
813 .device_fc = false,
814 };
815 struct dma_chan *chan;
816 struct dma_device *device;
817 struct dma_async_tx_descriptor *desc;
818 int nr_sg;
819 unsigned long flags = DMA_CTRL_ACK;
820
821 if (data->flags & MMC_DATA_READ) {
822 conf.direction = DMA_DEV_TO_MEM;
823 chan = dmae->rx_channel;
824 } else {
825 conf.direction = DMA_MEM_TO_DEV;
826 chan = dmae->tx_channel;
827 }
828
829 /* If there's no DMA channel, fall back to PIO */
830 if (!chan)
831 return -EINVAL;
832
833 /* If less than or equal to the fifo size, don't bother with DMA */
834 if (data->blksz * data->blocks <= variant->fifosize)
835 return -EINVAL;
836
837 device = chan->device;
838 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
839 mmc_get_dma_dir(data));
840 if (nr_sg == 0)
841 return -EINVAL;
842
843 if (host->variant->qcom_dml)
844 flags |= DMA_PREP_INTERRUPT;
845
846 dmaengine_slave_config(chan, &conf);
847 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
848 conf.direction, flags);
849 if (!desc)
850 goto unmap_exit;
851
852 *dma_chan = chan;
853 *dma_desc = desc;
854
855 return 0;
856
857 unmap_exit:
858 dma_unmap_sg(device->dev, data->sg, data->sg_len,
859 mmc_get_dma_dir(data));
860 return -ENOMEM;
861 }
862
863 int mmci_dmae_prep_data(struct mmci_host *host,
864 struct mmc_data *data,
865 bool next)
866 {
867 struct mmci_dmae_priv *dmae = host->dma_priv;
868 struct mmci_dmae_next *nd = &dmae->next_data;
869
870 if (!host->use_dma)
871 return -EINVAL;
872
873 if (next)
874 return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc);
875 /* Check if next job is already prepared. */
876 if (dmae->cur && dmae->desc_current)
877 return 0;
878
879 /* No job were prepared thus do it now. */
880 return _mmci_dmae_prep_data(host, data, &dmae->cur,
881 &dmae->desc_current);
882 }
883
884 int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl)
885 {
886 struct mmci_dmae_priv *dmae = host->dma_priv;
887 struct mmc_data *data = host->data;
888
889 host->dma_in_progress = true;
890 dmaengine_submit(dmae->desc_current);
891 dma_async_issue_pending(dmae->cur);
892
893 if (host->variant->qcom_dml)
894 dml_start_xfer(host, data);
895
896 *datactrl |= MCI_DPSM_DMAENABLE;
897
898 return 0;
899 }
900
901 void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data)
902 {
903 struct mmci_dmae_priv *dmae = host->dma_priv;
904 struct mmci_dmae_next *next = &dmae->next_data;
905
906 if (!host->use_dma)
907 return;
908
909 WARN_ON(!data->host_cookie && (next->desc || next->chan));
910
911 dmae->desc_current = next->desc;
912 dmae->cur = next->chan;
913 next->desc = NULL;
914 next->chan = NULL;
915 }
916
917 void mmci_dmae_unprep_data(struct mmci_host *host,
918 struct mmc_data *data, int err)
919
920 {
921 struct mmci_dmae_priv *dmae = host->dma_priv;
922
923 if (!host->use_dma)
924 return;
925
926 mmci_dma_unmap(host, data);
927
928 if (err) {
929 struct mmci_dmae_next *next = &dmae->next_data;
930 struct dma_chan *chan;
931 if (data->flags & MMC_DATA_READ)
932 chan = dmae->rx_channel;
933 else
934 chan = dmae->tx_channel;
935 dmaengine_terminate_all(chan);
936
937 if (dmae->desc_current == next->desc)
938 dmae->desc_current = NULL;
939
940 if (dmae->cur == next->chan) {
941 host->dma_in_progress = false;
942 dmae->cur = NULL;
943 }
944
945 next->desc = NULL;
946 next->chan = NULL;
947 }
948 }
949
950 static struct mmci_host_ops mmci_variant_ops = {
951 .prep_data = mmci_dmae_prep_data,
952 .unprep_data = mmci_dmae_unprep_data,
953 .get_next_data = mmci_dmae_get_next_data,
954 .dma_setup = mmci_dmae_setup,
955 .dma_release = mmci_dmae_release,
956 .dma_start = mmci_dmae_start,
957 .dma_finalize = mmci_dmae_finalize,
958 .dma_error = mmci_dmae_error,
959 };
960
961 void mmci_variant_init(struct mmci_host *host)
962 {
963 host->ops = &mmci_variant_ops;
964 }
965 #endif
966
967 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
968 {
969 struct mmci_host *host = mmc_priv(mmc);
970 struct mmc_data *data = mrq->data;
971
972 if (!data)
973 return;
974
975 WARN_ON(data->host_cookie);
976
977 if (mmci_validate_data(host, data))
978 return;
979
980 mmci_prep_data(host, data, true);
981 }
982
983 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
984 int err)
985 {
986 struct mmci_host *host = mmc_priv(mmc);
987 struct mmc_data *data = mrq->data;
988
989 if (!data || !data->host_cookie)
990 return;
991
992 mmci_unprep_data(host, data, err);
993 }
994
995 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
996 {
997 struct variant_data *variant = host->variant;
998 unsigned int datactrl, timeout, irqmask;
999 unsigned long long clks;
1000 void __iomem *base;
1001 int blksz_bits;
1002
1003 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
1004 data->blksz, data->blocks, data->flags);
1005
1006 host->data = data;
1007 host->size = data->blksz * data->blocks;
1008 data->bytes_xfered = 0;
1009
1010 clks = (unsigned long long)data->timeout_ns * host->cclk;
1011 do_div(clks, NSEC_PER_SEC);
1012
1013 timeout = data->timeout_clks + (unsigned int)clks;
1014
1015 base = host->base;
1016 writel(timeout, base + MMCIDATATIMER);
1017 writel(host->size, base + MMCIDATALENGTH);
1018
1019 blksz_bits = ffs(data->blksz) - 1;
1020 BUG_ON(1 << blksz_bits != data->blksz);
1021
1022 if (variant->blksz_datactrl16)
1023 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 16);
1024 else if (variant->blksz_datactrl4)
1025 datactrl = variant->datactrl_dpsm_enable | (data->blksz << 4);
1026 else
1027 datactrl = variant->datactrl_dpsm_enable | blksz_bits << 4;
1028
1029 if (data->flags & MMC_DATA_READ)
1030 datactrl |= MCI_DPSM_DIRECTION;
1031
1032 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
1033 u32 clk;
1034
1035 datactrl |= variant->datactrl_mask_sdio;
1036
1037 /*
1038 * The ST Micro variant for SDIO small write transfers
1039 * needs to have clock H/W flow control disabled,
1040 * otherwise the transfer will not start. The threshold
1041 * depends on the rate of MCLK.
1042 */
1043 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
1044 (host->size < 8 ||
1045 (host->size <= 8 && host->mclk > 50000000)))
1046 clk = host->clk_reg & ~variant->clkreg_enable;
1047 else
1048 clk = host->clk_reg | variant->clkreg_enable;
1049
1050 mmci_write_clkreg(host, clk);
1051 }
1052
1053 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
1054 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
1055 datactrl |= variant->datactrl_mask_ddrmode;
1056
1057 /*
1058 * Attempt to use DMA operation mode, if this
1059 * should fail, fall back to PIO mode
1060 */
1061 if (!mmci_dma_start(host, datactrl))
1062 return;
1063
1064 /* IRQ mode, map the SG list for CPU reading/writing */
1065 mmci_init_sg(host, data);
1066
1067 if (data->flags & MMC_DATA_READ) {
1068 irqmask = MCI_RXFIFOHALFFULLMASK;
1069
1070 /*
1071 * If we have less than the fifo 'half-full' threshold to
1072 * transfer, trigger a PIO interrupt as soon as any data
1073 * is available.
1074 */
1075 if (host->size < variant->fifohalfsize)
1076 irqmask |= MCI_RXDATAAVLBLMASK;
1077 } else {
1078 /*
1079 * We don't actually need to include "FIFO empty" here
1080 * since its implicit in "FIFO half empty".
1081 */
1082 irqmask = MCI_TXFIFOHALFEMPTYMASK;
1083 }
1084
1085 mmci_write_datactrlreg(host, datactrl);
1086 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
1087 mmci_set_mask1(host, irqmask);
1088 }
1089
1090 static void
1091 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
1092 {
1093 void __iomem *base = host->base;
1094
1095 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
1096 cmd->opcode, cmd->arg, cmd->flags);
1097
1098 if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) {
1099 writel(0, base + MMCICOMMAND);
1100 mmci_reg_delay(host);
1101 }
1102
1103 c |= cmd->opcode | host->variant->cmdreg_cpsm_enable;
1104 if (cmd->flags & MMC_RSP_PRESENT) {
1105 if (cmd->flags & MMC_RSP_136)
1106 c |= host->variant->cmdreg_lrsp_crc;
1107 else if (cmd->flags & MMC_RSP_CRC)
1108 c |= host->variant->cmdreg_srsp_crc;
1109 else
1110 c |= host->variant->cmdreg_srsp;
1111 }
1112 if (/*interrupt*/0)
1113 c |= MCI_CPSM_INTERRUPT;
1114
1115 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
1116 c |= host->variant->data_cmd_enable;
1117
1118 host->cmd = cmd;
1119
1120 writel(cmd->arg, base + MMCIARGUMENT);
1121 writel(c, base + MMCICOMMAND);
1122 }
1123
1124 static void
1125 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
1126 unsigned int status)
1127 {
1128 unsigned int status_err;
1129
1130 /* Make sure we have data to handle */
1131 if (!data)
1132 return;
1133
1134 /* First check for errors */
1135 status_err = status & (host->variant->start_err |
1136 MCI_DATACRCFAIL | MCI_DATATIMEOUT |
1137 MCI_TXUNDERRUN | MCI_RXOVERRUN);
1138
1139 if (status_err) {
1140 u32 remain, success;
1141
1142 /* Terminate the DMA transfer */
1143 mmci_dma_error(host);
1144
1145 /*
1146 * Calculate how far we are into the transfer. Note that
1147 * the data counter gives the number of bytes transferred
1148 * on the MMC bus, not on the host side. On reads, this
1149 * can be as much as a FIFO-worth of data ahead. This
1150 * matters for FIFO overruns only.
1151 */
1152 if (!host->variant->datacnt_useless) {
1153 remain = readl(host->base + MMCIDATACNT);
1154 success = data->blksz * data->blocks - remain;
1155 } else {
1156 success = 0;
1157 }
1158
1159 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
1160 status_err, success);
1161 if (status_err & MCI_DATACRCFAIL) {
1162 /* Last block was not successful */
1163 success -= 1;
1164 data->error = -EILSEQ;
1165 } else if (status_err & MCI_DATATIMEOUT) {
1166 data->error = -ETIMEDOUT;
1167 } else if (status_err & MCI_STARTBITERR) {
1168 data->error = -ECOMM;
1169 } else if (status_err & MCI_TXUNDERRUN) {
1170 data->error = -EIO;
1171 } else if (status_err & MCI_RXOVERRUN) {
1172 if (success > host->variant->fifosize)
1173 success -= host->variant->fifosize;
1174 else
1175 success = 0;
1176 data->error = -EIO;
1177 }
1178 data->bytes_xfered = round_down(success, data->blksz);
1179 }
1180
1181 if (status & MCI_DATABLOCKEND)
1182 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
1183
1184 if (status & MCI_DATAEND || data->error) {
1185 mmci_dma_finalize(host, data);
1186
1187 mmci_stop_data(host);
1188
1189 if (!data->error)
1190 /* The error clause is handled above, success! */
1191 data->bytes_xfered = data->blksz * data->blocks;
1192
1193 if (!data->stop || host->mrq->sbc) {
1194 mmci_request_end(host, data->mrq);
1195 } else {
1196 mmci_start_command(host, data->stop, 0);
1197 }
1198 }
1199 }
1200
1201 static void
1202 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
1203 unsigned int status)
1204 {
1205 void __iomem *base = host->base;
1206 bool sbc;
1207
1208 if (!cmd)
1209 return;
1210
1211 sbc = (cmd == host->mrq->sbc);
1212
1213 /*
1214 * We need to be one of these interrupts to be considered worth
1215 * handling. Note that we tag on any latent IRQs postponed
1216 * due to waiting for busy status.
1217 */
1218 if (!((status|host->busy_status) &
1219 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
1220 return;
1221
1222 /*
1223 * ST Micro variant: handle busy detection.
1224 */
1225 if (host->variant->busy_detect) {
1226 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
1227
1228 /* We are busy with a command, return */
1229 if (host->busy_status &&
1230 (status & host->variant->busy_detect_flag))
1231 return;
1232
1233 /*
1234 * We were not busy, but we now got a busy response on
1235 * something that was not an error, and we double-check
1236 * that the special busy status bit is still set before
1237 * proceeding.
1238 */
1239 if (!host->busy_status && busy_resp &&
1240 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1241 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1242
1243 /* Clear the busy start IRQ */
1244 writel(host->variant->busy_detect_mask,
1245 host->base + MMCICLEAR);
1246
1247 /* Unmask the busy end IRQ */
1248 writel(readl(base + MMCIMASK0) |
1249 host->variant->busy_detect_mask,
1250 base + MMCIMASK0);
1251 /*
1252 * Now cache the last response status code (until
1253 * the busy bit goes low), and return.
1254 */
1255 host->busy_status =
1256 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1257 return;
1258 }
1259
1260 /*
1261 * At this point we are not busy with a command, we have
1262 * not received a new busy request, clear and mask the busy
1263 * end IRQ and fall through to process the IRQ.
1264 */
1265 if (host->busy_status) {
1266
1267 writel(host->variant->busy_detect_mask,
1268 host->base + MMCICLEAR);
1269
1270 writel(readl(base + MMCIMASK0) &
1271 ~host->variant->busy_detect_mask,
1272 base + MMCIMASK0);
1273 host->busy_status = 0;
1274 }
1275 }
1276
1277 host->cmd = NULL;
1278
1279 if (status & MCI_CMDTIMEOUT) {
1280 cmd->error = -ETIMEDOUT;
1281 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1282 cmd->error = -EILSEQ;
1283 } else {
1284 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1285 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1286 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1287 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1288 }
1289
1290 if ((!sbc && !cmd->data) || cmd->error) {
1291 if (host->data) {
1292 /* Terminate the DMA transfer */
1293 mmci_dma_error(host);
1294
1295 mmci_stop_data(host);
1296 }
1297 mmci_request_end(host, host->mrq);
1298 } else if (sbc) {
1299 mmci_start_command(host, host->mrq->cmd, 0);
1300 } else if (!host->variant->datactrl_first &&
1301 !(cmd->data->flags & MMC_DATA_READ)) {
1302 mmci_start_data(host, cmd->data);
1303 }
1304 }
1305
1306 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1307 {
1308 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1309 }
1310
1311 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1312 {
1313 /*
1314 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1315 * from the fifo range should be used
1316 */
1317 if (status & MCI_RXFIFOHALFFULL)
1318 return host->variant->fifohalfsize;
1319 else if (status & MCI_RXDATAAVLBL)
1320 return 4;
1321
1322 return 0;
1323 }
1324
1325 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1326 {
1327 void __iomem *base = host->base;
1328 char *ptr = buffer;
1329 u32 status = readl(host->base + MMCISTATUS);
1330 int host_remain = host->size;
1331
1332 do {
1333 int count = host->get_rx_fifocnt(host, status, host_remain);
1334
1335 if (count > remain)
1336 count = remain;
1337
1338 if (count <= 0)
1339 break;
1340
1341 /*
1342 * SDIO especially may want to send something that is
1343 * not divisible by 4 (as opposed to card sectors
1344 * etc). Therefore make sure to always read the last bytes
1345 * while only doing full 32-bit reads towards the FIFO.
1346 */
1347 if (unlikely(count & 0x3)) {
1348 if (count < 4) {
1349 unsigned char buf[4];
1350 ioread32_rep(base + MMCIFIFO, buf, 1);
1351 memcpy(ptr, buf, count);
1352 } else {
1353 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1354 count &= ~0x3;
1355 }
1356 } else {
1357 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1358 }
1359
1360 ptr += count;
1361 remain -= count;
1362 host_remain -= count;
1363
1364 if (remain == 0)
1365 break;
1366
1367 status = readl(base + MMCISTATUS);
1368 } while (status & MCI_RXDATAAVLBL);
1369
1370 return ptr - buffer;
1371 }
1372
1373 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1374 {
1375 struct variant_data *variant = host->variant;
1376 void __iomem *base = host->base;
1377 char *ptr = buffer;
1378
1379 do {
1380 unsigned int count, maxcnt;
1381
1382 maxcnt = status & MCI_TXFIFOEMPTY ?
1383 variant->fifosize : variant->fifohalfsize;
1384 count = min(remain, maxcnt);
1385
1386 /*
1387 * SDIO especially may want to send something that is
1388 * not divisible by 4 (as opposed to card sectors
1389 * etc), and the FIFO only accept full 32-bit writes.
1390 * So compensate by adding +3 on the count, a single
1391 * byte become a 32bit write, 7 bytes will be two
1392 * 32bit writes etc.
1393 */
1394 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1395
1396 ptr += count;
1397 remain -= count;
1398
1399 if (remain == 0)
1400 break;
1401
1402 status = readl(base + MMCISTATUS);
1403 } while (status & MCI_TXFIFOHALFEMPTY);
1404
1405 return ptr - buffer;
1406 }
1407
1408 /*
1409 * PIO data transfer IRQ handler.
1410 */
1411 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1412 {
1413 struct mmci_host *host = dev_id;
1414 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1415 struct variant_data *variant = host->variant;
1416 void __iomem *base = host->base;
1417 u32 status;
1418
1419 status = readl(base + MMCISTATUS);
1420
1421 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1422
1423 do {
1424 unsigned int remain, len;
1425 char *buffer;
1426
1427 /*
1428 * For write, we only need to test the half-empty flag
1429 * here - if the FIFO is completely empty, then by
1430 * definition it is more than half empty.
1431 *
1432 * For read, check for data available.
1433 */
1434 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1435 break;
1436
1437 if (!sg_miter_next(sg_miter))
1438 break;
1439
1440 buffer = sg_miter->addr;
1441 remain = sg_miter->length;
1442
1443 len = 0;
1444 if (status & MCI_RXACTIVE)
1445 len = mmci_pio_read(host, buffer, remain);
1446 if (status & MCI_TXACTIVE)
1447 len = mmci_pio_write(host, buffer, remain, status);
1448
1449 sg_miter->consumed = len;
1450
1451 host->size -= len;
1452 remain -= len;
1453
1454 if (remain)
1455 break;
1456
1457 status = readl(base + MMCISTATUS);
1458 } while (1);
1459
1460 sg_miter_stop(sg_miter);
1461
1462 /*
1463 * If we have less than the fifo 'half-full' threshold to transfer,
1464 * trigger a PIO interrupt as soon as any data is available.
1465 */
1466 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1467 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1468
1469 /*
1470 * If we run out of data, disable the data IRQs; this
1471 * prevents a race where the FIFO becomes empty before
1472 * the chip itself has disabled the data path, and
1473 * stops us racing with our data end IRQ.
1474 */
1475 if (host->size == 0) {
1476 mmci_set_mask1(host, 0);
1477 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1478 }
1479
1480 return IRQ_HANDLED;
1481 }
1482
1483 /*
1484 * Handle completion of command and data transfers.
1485 */
1486 static irqreturn_t mmci_irq(int irq, void *dev_id)
1487 {
1488 struct mmci_host *host = dev_id;
1489 u32 status;
1490 int ret = 0;
1491
1492 spin_lock(&host->lock);
1493
1494 do {
1495 status = readl(host->base + MMCISTATUS);
1496
1497 if (host->singleirq) {
1498 if (status & host->mask1_reg)
1499 mmci_pio_irq(irq, dev_id);
1500
1501 status &= ~host->variant->irq_pio_mask;
1502 }
1503
1504 /*
1505 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1506 * enabled) in mmci_cmd_irq() function where ST Micro busy
1507 * detection variant is handled. Considering the HW seems to be
1508 * triggering the IRQ on both edges while monitoring DAT0 for
1509 * busy completion and that same status bit is used to monitor
1510 * start and end of busy detection, special care must be taken
1511 * to make sure that both start and end interrupts are always
1512 * cleared one after the other.
1513 */
1514 status &= readl(host->base + MMCIMASK0);
1515 if (host->variant->busy_detect)
1516 writel(status & ~host->variant->busy_detect_mask,
1517 host->base + MMCICLEAR);
1518 else
1519 writel(status, host->base + MMCICLEAR);
1520
1521 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1522
1523 if (host->variant->reversed_irq_handling) {
1524 mmci_data_irq(host, host->data, status);
1525 mmci_cmd_irq(host, host->cmd, status);
1526 } else {
1527 mmci_cmd_irq(host, host->cmd, status);
1528 mmci_data_irq(host, host->data, status);
1529 }
1530
1531 /*
1532 * Don't poll for busy completion in irq context.
1533 */
1534 if (host->variant->busy_detect && host->busy_status)
1535 status &= ~host->variant->busy_detect_flag;
1536
1537 ret = 1;
1538 } while (status);
1539
1540 spin_unlock(&host->lock);
1541
1542 return IRQ_RETVAL(ret);
1543 }
1544
1545 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1546 {
1547 struct mmci_host *host = mmc_priv(mmc);
1548 unsigned long flags;
1549
1550 WARN_ON(host->mrq != NULL);
1551
1552 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1553 if (mrq->cmd->error) {
1554 mmc_request_done(mmc, mrq);
1555 return;
1556 }
1557
1558 spin_lock_irqsave(&host->lock, flags);
1559
1560 host->mrq = mrq;
1561
1562 if (mrq->data)
1563 mmci_get_next_data(host, mrq->data);
1564
1565 if (mrq->data &&
1566 (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ))
1567 mmci_start_data(host, mrq->data);
1568
1569 if (mrq->sbc)
1570 mmci_start_command(host, mrq->sbc, 0);
1571 else
1572 mmci_start_command(host, mrq->cmd, 0);
1573
1574 spin_unlock_irqrestore(&host->lock, flags);
1575 }
1576
1577 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1578 {
1579 struct mmci_host *host = mmc_priv(mmc);
1580 struct variant_data *variant = host->variant;
1581 u32 pwr = 0;
1582 unsigned long flags;
1583 int ret;
1584
1585 if (host->plat->ios_handler &&
1586 host->plat->ios_handler(mmc_dev(mmc), ios))
1587 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1588
1589 switch (ios->power_mode) {
1590 case MMC_POWER_OFF:
1591 if (!IS_ERR(mmc->supply.vmmc))
1592 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1593
1594 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1595 regulator_disable(mmc->supply.vqmmc);
1596 host->vqmmc_enabled = false;
1597 }
1598
1599 break;
1600 case MMC_POWER_UP:
1601 if (!IS_ERR(mmc->supply.vmmc))
1602 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1603
1604 /*
1605 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1606 * and instead uses MCI_PWR_ON so apply whatever value is
1607 * configured in the variant data.
1608 */
1609 pwr |= variant->pwrreg_powerup;
1610
1611 break;
1612 case MMC_POWER_ON:
1613 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1614 ret = regulator_enable(mmc->supply.vqmmc);
1615 if (ret < 0)
1616 dev_err(mmc_dev(mmc),
1617 "failed to enable vqmmc regulator\n");
1618 else
1619 host->vqmmc_enabled = true;
1620 }
1621
1622 pwr |= MCI_PWR_ON;
1623 break;
1624 }
1625
1626 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1627 /*
1628 * The ST Micro variant has some additional bits
1629 * indicating signal direction for the signals in
1630 * the SD/MMC bus and feedback-clock usage.
1631 */
1632 pwr |= host->pwr_reg_add;
1633
1634 if (ios->bus_width == MMC_BUS_WIDTH_4)
1635 pwr &= ~MCI_ST_DATA74DIREN;
1636 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1637 pwr &= (~MCI_ST_DATA74DIREN &
1638 ~MCI_ST_DATA31DIREN &
1639 ~MCI_ST_DATA2DIREN);
1640 }
1641
1642 if (variant->opendrain) {
1643 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1644 pwr |= variant->opendrain;
1645 } else {
1646 /*
1647 * If the variant cannot configure the pads by its own, then we
1648 * expect the pinctrl to be able to do that for us
1649 */
1650 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1651 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1652 else
1653 pinctrl_select_state(host->pinctrl, host->pins_default);
1654 }
1655
1656 /*
1657 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1658 * gating the clock, the MCI_PWR_ON bit is cleared.
1659 */
1660 if (!ios->clock && variant->pwrreg_clkgate)
1661 pwr &= ~MCI_PWR_ON;
1662
1663 if (host->variant->explicit_mclk_control &&
1664 ios->clock != host->clock_cache) {
1665 ret = clk_set_rate(host->clk, ios->clock);
1666 if (ret < 0)
1667 dev_err(mmc_dev(host->mmc),
1668 "Error setting clock rate (%d)\n", ret);
1669 else
1670 host->mclk = clk_get_rate(host->clk);
1671 }
1672 host->clock_cache = ios->clock;
1673
1674 spin_lock_irqsave(&host->lock, flags);
1675
1676 if (host->ops && host->ops->set_clkreg)
1677 host->ops->set_clkreg(host, ios->clock);
1678 else
1679 mmci_set_clkreg(host, ios->clock);
1680
1681 if (host->ops && host->ops->set_pwrreg)
1682 host->ops->set_pwrreg(host, pwr);
1683 else
1684 mmci_write_pwrreg(host, pwr);
1685
1686 mmci_reg_delay(host);
1687
1688 spin_unlock_irqrestore(&host->lock, flags);
1689 }
1690
1691 static int mmci_get_cd(struct mmc_host *mmc)
1692 {
1693 struct mmci_host *host = mmc_priv(mmc);
1694 struct mmci_platform_data *plat = host->plat;
1695 unsigned int status = mmc_gpio_get_cd(mmc);
1696
1697 if (status == -ENOSYS) {
1698 if (!plat->status)
1699 return 1; /* Assume always present */
1700
1701 status = plat->status(mmc_dev(host->mmc));
1702 }
1703 return status;
1704 }
1705
1706 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1707 {
1708 int ret = 0;
1709
1710 if (!IS_ERR(mmc->supply.vqmmc)) {
1711
1712 switch (ios->signal_voltage) {
1713 case MMC_SIGNAL_VOLTAGE_330:
1714 ret = regulator_set_voltage(mmc->supply.vqmmc,
1715 2700000, 3600000);
1716 break;
1717 case MMC_SIGNAL_VOLTAGE_180:
1718 ret = regulator_set_voltage(mmc->supply.vqmmc,
1719 1700000, 1950000);
1720 break;
1721 case MMC_SIGNAL_VOLTAGE_120:
1722 ret = regulator_set_voltage(mmc->supply.vqmmc,
1723 1100000, 1300000);
1724 break;
1725 }
1726
1727 if (ret)
1728 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1729 }
1730
1731 return ret;
1732 }
1733
1734 static struct mmc_host_ops mmci_ops = {
1735 .request = mmci_request,
1736 .pre_req = mmci_pre_request,
1737 .post_req = mmci_post_request,
1738 .set_ios = mmci_set_ios,
1739 .get_ro = mmc_gpio_get_ro,
1740 .get_cd = mmci_get_cd,
1741 .start_signal_voltage_switch = mmci_sig_volt_switch,
1742 };
1743
1744 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1745 {
1746 struct mmci_host *host = mmc_priv(mmc);
1747 int ret = mmc_of_parse(mmc);
1748
1749 if (ret)
1750 return ret;
1751
1752 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1753 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1754 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1755 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1756 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1757 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1758 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1759 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1760 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1761 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1762 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1763 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1764 if (of_get_property(np, "st,sig-dir", NULL))
1765 host->pwr_reg_add |= MCI_STM32_DIRPOL;
1766 if (of_get_property(np, "st,neg-edge", NULL))
1767 host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE;
1768 if (of_get_property(np, "st,use-ckin", NULL))
1769 host->clk_reg_add |= MCI_STM32_CLK_SELCKIN;
1770
1771 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1772 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1773 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1774 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1775
1776 return 0;
1777 }
1778
1779 static int mmci_probe(struct amba_device *dev,
1780 const struct amba_id *id)
1781 {
1782 struct mmci_platform_data *plat = dev->dev.platform_data;
1783 struct device_node *np = dev->dev.of_node;
1784 struct variant_data *variant = id->data;
1785 struct mmci_host *host;
1786 struct mmc_host *mmc;
1787 int ret;
1788
1789 /* Must have platform data or Device Tree. */
1790 if (!plat && !np) {
1791 dev_err(&dev->dev, "No plat data or DT found\n");
1792 return -EINVAL;
1793 }
1794
1795 if (!plat) {
1796 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1797 if (!plat)
1798 return -ENOMEM;
1799 }
1800
1801 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1802 if (!mmc)
1803 return -ENOMEM;
1804
1805 ret = mmci_of_parse(np, mmc);
1806 if (ret)
1807 goto host_free;
1808
1809 host = mmc_priv(mmc);
1810 host->mmc = mmc;
1811
1812 /*
1813 * Some variant (STM32) doesn't have opendrain bit, nevertheless
1814 * pins can be set accordingly using pinctrl
1815 */
1816 if (!variant->opendrain) {
1817 host->pinctrl = devm_pinctrl_get(&dev->dev);
1818 if (IS_ERR(host->pinctrl)) {
1819 dev_err(&dev->dev, "failed to get pinctrl");
1820 ret = PTR_ERR(host->pinctrl);
1821 goto host_free;
1822 }
1823
1824 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1825 PINCTRL_STATE_DEFAULT);
1826 if (IS_ERR(host->pins_default)) {
1827 dev_err(mmc_dev(mmc), "Can't select default pins\n");
1828 ret = PTR_ERR(host->pins_default);
1829 goto host_free;
1830 }
1831
1832 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1833 MMCI_PINCTRL_STATE_OPENDRAIN);
1834 if (IS_ERR(host->pins_opendrain)) {
1835 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1836 ret = PTR_ERR(host->pins_opendrain);
1837 goto host_free;
1838 }
1839 }
1840
1841 host->hw_designer = amba_manf(dev);
1842 host->hw_revision = amba_rev(dev);
1843 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1844 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1845
1846 host->clk = devm_clk_get(&dev->dev, NULL);
1847 if (IS_ERR(host->clk)) {
1848 ret = PTR_ERR(host->clk);
1849 goto host_free;
1850 }
1851
1852 ret = clk_prepare_enable(host->clk);
1853 if (ret)
1854 goto host_free;
1855
1856 if (variant->qcom_fifo)
1857 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1858 else
1859 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1860
1861 host->plat = plat;
1862 host->variant = variant;
1863 host->mclk = clk_get_rate(host->clk);
1864 /*
1865 * According to the spec, mclk is max 100 MHz,
1866 * so we try to adjust the clock down to this,
1867 * (if possible).
1868 */
1869 if (host->mclk > variant->f_max) {
1870 ret = clk_set_rate(host->clk, variant->f_max);
1871 if (ret < 0)
1872 goto clk_disable;
1873 host->mclk = clk_get_rate(host->clk);
1874 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1875 host->mclk);
1876 }
1877
1878 host->phybase = dev->res.start;
1879 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1880 if (IS_ERR(host->base)) {
1881 ret = PTR_ERR(host->base);
1882 goto clk_disable;
1883 }
1884
1885 if (variant->init)
1886 variant->init(host);
1887
1888 /*
1889 * The ARM and ST versions of the block have slightly different
1890 * clock divider equations which means that the minimum divider
1891 * differs too.
1892 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1893 */
1894 if (variant->st_clkdiv)
1895 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1896 else if (variant->stm32_clkdiv)
1897 mmc->f_min = DIV_ROUND_UP(host->mclk, 2046);
1898 else if (variant->explicit_mclk_control)
1899 mmc->f_min = clk_round_rate(host->clk, 100000);
1900 else
1901 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1902 /*
1903 * If no maximum operating frequency is supplied, fall back to use
1904 * the module parameter, which has a (low) default value in case it
1905 * is not specified. Either value must not exceed the clock rate into
1906 * the block, of course.
1907 */
1908 if (mmc->f_max)
1909 mmc->f_max = variant->explicit_mclk_control ?
1910 min(variant->f_max, mmc->f_max) :
1911 min(host->mclk, mmc->f_max);
1912 else
1913 mmc->f_max = variant->explicit_mclk_control ?
1914 fmax : min(host->mclk, fmax);
1915
1916
1917 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1918
1919 host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL);
1920 if (IS_ERR(host->rst)) {
1921 ret = PTR_ERR(host->rst);
1922 goto clk_disable;
1923 }
1924
1925 /* Get regulators and the supported OCR mask */
1926 ret = mmc_regulator_get_supply(mmc);
1927 if (ret)
1928 goto clk_disable;
1929
1930 if (!mmc->ocr_avail)
1931 mmc->ocr_avail = plat->ocr_mask;
1932 else if (plat->ocr_mask)
1933 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1934
1935 /* We support these capabilities. */
1936 mmc->caps |= MMC_CAP_CMD23;
1937
1938 /*
1939 * Enable busy detection.
1940 */
1941 if (variant->busy_detect) {
1942 mmci_ops.card_busy = mmci_card_busy;
1943 /*
1944 * Not all variants have a flag to enable busy detection
1945 * in the DPSM, but if they do, set it here.
1946 */
1947 if (variant->busy_dpsm_flag)
1948 mmci_write_datactrlreg(host,
1949 host->variant->busy_dpsm_flag);
1950 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1951 mmc->max_busy_timeout = 0;
1952 }
1953
1954 mmc->ops = &mmci_ops;
1955
1956 /* We support these PM capabilities. */
1957 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1958
1959 /*
1960 * We can do SGIO
1961 */
1962 mmc->max_segs = NR_SG;
1963
1964 /*
1965 * Since only a certain number of bits are valid in the data length
1966 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1967 * single request.
1968 */
1969 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1970
1971 /*
1972 * Set the maximum segment size. Since we aren't doing DMA
1973 * (yet) we are only limited by the data length register.
1974 */
1975 mmc->max_seg_size = mmc->max_req_size;
1976
1977 /*
1978 * Block size can be up to 2048 bytes, but must be a power of two.
1979 */
1980 mmc->max_blk_size = 1 << variant->datactrl_blocksz;
1981
1982 /*
1983 * Limit the number of blocks transferred so that we don't overflow
1984 * the maximum request size.
1985 */
1986 mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz;
1987
1988 spin_lock_init(&host->lock);
1989
1990 writel(0, host->base + MMCIMASK0);
1991
1992 if (variant->mmcimask1)
1993 writel(0, host->base + MMCIMASK1);
1994
1995 writel(0xfff, host->base + MMCICLEAR);
1996
1997 /*
1998 * If:
1999 * - not using DT but using a descriptor table, or
2000 * - using a table of descriptors ALONGSIDE DT, or
2001 * look up these descriptors named "cd" and "wp" right here, fail
2002 * silently of these do not exist
2003 */
2004 if (!np) {
2005 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
2006 if (ret == -EPROBE_DEFER)
2007 goto clk_disable;
2008
2009 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
2010 if (ret == -EPROBE_DEFER)
2011 goto clk_disable;
2012 }
2013
2014 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
2015 DRIVER_NAME " (cmd)", host);
2016 if (ret)
2017 goto clk_disable;
2018
2019 if (!dev->irq[1])
2020 host->singleirq = true;
2021 else {
2022 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
2023 IRQF_SHARED, DRIVER_NAME " (pio)", host);
2024 if (ret)
2025 goto clk_disable;
2026 }
2027
2028 writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0);
2029
2030 amba_set_drvdata(dev, mmc);
2031
2032 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
2033 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
2034 amba_rev(dev), (unsigned long long)dev->res.start,
2035 dev->irq[0], dev->irq[1]);
2036
2037 mmci_dma_setup(host);
2038
2039 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
2040 pm_runtime_use_autosuspend(&dev->dev);
2041
2042 mmc_add_host(mmc);
2043
2044 pm_runtime_put(&dev->dev);
2045 return 0;
2046
2047 clk_disable:
2048 clk_disable_unprepare(host->clk);
2049 host_free:
2050 mmc_free_host(mmc);
2051 return ret;
2052 }
2053
2054 static int mmci_remove(struct amba_device *dev)
2055 {
2056 struct mmc_host *mmc = amba_get_drvdata(dev);
2057
2058 if (mmc) {
2059 struct mmci_host *host = mmc_priv(mmc);
2060 struct variant_data *variant = host->variant;
2061
2062 /*
2063 * Undo pm_runtime_put() in probe. We use the _sync
2064 * version here so that we can access the primecell.
2065 */
2066 pm_runtime_get_sync(&dev->dev);
2067
2068 mmc_remove_host(mmc);
2069
2070 writel(0, host->base + MMCIMASK0);
2071
2072 if (variant->mmcimask1)
2073 writel(0, host->base + MMCIMASK1);
2074
2075 writel(0, host->base + MMCICOMMAND);
2076 writel(0, host->base + MMCIDATACTRL);
2077
2078 mmci_dma_release(host);
2079 clk_disable_unprepare(host->clk);
2080 mmc_free_host(mmc);
2081 }
2082
2083 return 0;
2084 }
2085
2086 #ifdef CONFIG_PM
2087 static void mmci_save(struct mmci_host *host)
2088 {
2089 unsigned long flags;
2090
2091 spin_lock_irqsave(&host->lock, flags);
2092
2093 writel(0, host->base + MMCIMASK0);
2094 if (host->variant->pwrreg_nopower) {
2095 writel(0, host->base + MMCIDATACTRL);
2096 writel(0, host->base + MMCIPOWER);
2097 writel(0, host->base + MMCICLOCK);
2098 }
2099 mmci_reg_delay(host);
2100
2101 spin_unlock_irqrestore(&host->lock, flags);
2102 }
2103
2104 static void mmci_restore(struct mmci_host *host)
2105 {
2106 unsigned long flags;
2107
2108 spin_lock_irqsave(&host->lock, flags);
2109
2110 if (host->variant->pwrreg_nopower) {
2111 writel(host->clk_reg, host->base + MMCICLOCK);
2112 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
2113 writel(host->pwr_reg, host->base + MMCIPOWER);
2114 }
2115 writel(MCI_IRQENABLE | host->variant->start_err,
2116 host->base + MMCIMASK0);
2117 mmci_reg_delay(host);
2118
2119 spin_unlock_irqrestore(&host->lock, flags);
2120 }
2121
2122 static int mmci_runtime_suspend(struct device *dev)
2123 {
2124 struct amba_device *adev = to_amba_device(dev);
2125 struct mmc_host *mmc = amba_get_drvdata(adev);
2126
2127 if (mmc) {
2128 struct mmci_host *host = mmc_priv(mmc);
2129 pinctrl_pm_select_sleep_state(dev);
2130 mmci_save(host);
2131 clk_disable_unprepare(host->clk);
2132 }
2133
2134 return 0;
2135 }
2136
2137 static int mmci_runtime_resume(struct device *dev)
2138 {
2139 struct amba_device *adev = to_amba_device(dev);
2140 struct mmc_host *mmc = amba_get_drvdata(adev);
2141
2142 if (mmc) {
2143 struct mmci_host *host = mmc_priv(mmc);
2144 clk_prepare_enable(host->clk);
2145 mmci_restore(host);
2146 pinctrl_pm_select_default_state(dev);
2147 }
2148
2149 return 0;
2150 }
2151 #endif
2152
2153 static const struct dev_pm_ops mmci_dev_pm_ops = {
2154 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
2155 pm_runtime_force_resume)
2156 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
2157 };
2158
2159 static const struct amba_id mmci_ids[] = {
2160 {
2161 .id = 0x00041180,
2162 .mask = 0xff0fffff,
2163 .data = &variant_arm,
2164 },
2165 {
2166 .id = 0x01041180,
2167 .mask = 0xff0fffff,
2168 .data = &variant_arm_extended_fifo,
2169 },
2170 {
2171 .id = 0x02041180,
2172 .mask = 0xff0fffff,
2173 .data = &variant_arm_extended_fifo_hwfc,
2174 },
2175 {
2176 .id = 0x00041181,
2177 .mask = 0x000fffff,
2178 .data = &variant_arm,
2179 },
2180 /* ST Micro variants */
2181 {
2182 .id = 0x00180180,
2183 .mask = 0x00ffffff,
2184 .data = &variant_u300,
2185 },
2186 {
2187 .id = 0x10180180,
2188 .mask = 0xf0ffffff,
2189 .data = &variant_nomadik,
2190 },
2191 {
2192 .id = 0x00280180,
2193 .mask = 0x00ffffff,
2194 .data = &variant_nomadik,
2195 },
2196 {
2197 .id = 0x00480180,
2198 .mask = 0xf0ffffff,
2199 .data = &variant_ux500,
2200 },
2201 {
2202 .id = 0x10480180,
2203 .mask = 0xf0ffffff,
2204 .data = &variant_ux500v2,
2205 },
2206 {
2207 .id = 0x00880180,
2208 .mask = 0x00ffffff,
2209 .data = &variant_stm32,
2210 },
2211 {
2212 .id = 0x10153180,
2213 .mask = 0xf0ffffff,
2214 .data = &variant_stm32_sdmmc,
2215 },
2216 /* Qualcomm variants */
2217 {
2218 .id = 0x00051180,
2219 .mask = 0x000fffff,
2220 .data = &variant_qcom,
2221 },
2222 { 0, 0 },
2223 };
2224
2225 MODULE_DEVICE_TABLE(amba, mmci_ids);
2226
2227 static struct amba_driver mmci_driver = {
2228 .drv = {
2229 .name = DRIVER_NAME,
2230 .pm = &mmci_dev_pm_ops,
2231 },
2232 .probe = mmci_probe,
2233 .remove = mmci_remove,
2234 .id_table = mmci_ids,
2235 };
2236
2237 module_amba_driver(mmci_driver);
2238
2239 module_param(fmax, uint, 0444);
2240
2241 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2242 MODULE_LICENSE("GPL");
Linux with added FPC-III support