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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / mmc / host / mxcmmc.c
blob4d17032d15eef5d1b412df99aa7b661c045ac48b
1 /*
2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
3 *
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
8 *
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
11 *
12 * derived from pxamci.c by Russell King
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
17 *
18 */
19
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/highmem.h>
25 #include <linux/interrupt.h>
26 #include <linux/irq.h>
27 #include <linux/blkdev.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/delay.h>
32 #include <linux/clk.h>
33 #include <linux/io.h>
34 #include <linux/gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/dmaengine.h>
37 #include <linux/types.h>
38 #include <linux/of.h>
39 #include <linux/of_device.h>
40 #include <linux/of_dma.h>
41 #include <linux/of_gpio.h>
42 #include <linux/mmc/slot-gpio.h>
43
44 #include <asm/dma.h>
45 #include <asm/irq.h>
46 #include <linux/platform_data/mmc-mxcmmc.h>
47
48 #include <linux/platform_data/dma-imx.h>
49
50 #define DRIVER_NAME "mxc-mmc"
51 #define MXCMCI_TIMEOUT_MS 10000
52
53 #define MMC_REG_STR_STP_CLK 0x00
54 #define MMC_REG_STATUS 0x04
55 #define MMC_REG_CLK_RATE 0x08
56 #define MMC_REG_CMD_DAT_CONT 0x0C
57 #define MMC_REG_RES_TO 0x10
58 #define MMC_REG_READ_TO 0x14
59 #define MMC_REG_BLK_LEN 0x18
60 #define MMC_REG_NOB 0x1C
61 #define MMC_REG_REV_NO 0x20
62 #define MMC_REG_INT_CNTR 0x24
63 #define MMC_REG_CMD 0x28
64 #define MMC_REG_ARG 0x2C
65 #define MMC_REG_RES_FIFO 0x34
66 #define MMC_REG_BUFFER_ACCESS 0x38
67
68 #define STR_STP_CLK_RESET (1 << 3)
69 #define STR_STP_CLK_START_CLK (1 << 1)
70 #define STR_STP_CLK_STOP_CLK (1 << 0)
71
72 #define STATUS_CARD_INSERTION (1 << 31)
73 #define STATUS_CARD_REMOVAL (1 << 30)
74 #define STATUS_YBUF_EMPTY (1 << 29)
75 #define STATUS_XBUF_EMPTY (1 << 28)
76 #define STATUS_YBUF_FULL (1 << 27)
77 #define STATUS_XBUF_FULL (1 << 26)
78 #define STATUS_BUF_UND_RUN (1 << 25)
79 #define STATUS_BUF_OVFL (1 << 24)
80 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
81 #define STATUS_END_CMD_RESP (1 << 13)
82 #define STATUS_WRITE_OP_DONE (1 << 12)
83 #define STATUS_DATA_TRANS_DONE (1 << 11)
84 #define STATUS_READ_OP_DONE (1 << 11)
85 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
86 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
87 #define STATUS_BUF_READ_RDY (1 << 7)
88 #define STATUS_BUF_WRITE_RDY (1 << 6)
89 #define STATUS_RESP_CRC_ERR (1 << 5)
90 #define STATUS_CRC_READ_ERR (1 << 3)
91 #define STATUS_CRC_WRITE_ERR (1 << 2)
92 #define STATUS_TIME_OUT_RESP (1 << 1)
93 #define STATUS_TIME_OUT_READ (1 << 0)
94 #define STATUS_ERR_MASK 0x2f
95
96 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
97 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
98 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
99 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
100 #define CMD_DAT_CONT_INIT (1 << 7)
101 #define CMD_DAT_CONT_WRITE (1 << 4)
102 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
103 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
104 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
105 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
106
107 #define INT_SDIO_INT_WKP_EN (1 << 18)
108 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
109 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
110 #define INT_CARD_INSERTION_EN (1 << 15)
111 #define INT_CARD_REMOVAL_EN (1 << 14)
112 #define INT_SDIO_IRQ_EN (1 << 13)
113 #define INT_DAT0_EN (1 << 12)
114 #define INT_BUF_READ_EN (1 << 4)
115 #define INT_BUF_WRITE_EN (1 << 3)
116 #define INT_END_CMD_RES_EN (1 << 2)
117 #define INT_WRITE_OP_DONE_EN (1 << 1)
118 #define INT_READ_OP_EN (1 << 0)
119
120 enum mxcmci_type {
121 IMX21_MMC,
122 IMX31_MMC,
123 MPC512X_MMC,
124 };
125
126 struct mxcmci_host {
127 struct mmc_host *mmc;
128 void __iomem *base;
129 dma_addr_t phys_base;
130 int detect_irq;
131 struct dma_chan *dma;
132 struct dma_async_tx_descriptor *desc;
133 int do_dma;
134 int default_irq_mask;
135 int use_sdio;
136 unsigned int power_mode;
137 struct imxmmc_platform_data *pdata;
138
139 struct mmc_request *req;
140 struct mmc_command *cmd;
141 struct mmc_data *data;
142
143 unsigned int datasize;
144 unsigned int dma_dir;
145
146 u16 rev_no;
147 unsigned int cmdat;
148
149 struct clk *clk_ipg;
150 struct clk *clk_per;
151
152 int clock;
153
154 struct work_struct datawork;
155 spinlock_t lock;
156
157 int burstlen;
158 int dmareq;
159 struct dma_slave_config dma_slave_config;
160 struct imx_dma_data dma_data;
161
162 struct timer_list watchdog;
163 enum mxcmci_type devtype;
164 };
165
166 static const struct platform_device_id mxcmci_devtype[] = {
167 {
168 .name = "imx21-mmc",
169 .driver_data = IMX21_MMC,
170 }, {
171 .name = "imx31-mmc",
172 .driver_data = IMX31_MMC,
173 }, {
174 .name = "mpc512x-sdhc",
175 .driver_data = MPC512X_MMC,
176 }, {
177 /* sentinel */
178 }
179 };
180 MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
181
182 static const struct of_device_id mxcmci_of_match[] = {
183 {
184 .compatible = "fsl,imx21-mmc",
185 .data = &mxcmci_devtype[IMX21_MMC],
186 }, {
187 .compatible = "fsl,imx31-mmc",
188 .data = &mxcmci_devtype[IMX31_MMC],
189 }, {
190 .compatible = "fsl,mpc5121-sdhc",
191 .data = &mxcmci_devtype[MPC512X_MMC],
192 }, {
193 /* sentinel */
194 }
195 };
196 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
197
198 static inline int is_imx31_mmc(struct mxcmci_host *host)
199 {
200 return host->devtype == IMX31_MMC;
201 }
202
203 static inline int is_mpc512x_mmc(struct mxcmci_host *host)
204 {
205 return host->devtype == MPC512X_MMC;
206 }
207
208 static inline u32 mxcmci_readl(struct mxcmci_host *host, int reg)
209 {
210 if (IS_ENABLED(CONFIG_PPC_MPC512x))
211 return ioread32be(host->base + reg);
212 else
213 return readl(host->base + reg);
214 }
215
216 static inline void mxcmci_writel(struct mxcmci_host *host, u32 val, int reg)
217 {
218 if (IS_ENABLED(CONFIG_PPC_MPC512x))
219 iowrite32be(val, host->base + reg);
220 else
221 writel(val, host->base + reg);
222 }
223
224 static inline u16 mxcmci_readw(struct mxcmci_host *host, int reg)
225 {
226 if (IS_ENABLED(CONFIG_PPC_MPC512x))
227 return ioread32be(host->base + reg);
228 else
229 return readw(host->base + reg);
230 }
231
232 static inline void mxcmci_writew(struct mxcmci_host *host, u16 val, int reg)
233 {
234 if (IS_ENABLED(CONFIG_PPC_MPC512x))
235 iowrite32be(val, host->base + reg);
236 else
237 writew(val, host->base + reg);
238 }
239
240 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
241
242 static void mxcmci_set_power(struct mxcmci_host *host, unsigned int vdd)
243 {
244 if (!IS_ERR(host->mmc->supply.vmmc)) {
245 if (host->power_mode == MMC_POWER_UP)
246 mmc_regulator_set_ocr(host->mmc,
247 host->mmc->supply.vmmc, vdd);
248 else if (host->power_mode == MMC_POWER_OFF)
249 mmc_regulator_set_ocr(host->mmc,
250 host->mmc->supply.vmmc, 0);
251 }
252
253 if (host->pdata && host->pdata->setpower)
254 host->pdata->setpower(mmc_dev(host->mmc), vdd);
255 }
256
257 static inline int mxcmci_use_dma(struct mxcmci_host *host)
258 {
259 return host->do_dma;
260 }
261
262 static void mxcmci_softreset(struct mxcmci_host *host)
263 {
264 int i;
265
266 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
267
268 /* reset sequence */
269 mxcmci_writew(host, STR_STP_CLK_RESET, MMC_REG_STR_STP_CLK);
270 mxcmci_writew(host, STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
271 MMC_REG_STR_STP_CLK);
272
273 for (i = 0; i < 8; i++)
274 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
275
276 mxcmci_writew(host, 0xff, MMC_REG_RES_TO);
277 }
278
279 #if IS_ENABLED(CONFIG_PPC_MPC512x)
280 static inline void buffer_swap32(u32 *buf, int len)
281 {
282 int i;
283
284 for (i = 0; i < ((len + 3) / 4); i++) {
285 *buf = swab32(*buf);
286 buf++;
287 }
288 }
289
290 static void mxcmci_swap_buffers(struct mmc_data *data)
291 {
292 struct scatterlist *sg;
293 int i;
294
295 for_each_sg(data->sg, sg, data->sg_len, i) {
296 void *buf = kmap_atomic(sg_page(sg) + sg->offset);
297 buffer_swap32(buf, sg->length);
298 kunmap_atomic(buf);
299 }
300 }
301 #else
302 static inline void mxcmci_swap_buffers(struct mmc_data *data) {}
303 #endif
304
305 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
306 {
307 unsigned int nob = data->blocks;
308 unsigned int blksz = data->blksz;
309 unsigned int datasize = nob * blksz;
310 struct scatterlist *sg;
311 enum dma_transfer_direction slave_dirn;
312 int i, nents;
313
314 host->data = data;
315 data->bytes_xfered = 0;
316
317 mxcmci_writew(host, nob, MMC_REG_NOB);
318 mxcmci_writew(host, blksz, MMC_REG_BLK_LEN);
319 host->datasize = datasize;
320
321 if (!mxcmci_use_dma(host))
322 return 0;
323
324 for_each_sg(data->sg, sg, data->sg_len, i) {
325 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
326 host->do_dma = 0;
327 return 0;
328 }
329 }
330
331 if (data->flags & MMC_DATA_READ) {
332 host->dma_dir = DMA_FROM_DEVICE;
333 slave_dirn = DMA_DEV_TO_MEM;
334 } else {
335 host->dma_dir = DMA_TO_DEVICE;
336 slave_dirn = DMA_MEM_TO_DEV;
337
338 mxcmci_swap_buffers(data);
339 }
340
341 nents = dma_map_sg(host->dma->device->dev, data->sg,
342 data->sg_len, host->dma_dir);
343 if (nents != data->sg_len)
344 return -EINVAL;
345
346 host->desc = dmaengine_prep_slave_sg(host->dma,
347 data->sg, data->sg_len, slave_dirn,
348 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
349
350 if (!host->desc) {
351 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
352 host->dma_dir);
353 host->do_dma = 0;
354 return 0; /* Fall back to PIO */
355 }
356 wmb();
357
358 dmaengine_submit(host->desc);
359 dma_async_issue_pending(host->dma);
360
361 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
362
363 return 0;
364 }
365
366 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
367 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
368
369 static void mxcmci_dma_callback(void *data)
370 {
371 struct mxcmci_host *host = data;
372 u32 stat;
373
374 del_timer(&host->watchdog);
375
376 stat = mxcmci_readl(host, MMC_REG_STATUS);
377
378 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
379
380 mxcmci_data_done(host, stat);
381 }
382
383 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
384 unsigned int cmdat)
385 {
386 u32 int_cntr = host->default_irq_mask;
387 unsigned long flags;
388
389 WARN_ON(host->cmd != NULL);
390 host->cmd = cmd;
391
392 switch (mmc_resp_type(cmd)) {
393 case MMC_RSP_R1: /* short CRC, OPCODE */
394 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
395 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
396 break;
397 case MMC_RSP_R2: /* long 136 bit + CRC */
398 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
399 break;
400 case MMC_RSP_R3: /* short */
401 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
402 break;
403 case MMC_RSP_NONE:
404 break;
405 default:
406 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
407 mmc_resp_type(cmd));
408 cmd->error = -EINVAL;
409 return -EINVAL;
410 }
411
412 int_cntr = INT_END_CMD_RES_EN;
413
414 if (mxcmci_use_dma(host)) {
415 if (host->dma_dir == DMA_FROM_DEVICE) {
416 host->desc->callback = mxcmci_dma_callback;
417 host->desc->callback_param = host;
418 } else {
419 int_cntr |= INT_WRITE_OP_DONE_EN;
420 }
421 }
422
423 spin_lock_irqsave(&host->lock, flags);
424 if (host->use_sdio)
425 int_cntr |= INT_SDIO_IRQ_EN;
426 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
427 spin_unlock_irqrestore(&host->lock, flags);
428
429 mxcmci_writew(host, cmd->opcode, MMC_REG_CMD);
430 mxcmci_writel(host, cmd->arg, MMC_REG_ARG);
431 mxcmci_writew(host, cmdat, MMC_REG_CMD_DAT_CONT);
432
433 return 0;
434 }
435
436 static void mxcmci_finish_request(struct mxcmci_host *host,
437 struct mmc_request *req)
438 {
439 u32 int_cntr = host->default_irq_mask;
440 unsigned long flags;
441
442 spin_lock_irqsave(&host->lock, flags);
443 if (host->use_sdio)
444 int_cntr |= INT_SDIO_IRQ_EN;
445 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
446 spin_unlock_irqrestore(&host->lock, flags);
447
448 host->req = NULL;
449 host->cmd = NULL;
450 host->data = NULL;
451
452 mmc_request_done(host->mmc, req);
453 }
454
455 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
456 {
457 struct mmc_data *data = host->data;
458 int data_error;
459
460 if (mxcmci_use_dma(host)) {
461 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
462 host->dma_dir);
463 mxcmci_swap_buffers(data);
464 }
465
466 if (stat & STATUS_ERR_MASK) {
467 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
468 stat);
469 if (stat & STATUS_CRC_READ_ERR) {
470 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
471 data->error = -EILSEQ;
472 } else if (stat & STATUS_CRC_WRITE_ERR) {
473 u32 err_code = (stat >> 9) & 0x3;
474 if (err_code == 2) { /* No CRC response */
475 dev_err(mmc_dev(host->mmc),
476 "%s: No CRC -ETIMEDOUT\n", __func__);
477 data->error = -ETIMEDOUT;
478 } else {
479 dev_err(mmc_dev(host->mmc),
480 "%s: -EILSEQ\n", __func__);
481 data->error = -EILSEQ;
482 }
483 } else if (stat & STATUS_TIME_OUT_READ) {
484 dev_err(mmc_dev(host->mmc),
485 "%s: read -ETIMEDOUT\n", __func__);
486 data->error = -ETIMEDOUT;
487 } else {
488 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
489 data->error = -EIO;
490 }
491 } else {
492 data->bytes_xfered = host->datasize;
493 }
494
495 data_error = data->error;
496
497 host->data = NULL;
498
499 return data_error;
500 }
501
502 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
503 {
504 struct mmc_command *cmd = host->cmd;
505 int i;
506 u32 a, b, c;
507
508 if (!cmd)
509 return;
510
511 if (stat & STATUS_TIME_OUT_RESP) {
512 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
513 cmd->error = -ETIMEDOUT;
514 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
515 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
516 cmd->error = -EILSEQ;
517 }
518
519 if (cmd->flags & MMC_RSP_PRESENT) {
520 if (cmd->flags & MMC_RSP_136) {
521 for (i = 0; i < 4; i++) {
522 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
523 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
524 cmd->resp[i] = a << 16 | b;
525 }
526 } else {
527 a = mxcmci_readw(host, MMC_REG_RES_FIFO);
528 b = mxcmci_readw(host, MMC_REG_RES_FIFO);
529 c = mxcmci_readw(host, MMC_REG_RES_FIFO);
530 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
531 }
532 }
533 }
534
535 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
536 {
537 u32 stat;
538 unsigned long timeout = jiffies + HZ;
539
540 do {
541 stat = mxcmci_readl(host, MMC_REG_STATUS);
542 if (stat & STATUS_ERR_MASK)
543 return stat;
544 if (time_after(jiffies, timeout)) {
545 mxcmci_softreset(host);
546 mxcmci_set_clk_rate(host, host->clock);
547 return STATUS_TIME_OUT_READ;
548 }
549 if (stat & mask)
550 return 0;
551 cpu_relax();
552 } while (1);
553 }
554
555 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
556 {
557 unsigned int stat;
558 u32 *buf = _buf;
559
560 while (bytes > 3) {
561 stat = mxcmci_poll_status(host,
562 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
563 if (stat)
564 return stat;
565 *buf++ = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
566 bytes -= 4;
567 }
568
569 if (bytes) {
570 u8 *b = (u8 *)buf;
571 u32 tmp;
572
573 stat = mxcmci_poll_status(host,
574 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
575 if (stat)
576 return stat;
577 tmp = cpu_to_le32(mxcmci_readl(host, MMC_REG_BUFFER_ACCESS));
578 memcpy(b, &tmp, bytes);
579 }
580
581 return 0;
582 }
583
584 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
585 {
586 unsigned int stat;
587 u32 *buf = _buf;
588
589 while (bytes > 3) {
590 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
591 if (stat)
592 return stat;
593 mxcmci_writel(host, cpu_to_le32(*buf++), MMC_REG_BUFFER_ACCESS);
594 bytes -= 4;
595 }
596
597 if (bytes) {
598 u8 *b = (u8 *)buf;
599 u32 tmp;
600
601 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
602 if (stat)
603 return stat;
604
605 memcpy(&tmp, b, bytes);
606 mxcmci_writel(host, cpu_to_le32(tmp), MMC_REG_BUFFER_ACCESS);
607 }
608
609 return mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
610 }
611
612 static int mxcmci_transfer_data(struct mxcmci_host *host)
613 {
614 struct mmc_data *data = host->req->data;
615 struct scatterlist *sg;
616 void *buf;
617 int stat, i;
618
619 host->data = data;
620 host->datasize = 0;
621
622 if (data->flags & MMC_DATA_READ) {
623 for_each_sg(data->sg, sg, data->sg_len, i) {
624 buf = kmap_atomic(sg_page(sg) + sg->offset);
625 stat = mxcmci_pull(host, buf, sg->length);
626 kunmap(buf);
627 if (stat)
628 return stat;
629 host->datasize += sg->length;
630 }
631 } else {
632 for_each_sg(data->sg, sg, data->sg_len, i) {
633 buf = kmap_atomic(sg_page(sg) + sg->offset);
634 stat = mxcmci_push(host, buf, sg->length);
635 kunmap(buf);
636 if (stat)
637 return stat;
638 host->datasize += sg->length;
639 }
640 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
641 if (stat)
642 return stat;
643 }
644 return 0;
645 }
646
647 static void mxcmci_datawork(struct work_struct *work)
648 {
649 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
650 datawork);
651 int datastat = mxcmci_transfer_data(host);
652
653 mxcmci_writel(host, STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
654 MMC_REG_STATUS);
655 mxcmci_finish_data(host, datastat);
656
657 if (host->req->stop) {
658 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
659 mxcmci_finish_request(host, host->req);
660 return;
661 }
662 } else {
663 mxcmci_finish_request(host, host->req);
664 }
665 }
666
667 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
668 {
669 struct mmc_request *req;
670 int data_error;
671 unsigned long flags;
672
673 spin_lock_irqsave(&host->lock, flags);
674
675 if (!host->data) {
676 spin_unlock_irqrestore(&host->lock, flags);
677 return;
678 }
679
680 if (!host->req) {
681 spin_unlock_irqrestore(&host->lock, flags);
682 return;
683 }
684
685 req = host->req;
686 if (!req->stop)
687 host->req = NULL; /* we will handle finish req below */
688
689 data_error = mxcmci_finish_data(host, stat);
690
691 spin_unlock_irqrestore(&host->lock, flags);
692
693 if (data_error)
694 return;
695
696 mxcmci_read_response(host, stat);
697 host->cmd = NULL;
698
699 if (req->stop) {
700 if (mxcmci_start_cmd(host, req->stop, 0)) {
701 mxcmci_finish_request(host, req);
702 return;
703 }
704 } else {
705 mxcmci_finish_request(host, req);
706 }
707 }
708
709 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
710 {
711 mxcmci_read_response(host, stat);
712 host->cmd = NULL;
713
714 if (!host->data && host->req) {
715 mxcmci_finish_request(host, host->req);
716 return;
717 }
718
719 /* For the DMA case the DMA engine handles the data transfer
720 * automatically. For non DMA we have to do it ourselves.
721 * Don't do it in interrupt context though.
722 */
723 if (!mxcmci_use_dma(host) && host->data)
724 schedule_work(&host->datawork);
725
726 }
727
728 static irqreturn_t mxcmci_irq(int irq, void *devid)
729 {
730 struct mxcmci_host *host = devid;
731 bool sdio_irq;
732 u32 stat;
733
734 stat = mxcmci_readl(host, MMC_REG_STATUS);
735 mxcmci_writel(host,
736 stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
737 STATUS_WRITE_OP_DONE),
738 MMC_REG_STATUS);
739
740 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
741
742 spin_lock(&host->lock);
743 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
744 spin_unlock(&host->lock);
745
746 if (mxcmci_use_dma(host) && (stat & (STATUS_WRITE_OP_DONE)))
747 mxcmci_writel(host, STATUS_WRITE_OP_DONE, MMC_REG_STATUS);
748
749 if (sdio_irq) {
750 mxcmci_writel(host, STATUS_SDIO_INT_ACTIVE, MMC_REG_STATUS);
751 mmc_signal_sdio_irq(host->mmc);
752 }
753
754 if (stat & STATUS_END_CMD_RESP)
755 mxcmci_cmd_done(host, stat);
756
757 if (mxcmci_use_dma(host) && (stat & STATUS_WRITE_OP_DONE)) {
758 del_timer(&host->watchdog);
759 mxcmci_data_done(host, stat);
760 }
761
762 if (host->default_irq_mask &&
763 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
764 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
765
766 return IRQ_HANDLED;
767 }
768
769 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
770 {
771 struct mxcmci_host *host = mmc_priv(mmc);
772 unsigned int cmdat = host->cmdat;
773 int error;
774
775 WARN_ON(host->req != NULL);
776
777 host->req = req;
778 host->cmdat &= ~CMD_DAT_CONT_INIT;
779
780 if (host->dma)
781 host->do_dma = 1;
782
783 if (req->data) {
784 error = mxcmci_setup_data(host, req->data);
785 if (error) {
786 req->cmd->error = error;
787 goto out;
788 }
789
790
791 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
792
793 if (req->data->flags & MMC_DATA_WRITE)
794 cmdat |= CMD_DAT_CONT_WRITE;
795 }
796
797 error = mxcmci_start_cmd(host, req->cmd, cmdat);
798
799 out:
800 if (error)
801 mxcmci_finish_request(host, req);
802 }
803
804 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
805 {
806 unsigned int divider;
807 int prescaler = 0;
808 unsigned int clk_in = clk_get_rate(host->clk_per);
809
810 while (prescaler <= 0x800) {
811 for (divider = 1; divider <= 0xF; divider++) {
812 int x;
813
814 x = (clk_in / (divider + 1));
815
816 if (prescaler)
817 x /= (prescaler * 2);
818
819 if (x <= clk_ios)
820 break;
821 }
822 if (divider < 0x10)
823 break;
824
825 if (prescaler == 0)
826 prescaler = 1;
827 else
828 prescaler <<= 1;
829 }
830
831 mxcmci_writew(host, (prescaler << 4) | divider, MMC_REG_CLK_RATE);
832
833 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
834 prescaler, divider, clk_in, clk_ios);
835 }
836
837 static int mxcmci_setup_dma(struct mmc_host *mmc)
838 {
839 struct mxcmci_host *host = mmc_priv(mmc);
840 struct dma_slave_config *config = &host->dma_slave_config;
841
842 config->dst_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
843 config->src_addr = host->phys_base + MMC_REG_BUFFER_ACCESS;
844 config->dst_addr_width = 4;
845 config->src_addr_width = 4;
846 config->dst_maxburst = host->burstlen;
847 config->src_maxburst = host->burstlen;
848 config->device_fc = false;
849
850 return dmaengine_slave_config(host->dma, config);
851 }
852
853 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
854 {
855 struct mxcmci_host *host = mmc_priv(mmc);
856 int burstlen, ret;
857
858 /*
859 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
860 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
861 */
862 if (ios->bus_width == MMC_BUS_WIDTH_4)
863 burstlen = 16;
864 else
865 burstlen = 4;
866
867 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
868 host->burstlen = burstlen;
869 ret = mxcmci_setup_dma(mmc);
870 if (ret) {
871 dev_err(mmc_dev(host->mmc),
872 "failed to config DMA channel. Falling back to PIO\n");
873 dma_release_channel(host->dma);
874 host->do_dma = 0;
875 host->dma = NULL;
876 }
877 }
878
879 if (ios->bus_width == MMC_BUS_WIDTH_4)
880 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
881 else
882 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
883
884 if (host->power_mode != ios->power_mode) {
885 host->power_mode = ios->power_mode;
886 mxcmci_set_power(host, ios->vdd);
887
888 if (ios->power_mode == MMC_POWER_ON)
889 host->cmdat |= CMD_DAT_CONT_INIT;
890 }
891
892 if (ios->clock) {
893 mxcmci_set_clk_rate(host, ios->clock);
894 mxcmci_writew(host, STR_STP_CLK_START_CLK, MMC_REG_STR_STP_CLK);
895 } else {
896 mxcmci_writew(host, STR_STP_CLK_STOP_CLK, MMC_REG_STR_STP_CLK);
897 }
898
899 host->clock = ios->clock;
900 }
901
902 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
903 {
904 struct mmc_host *mmc = data;
905
906 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
907
908 mmc_detect_change(mmc, msecs_to_jiffies(250));
909 return IRQ_HANDLED;
910 }
911
912 static int mxcmci_get_ro(struct mmc_host *mmc)
913 {
914 struct mxcmci_host *host = mmc_priv(mmc);
915
916 if (host->pdata && host->pdata->get_ro)
917 return !!host->pdata->get_ro(mmc_dev(mmc));
918 /*
919 * If board doesn't support read only detection (no mmc_gpio
920 * context or gpio is invalid), then let the mmc core decide
921 * what to do.
922 */
923 return mmc_gpio_get_ro(mmc);
924 }
925
926 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
927 {
928 struct mxcmci_host *host = mmc_priv(mmc);
929 unsigned long flags;
930 u32 int_cntr;
931
932 spin_lock_irqsave(&host->lock, flags);
933 host->use_sdio = enable;
934 int_cntr = mxcmci_readl(host, MMC_REG_INT_CNTR);
935
936 if (enable)
937 int_cntr |= INT_SDIO_IRQ_EN;
938 else
939 int_cntr &= ~INT_SDIO_IRQ_EN;
940
941 mxcmci_writel(host, int_cntr, MMC_REG_INT_CNTR);
942 spin_unlock_irqrestore(&host->lock, flags);
943 }
944
945 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
946 {
947 struct mxcmci_host *mxcmci = mmc_priv(host);
948
949 /*
950 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
951 * multi-block transfers when connected SDIO peripheral doesn't
952 * drive the BUSY line as required by the specs.
953 * One way to prevent this is to only allow 1-bit transfers.
954 */
955
956 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
957 host->caps &= ~MMC_CAP_4_BIT_DATA;
958 else
959 host->caps |= MMC_CAP_4_BIT_DATA;
960 }
961
962 static bool filter(struct dma_chan *chan, void *param)
963 {
964 struct mxcmci_host *host = param;
965
966 if (!imx_dma_is_general_purpose(chan))
967 return false;
968
969 chan->private = &host->dma_data;
970
971 return true;
972 }
973
974 static void mxcmci_watchdog(struct timer_list *t)
975 {
976 struct mxcmci_host *host = from_timer(host, t, watchdog);
977 struct mmc_request *req = host->req;
978 unsigned int stat = mxcmci_readl(host, MMC_REG_STATUS);
979
980 if (host->dma_dir == DMA_FROM_DEVICE) {
981 dmaengine_terminate_all(host->dma);
982 dev_err(mmc_dev(host->mmc),
983 "%s: read time out (status = 0x%08x)\n",
984 __func__, stat);
985 } else {
986 dev_err(mmc_dev(host->mmc),
987 "%s: write time out (status = 0x%08x)\n",
988 __func__, stat);
989 mxcmci_softreset(host);
990 }
991
992 /* Mark transfer as erroneus and inform the upper layers */
993
994 if (host->data)
995 host->data->error = -ETIMEDOUT;
996 host->req = NULL;
997 host->cmd = NULL;
998 host->data = NULL;
999 mmc_request_done(host->mmc, req);
1000 }
1001
1002 static const struct mmc_host_ops mxcmci_ops = {
1003 .request = mxcmci_request,
1004 .set_ios = mxcmci_set_ios,
1005 .get_ro = mxcmci_get_ro,
1006 .enable_sdio_irq = mxcmci_enable_sdio_irq,
1007 .init_card = mxcmci_init_card,
1008 };
1009
1010 static int mxcmci_probe(struct platform_device *pdev)
1011 {
1012 struct mmc_host *mmc;
1013 struct mxcmci_host *host;
1014 struct resource *res;
1015 int ret = 0, irq;
1016 bool dat3_card_detect = false;
1017 dma_cap_mask_t mask;
1018 const struct of_device_id *of_id;
1019 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
1020
1021 pr_info("i.MX/MPC512x SDHC driver\n");
1022
1023 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
1024
1025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1026 irq = platform_get_irq(pdev, 0);
1027 if (irq < 0) {
1028 dev_err(&pdev->dev, "failed to get IRQ: %d\n", irq);
1029 return irq;
1030 }
1031
1032 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev);
1033 if (!mmc)
1034 return -ENOMEM;
1035
1036 host = mmc_priv(mmc);
1037
1038 host->base = devm_ioremap_resource(&pdev->dev, res);
1039 if (IS_ERR(host->base)) {
1040 ret = PTR_ERR(host->base);
1041 goto out_free;
1042 }
1043
1044 host->phys_base = res->start;
1045
1046 ret = mmc_of_parse(mmc);
1047 if (ret)
1048 goto out_free;
1049 mmc->ops = &mxcmci_ops;
1050
1051 /* For devicetree parsing, the bus width is read from devicetree */
1052 if (pdata)
1053 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1054 else
1055 mmc->caps |= MMC_CAP_SDIO_IRQ;
1056
1057 /* MMC core transfer sizes tunable parameters */
1058 mmc->max_blk_size = 2048;
1059 mmc->max_blk_count = 65535;
1060 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1061 mmc->max_seg_size = mmc->max_req_size;
1062
1063 if (of_id) {
1064 const struct platform_device_id *id_entry = of_id->data;
1065 host->devtype = id_entry->driver_data;
1066 } else {
1067 host->devtype = pdev->id_entry->driver_data;
1068 }
1069
1070 /* adjust max_segs after devtype detection */
1071 if (!is_mpc512x_mmc(host))
1072 mmc->max_segs = 64;
1073
1074 host->mmc = mmc;
1075 host->pdata = pdata;
1076 spin_lock_init(&host->lock);
1077
1078 if (pdata)
1079 dat3_card_detect = pdata->dat3_card_detect;
1080 else if (mmc_card_is_removable(mmc)
1081 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1082 dat3_card_detect = true;
1083
1084 ret = mmc_regulator_get_supply(mmc);
1085 if (ret)
1086 goto out_free;
1087
1088 if (!mmc->ocr_avail) {
1089 if (pdata && pdata->ocr_avail)
1090 mmc->ocr_avail = pdata->ocr_avail;
1091 else
1092 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1093 }
1094
1095 if (dat3_card_detect)
1096 host->default_irq_mask =
1097 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1098 else
1099 host->default_irq_mask = 0;
1100
1101 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1102 if (IS_ERR(host->clk_ipg)) {
1103 ret = PTR_ERR(host->clk_ipg);
1104 goto out_free;
1105 }
1106
1107 host->clk_per = devm_clk_get(&pdev->dev, "per");
1108 if (IS_ERR(host->clk_per)) {
1109 ret = PTR_ERR(host->clk_per);
1110 goto out_free;
1111 }
1112
1113 ret = clk_prepare_enable(host->clk_per);
1114 if (ret)
1115 goto out_free;
1116
1117 ret = clk_prepare_enable(host->clk_ipg);
1118 if (ret)
1119 goto out_clk_per_put;
1120
1121 mxcmci_softreset(host);
1122
1123 host->rev_no = mxcmci_readw(host, MMC_REG_REV_NO);
1124 if (host->rev_no != 0x400) {
1125 ret = -ENODEV;
1126 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1127 host->rev_no);
1128 goto out_clk_put;
1129 }
1130
1131 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1132 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1133
1134 /* recommended in data sheet */
1135 mxcmci_writew(host, 0x2db4, MMC_REG_READ_TO);
1136
1137 mxcmci_writel(host, host->default_irq_mask, MMC_REG_INT_CNTR);
1138
1139 if (!host->pdata) {
1140 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1141 } else {
1142 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1143 if (res) {
1144 host->dmareq = res->start;
1145 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1146 host->dma_data.priority = DMA_PRIO_LOW;
1147 host->dma_data.dma_request = host->dmareq;
1148 dma_cap_zero(mask);
1149 dma_cap_set(DMA_SLAVE, mask);
1150 host->dma = dma_request_channel(mask, filter, host);
1151 }
1152 }
1153 if (host->dma)
1154 mmc->max_seg_size = dma_get_max_seg_size(
1155 host->dma->device->dev);
1156 else
1157 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1158
1159 INIT_WORK(&host->datawork, mxcmci_datawork);
1160
1161 ret = devm_request_irq(&pdev->dev, irq, mxcmci_irq, 0,
1162 dev_name(&pdev->dev), host);
1163 if (ret)
1164 goto out_free_dma;
1165
1166 platform_set_drvdata(pdev, mmc);
1167
1168 if (host->pdata && host->pdata->init) {
1169 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1170 host->mmc);
1171 if (ret)
1172 goto out_free_dma;
1173 }
1174
1175 timer_setup(&host->watchdog, mxcmci_watchdog, 0);
1176
1177 mmc_add_host(mmc);
1178
1179 return 0;
1180
1181 out_free_dma:
1182 if (host->dma)
1183 dma_release_channel(host->dma);
1184
1185 out_clk_put:
1186 clk_disable_unprepare(host->clk_ipg);
1187 out_clk_per_put:
1188 clk_disable_unprepare(host->clk_per);
1189
1190 out_free:
1191 mmc_free_host(mmc);
1192
1193 return ret;
1194 }
1195
1196 static int mxcmci_remove(struct platform_device *pdev)
1197 {
1198 struct mmc_host *mmc = platform_get_drvdata(pdev);
1199 struct mxcmci_host *host = mmc_priv(mmc);
1200
1201 mmc_remove_host(mmc);
1202
1203 if (host->pdata && host->pdata->exit)
1204 host->pdata->exit(&pdev->dev, mmc);
1205
1206 if (host->dma)
1207 dma_release_channel(host->dma);
1208
1209 clk_disable_unprepare(host->clk_per);
1210 clk_disable_unprepare(host->clk_ipg);
1211
1212 mmc_free_host(mmc);
1213
1214 return 0;
1215 }
1216
1217 #ifdef CONFIG_PM_SLEEP
1218 static int mxcmci_suspend(struct device *dev)
1219 {
1220 struct mmc_host *mmc = dev_get_drvdata(dev);
1221 struct mxcmci_host *host = mmc_priv(mmc);
1222
1223 clk_disable_unprepare(host->clk_per);
1224 clk_disable_unprepare(host->clk_ipg);
1225 return 0;
1226 }
1227
1228 static int mxcmci_resume(struct device *dev)
1229 {
1230 struct mmc_host *mmc = dev_get_drvdata(dev);
1231 struct mxcmci_host *host = mmc_priv(mmc);
1232 int ret;
1233
1234 ret = clk_prepare_enable(host->clk_per);
1235 if (ret)
1236 return ret;
1237
1238 ret = clk_prepare_enable(host->clk_ipg);
1239 if (ret)
1240 clk_disable_unprepare(host->clk_per);
1241
1242 return ret;
1243 }
1244 #endif
1245
1246 static SIMPLE_DEV_PM_OPS(mxcmci_pm_ops, mxcmci_suspend, mxcmci_resume);
1247
1248 static struct platform_driver mxcmci_driver = {
1249 .probe = mxcmci_probe,
1250 .remove = mxcmci_remove,
1251 .id_table = mxcmci_devtype,
1252 .driver = {
1253 .name = DRIVER_NAME,
1254 .pm = &mxcmci_pm_ops,
1255 .of_match_table = mxcmci_of_match,
1256 }
1257 };
1258
1259 module_platform_driver(mxcmci_driver);
1260
1261 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1262 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1263 MODULE_LICENSE("GPL");
1264 MODULE_ALIAS("platform:mxc-mmc");
Linux with added FPC-III support