drivers/mmc/host/renesas_sdhi_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Renesas SDHI
   4  *
   5  * Copyright (C) 2015-17 Renesas Electronics Corporation
   6  * Copyright (C) 2016-17 Sang Engineering, Wolfram Sang
   7  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   8  * Copyright (C) 2009 Magnus Damm
   9  *
  10  * Based on "Compaq ASIC3 support":
  11  *
  12  * Copyright 2001 Compaq Computer Corporation.
  13  * Copyright 2004-2005 Phil Blundell
  14  * Copyright 2007-2008 OpenedHand Ltd.
  15  *
  16  * Authors: Phil Blundell <pb@handhelds.org>,
  17  *          Samuel Ortiz <sameo@openedhand.com>
  18  *
  19  */
  20
  21 #include <linux/kernel.h>
  22 #include <linux/clk.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/of_device.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/mmc/host.h>
  28 #include <linux/mmc/slot-gpio.h>
  29 #include <linux/mfd/tmio.h>
  30 #include <linux/sh_dma.h>
  31 #include <linux/delay.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/pinctrl/pinctrl-state.h>
  34 #include <linux/regulator/consumer.h>
  35
  36 #include "renesas_sdhi.h"
  37 #include "tmio_mmc.h"
  38
  39 #define HOST_MODE               0xe4
  40
  41 #define SDHI_VER_GEN2_SDR50     0x490c
  42 #define SDHI_VER_RZ_A1          0x820b
  43 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */
  44 #define SDHI_VER_GEN2_SDR104    0xcb0d
  45 #define SDHI_VER_GEN3_SD        0xcc10
  46 #define SDHI_VER_GEN3_SDMMC     0xcd10
  47
  48 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width)
  49 {
  50         u32 val;
  51
  52         /*
  53          * see also
  54          *      renesas_sdhi_of_data :: dma_buswidth
  55          */
  56         switch (sd_ctrl_read16(host, CTL_VERSION)) {
  57         case SDHI_VER_GEN2_SDR50:
  58                 val = (width == 32) ? 0x0001 : 0x0000;
  59                 break;
  60         case SDHI_VER_GEN2_SDR104:
  61                 val = (width == 32) ? 0x0000 : 0x0001;
  62                 break;
  63         case SDHI_VER_GEN3_SD:
  64         case SDHI_VER_GEN3_SDMMC:
  65                 if (width == 64)
  66                         val = 0x0000;
  67                 else if (width == 32)
  68                         val = 0x0101;
  69                 else
  70                         val = 0x0001;
  71                 break;
  72         default:
  73                 /* nothing to do */
  74                 return;
  75         }
  76
  77         sd_ctrl_write16(host, HOST_MODE, val);
  78 }
  79
  80 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host)
  81 {
  82         struct mmc_host *mmc = host->mmc;
  83         struct renesas_sdhi *priv = host_to_priv(host);
  84         int ret = clk_prepare_enable(priv->clk);
  85
  86         if (ret < 0)
  87                 return ret;
  88
  89         ret = clk_prepare_enable(priv->clk_cd);
  90         if (ret < 0) {
  91                 clk_disable_unprepare(priv->clk);
  92                 return ret;
  93         }
  94
  95         /*
  96          * The clock driver may not know what maximum frequency
  97          * actually works, so it should be set with the max-frequency
  98          * property which will already have been read to f_max.  If it
  99          * was missing, assume the current frequency is the maximum.
 100          */
 101         if (!mmc->f_max)
 102                 mmc->f_max = clk_get_rate(priv->clk);
 103
 104         /*
 105          * Minimum frequency is the minimum input clock frequency
 106          * divided by our maximum divider.
 107          */
 108         mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L);
 109
 110         /* enable 16bit data access on SDBUF as default */
 111         renesas_sdhi_sdbuf_width(host, 16);
 112
 113         return 0;
 114 }
 115
 116 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host,
 117                                             unsigned int new_clock)
 118 {
 119         struct renesas_sdhi *priv = host_to_priv(host);
 120         unsigned int freq, diff, best_freq = 0, diff_min = ~0;
 121         int i, ret;
 122
 123         /* tested only on R-Car Gen2+ currently; may work for others */
 124         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 125                 return clk_get_rate(priv->clk);
 126
 127         /*
 128          * We want the bus clock to be as close as possible to, but no
 129          * greater than, new_clock.  As we can divide by 1 << i for
 130          * any i in [0, 9] we want the input clock to be as close as
 131          * possible, but no greater than, new_clock << i.
 132          */
 133         for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) {
 134                 freq = clk_round_rate(priv->clk, new_clock << i);
 135                 if (freq > (new_clock << i)) {
 136                         /* Too fast; look for a slightly slower option */
 137                         freq = clk_round_rate(priv->clk,
 138                                               (new_clock << i) / 4 * 3);
 139                         if (freq > (new_clock << i))
 140                                 continue;
 141                 }
 142
 143                 diff = new_clock - (freq >> i);
 144                 if (diff <= diff_min) {
 145                         best_freq = freq;
 146                         diff_min = diff;
 147                 }
 148         }
 149
 150         ret = clk_set_rate(priv->clk, best_freq);
 151
 152         return ret == 0 ? best_freq : clk_get_rate(priv->clk);
 153 }
 154
 155 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host,
 156                                    unsigned int new_clock)
 157 {
 158         u32 clk = 0, clock;
 159
 160         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 161                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 162
 163         if (new_clock == 0)
 164                 goto out;
 165
 166         /*
 167          * Both HS400 and HS200/SD104 set 200MHz, but some devices need to
 168          * set 400MHz to distinguish the CPG settings in HS400.
 169          */
 170         if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400 &&
 171             host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400 &&
 172             new_clock == 200000000)
 173                 new_clock = 400000000;
 174
 175         clock = renesas_sdhi_clk_update(host, new_clock) / 512;
 176
 177         for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1)
 178                 clock <<= 1;
 179
 180         /* 1/1 clock is option */
 181         if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) {
 182                 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400))
 183                         clk |= 0xff;
 184                 else
 185                         clk &= ~0xff;
 186         }
 187
 188         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK);
 189         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 190                 usleep_range(10000, 11000);
 191
 192         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 193                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 194
 195 out:
 196         /* HW engineers overrode docs: no sleep needed on R-Car2+ */
 197         if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2))
 198                 usleep_range(10000, 11000);
 199 }
 200
 201 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host)
 202 {
 203         struct renesas_sdhi *priv = host_to_priv(host);
 204
 205         clk_disable_unprepare(priv->clk);
 206         clk_disable_unprepare(priv->clk_cd);
 207 }
 208
 209 static int renesas_sdhi_card_busy(struct mmc_host *mmc)
 210 {
 211         struct tmio_mmc_host *host = mmc_priv(mmc);
 212
 213         return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
 214                  TMIO_STAT_DAT0);
 215 }
 216
 217 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc,
 218                                                     struct mmc_ios *ios)
 219 {
 220         struct tmio_mmc_host *host = mmc_priv(mmc);
 221         struct renesas_sdhi *priv = host_to_priv(host);
 222         struct pinctrl_state *pin_state;
 223         int ret;
 224
 225         switch (ios->signal_voltage) {
 226         case MMC_SIGNAL_VOLTAGE_330:
 227                 pin_state = priv->pins_default;
 228                 break;
 229         case MMC_SIGNAL_VOLTAGE_180:
 230                 pin_state = priv->pins_uhs;
 231                 break;
 232         default:
 233                 return -EINVAL;
 234         }
 235
 236         /*
 237          * If anything is missing, assume signal voltage is fixed at
 238          * 3.3V and succeed/fail accordingly.
 239          */
 240         if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state))
 241                 return ios->signal_voltage ==
 242                         MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL;
 243
 244         ret = mmc_regulator_set_vqmmc(host->mmc, ios);
 245         if (ret)
 246                 return ret;
 247
 248         return pinctrl_select_state(priv->pinctrl, pin_state);
 249 }
 250
 251 /* SCC registers */
 252 #define SH_MOBILE_SDHI_SCC_DTCNTL       0x000
 253 #define SH_MOBILE_SDHI_SCC_TAPSET       0x002
 254 #define SH_MOBILE_SDHI_SCC_DT2FF        0x004
 255 #define SH_MOBILE_SDHI_SCC_CKSEL        0x006
 256 #define SH_MOBILE_SDHI_SCC_RVSCNTL      0x008
 257 #define SH_MOBILE_SDHI_SCC_RVSREQ       0x00A
 258 #define SH_MOBILE_SDHI_SCC_TMPPORT2     0x00E
 259
 260 /* Definitions for values the SH_MOBILE_SDHI_SCC_DTCNTL register */
 261 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN         BIT(0)
 262 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT  16
 263 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK   0xff
 264
 265 /* Definitions for values the SH_MOBILE_SDHI_SCC_CKSEL register */
 266 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL          BIT(0)
 267 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSCNTL register */
 268 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN        BIT(0)
 269 /* Definitions for values the SH_MOBILE_SDHI_SCC_RVSREQ register */
 270 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR        BIT(2)
 271 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT2 register */
 272 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL   BIT(4)
 273 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN     BIT(31)
 274
 275 static inline u32 sd_scc_read32(struct tmio_mmc_host *host,
 276                                 struct renesas_sdhi *priv, int addr)
 277 {
 278         return readl(priv->scc_ctl + (addr << host->bus_shift));
 279 }
 280
 281 static inline void sd_scc_write32(struct tmio_mmc_host *host,
 282                                   struct renesas_sdhi *priv,
 283                                   int addr, u32 val)
 284 {
 285         writel(val, priv->scc_ctl + (addr << host->bus_shift));
 286 }
 287
 288 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host)
 289 {
 290         struct renesas_sdhi *priv;
 291
 292         priv = host_to_priv(host);
 293
 294         /* Initialize SCC */
 295         sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0);
 296
 297         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 298                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 299
 300         /* set sampling clock selection range */
 301         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 302                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 303                        0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 304
 305         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 306                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 307                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 308
 309         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 310                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 311                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 312
 313         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos);
 314
 315         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 316                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 317
 318         /* Read TAPNUM */
 319         return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >>
 320                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) &
 321                 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK;
 322 }
 323
 324 static void renesas_sdhi_prepare_tuning(struct tmio_mmc_host *host,
 325                                         unsigned long tap)
 326 {
 327         struct renesas_sdhi *priv = host_to_priv(host);
 328
 329         /* Set sampling clock position */
 330         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, tap);
 331 }
 332
 333 static void renesas_sdhi_hs400_complete(struct tmio_mmc_host *host)
 334 {
 335         struct renesas_sdhi *priv = host_to_priv(host);
 336
 337         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 338                 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 339
 340         /* Set HS400 mode */
 341         sd_ctrl_write16(host, CTL_SDIF_MODE, 0x0001 |
 342                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 343         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 344                        (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 345                         SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) |
 346                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 347
 348         /* Set the sampling clock selection range of HS400 mode */
 349         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 350                        SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN |
 351                        0x4 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT);
 352
 353
 354         if (host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400)
 355                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET,
 356                                host->tap_set / 2);
 357
 358         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 359                        SH_MOBILE_SDHI_SCC_CKSEL_DTSEL |
 360                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL));
 361
 362         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 363                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 364 }
 365
 366 static void renesas_sdhi_reset_scc(struct tmio_mmc_host *host,
 367                                    struct renesas_sdhi *priv)
 368 {
 369         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 370                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 371
 372         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL,
 373                        ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL &
 374                        sd_scc_read32(host, priv,
 375                                      SH_MOBILE_SDHI_SCC_CKSEL));
 376 }
 377
 378 static void renesas_sdhi_disable_scc(struct tmio_mmc_host *host)
 379 {
 380         struct renesas_sdhi *priv = host_to_priv(host);
 381
 382         renesas_sdhi_reset_scc(host, priv);
 383
 384         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL,
 385                        ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN &
 386                        sd_scc_read32(host, priv,
 387                                      SH_MOBILE_SDHI_SCC_DTCNTL));
 388
 389         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 390                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 391 }
 392
 393 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host,
 394                                           struct renesas_sdhi *priv)
 395 {
 396         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN &
 397                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 398
 399         /* Reset HS400 mode */
 400         sd_ctrl_write16(host, CTL_SDIF_MODE, ~0x0001 &
 401                         sd_ctrl_read16(host, CTL_SDIF_MODE));
 402         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2,
 403                        ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN |
 404                          SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) &
 405                         sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2));
 406
 407         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 408                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 409 }
 410
 411 static void renesas_sdhi_prepare_hs400_tuning(struct tmio_mmc_host *host)
 412 {
 413         renesas_sdhi_reset_hs400_mode(host, host_to_priv(host));
 414 }
 415
 416 #define SH_MOBILE_SDHI_MAX_TAP 3
 417
 418 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host)
 419 {
 420         struct renesas_sdhi *priv = host_to_priv(host);
 421         unsigned long tap_cnt;  /* counter of tuning success */
 422         unsigned long tap_start;/* start position of tuning success */
 423         unsigned long tap_end;  /* end position of tuning success */
 424         unsigned long ntap;     /* temporary counter of tuning success */
 425         unsigned long i;
 426
 427         /* Clear SCC_RVSREQ */
 428         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 429
 430         /*
 431          * When tuning CMD19 is issued twice for each tap, merge the
 432          * result requiring the tap to be good in both runs before
 433          * considering it for tuning selection.
 434          */
 435         for (i = 0; i < host->tap_num * 2; i++) {
 436                 int offset = host->tap_num * (i < host->tap_num ? 1 : -1);
 437
 438                 if (!test_bit(i, host->taps))
 439                         clear_bit(i + offset, host->taps);
 440         }
 441
 442         /*
 443          * Find the longest consecutive run of successful probes.  If that
 444          * is more than SH_MOBILE_SDHI_MAX_TAP probes long then use the
 445          * center index as the tap.
 446          */
 447         tap_cnt = 0;
 448         ntap = 0;
 449         tap_start = 0;
 450         tap_end = 0;
 451         for (i = 0; i < host->tap_num * 2; i++) {
 452                 if (test_bit(i, host->taps)) {
 453                         ntap++;
 454                 } else {
 455                         if (ntap > tap_cnt) {
 456                                 tap_start = i - ntap;
 457                                 tap_end = i - 1;
 458                                 tap_cnt = ntap;
 459                         }
 460                         ntap = 0;
 461                 }
 462         }
 463
 464         if (ntap > tap_cnt) {
 465                 tap_start = i - ntap;
 466                 tap_end = i - 1;
 467                 tap_cnt = ntap;
 468         }
 469
 470         if (tap_cnt >= SH_MOBILE_SDHI_MAX_TAP)
 471                 host->tap_set = (tap_start + tap_end) / 2 % host->tap_num;
 472         else
 473                 return -EIO;
 474
 475         /* Set SCC */
 476         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, host->tap_set);
 477
 478         /* Enable auto re-tuning */
 479         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 480                        SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN |
 481                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 482
 483         return 0;
 484 }
 485
 486 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host)
 487 {
 488         struct renesas_sdhi *priv = host_to_priv(host);
 489         bool use_4tap = host->pdata->flags & TMIO_MMC_HAVE_4TAP_HS400;
 490
 491         /*
 492          * Skip checking SCC errors when running on 4 taps in HS400 mode as
 493          * any retuning would still result in the same 4 taps being used.
 494          */
 495         if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) &&
 496             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) &&
 497             !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap))
 498                 return false;
 499
 500         if (mmc_doing_retune(host->mmc))
 501                 return false;
 502
 503         /* Check SCC error */
 504         if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) &
 505             SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &&
 506             sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) &
 507             SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) {
 508                 /* Clear SCC error */
 509                 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0);
 510                 return true;
 511         }
 512
 513         return false;
 514 }
 515
 516 static void renesas_sdhi_hw_reset(struct tmio_mmc_host *host)
 517 {
 518         struct renesas_sdhi *priv;
 519
 520         priv = host_to_priv(host);
 521
 522         renesas_sdhi_reset_scc(host, priv);
 523         renesas_sdhi_reset_hs400_mode(host, priv);
 524
 525         sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN |
 526                         sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL));
 527
 528         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 529                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 530                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 531
 532         sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL,
 533                        ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN &
 534                        sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL));
 535 }
 536
 537 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit)
 538 {
 539         int timeout = 1000;
 540         /* CBSY is set when busy, SCLKDIVEN is cleared when busy */
 541         u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0);
 542
 543         while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS)
 544                               & bit) == wait_state)
 545                 udelay(1);
 546
 547         if (!timeout) {
 548                 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n");
 549                 return -EBUSY;
 550         }
 551
 552         return 0;
 553 }
 554
 555 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr)
 556 {
 557         u32 bit = TMIO_STAT_SCLKDIVEN;
 558
 559         switch (addr) {
 560         case CTL_SD_CMD:
 561         case CTL_STOP_INTERNAL_ACTION:
 562         case CTL_XFER_BLK_COUNT:
 563         case CTL_SD_XFER_LEN:
 564         case CTL_SD_MEM_CARD_OPT:
 565         case CTL_TRANSACTION_CTL:
 566         case CTL_DMA_ENABLE:
 567         case HOST_MODE:
 568                 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY)
 569                         bit = TMIO_STAT_CMD_BUSY;
 570                 /* fallthrough */
 571         case CTL_SD_CARD_CLK_CTL:
 572                 return renesas_sdhi_wait_idle(host, bit);
 573         }
 574
 575         return 0;
 576 }
 577
 578 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card,
 579                                        unsigned int direction, int blk_size)
 580 {
 581         /*
 582          * In Renesas controllers, when performing a
 583          * multiple block read of one or two blocks,
 584          * depending on the timing with which the
 585          * response register is read, the response
 586          * value may not be read properly.
 587          * Use single block read for this HW bug
 588          */
 589         if ((direction == MMC_DATA_READ) &&
 590             blk_size == 2)
 591                 return 1;
 592
 593         return blk_size;
 594 }
 595
 596 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable)
 597 {
 598         /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */
 599         int width = (host->bus_shift == 2) ? 64 : 32;
 600
 601         sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0);
 602         renesas_sdhi_sdbuf_width(host, enable ? width : 16);
 603 }
 604
 605 int renesas_sdhi_probe(struct platform_device *pdev,
 606                        const struct tmio_mmc_dma_ops *dma_ops)
 607 {
 608         struct tmio_mmc_data *mmd = pdev->dev.platform_data;
 609         const struct renesas_sdhi_of_data *of_data;
 610         struct tmio_mmc_data *mmc_data;
 611         struct tmio_mmc_dma *dma_priv;
 612         struct tmio_mmc_host *host;
 613         struct renesas_sdhi *priv;
 614         struct resource *res;
 615         int irq, ret, i;
 616
 617         of_data = of_device_get_match_data(&pdev->dev);
 618
 619         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 620         if (!res)
 621                 return -EINVAL;
 622
 623         priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi),
 624                             GFP_KERNEL);
 625         if (!priv)
 626                 return -ENOMEM;
 627
 628         mmc_data = &priv->mmc_data;
 629         dma_priv = &priv->dma_priv;
 630
 631         priv->clk = devm_clk_get(&pdev->dev, NULL);
 632         if (IS_ERR(priv->clk)) {
 633                 ret = PTR_ERR(priv->clk);
 634                 dev_err(&pdev->dev, "cannot get clock: %d\n", ret);
 635                 return ret;
 636         }
 637
 638         /*
 639          * Some controllers provide a 2nd clock just to run the internal card
 640          * detection logic. Unfortunately, the existing driver architecture does
 641          * not support a separation of clocks for runtime PM usage. When
 642          * native hotplug is used, the tmio driver assumes that the core
 643          * must continue to run for card detect to stay active, so we cannot
 644          * disable it.
 645          * Additionally, it is prohibited to supply a clock to the core but not
 646          * to the card detect circuit. That leaves us with if separate clocks
 647          * are presented, we must treat them both as virtually 1 clock.
 648          */
 649         priv->clk_cd = devm_clk_get(&pdev->dev, "cd");
 650         if (IS_ERR(priv->clk_cd))
 651                 priv->clk_cd = NULL;
 652
 653         priv->pinctrl = devm_pinctrl_get(&pdev->dev);
 654         if (!IS_ERR(priv->pinctrl)) {
 655                 priv->pins_default = pinctrl_lookup_state(priv->pinctrl,
 656                                                 PINCTRL_STATE_DEFAULT);
 657                 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl,
 658                                                 "state_uhs");
 659         }
 660
 661         host = tmio_mmc_host_alloc(pdev, mmc_data);
 662         if (IS_ERR(host))
 663                 return PTR_ERR(host);
 664
 665         if (of_data) {
 666                 mmc_data->flags |= of_data->tmio_flags;
 667                 mmc_data->ocr_mask = of_data->tmio_ocr_mask;
 668                 mmc_data->capabilities |= of_data->capabilities;
 669                 mmc_data->capabilities2 |= of_data->capabilities2;
 670                 mmc_data->dma_rx_offset = of_data->dma_rx_offset;
 671                 mmc_data->max_blk_count = of_data->max_blk_count;
 672                 mmc_data->max_segs = of_data->max_segs;
 673                 dma_priv->dma_buswidth = of_data->dma_buswidth;
 674                 host->bus_shift = of_data->bus_shift;
 675         }
 676
 677         host->write16_hook      = renesas_sdhi_write16_hook;
 678         host->clk_enable        = renesas_sdhi_clk_enable;
 679         host->clk_disable       = renesas_sdhi_clk_disable;
 680         host->set_clock         = renesas_sdhi_set_clock;
 681         host->multi_io_quirk    = renesas_sdhi_multi_io_quirk;
 682         host->dma_ops           = dma_ops;
 683
 684         /* For some SoC, we disable internal WP. GPIO may override this */
 685         if (mmc_can_gpio_ro(host->mmc))
 686                 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT;
 687
 688         /* SDR speeds are only available on Gen2+ */
 689         if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) {
 690                 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */
 691                 host->ops.card_busy = renesas_sdhi_card_busy;
 692                 host->ops.start_signal_voltage_switch =
 693                         renesas_sdhi_start_signal_voltage_switch;
 694         }
 695
 696         /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */
 697         if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */
 698                 host->bus_shift = 1;
 699
 700         if (mmd)
 701                 *mmc_data = *mmd;
 702
 703         dma_priv->filter = shdma_chan_filter;
 704         dma_priv->enable = renesas_sdhi_enable_dma;
 705
 706         mmc_data->alignment_shift = 1; /* 2-byte alignment */
 707         mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED;
 708
 709         /*
 710          * All SDHI blocks support 2-byte and larger block sizes in 4-bit
 711          * bus width mode.
 712          */
 713         mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES;
 714
 715         /*
 716          * All SDHI blocks support SDIO IRQ signalling.
 717          */
 718         mmc_data->flags |= TMIO_MMC_SDIO_IRQ;
 719
 720         /* All SDHI have CMD12 control bit */
 721         mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL;
 722
 723         /* All SDHI have SDIO status bits which must be 1 */
 724         mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS;
 725
 726         ret = renesas_sdhi_clk_enable(host);
 727         if (ret)
 728                 goto efree;
 729
 730         ret = tmio_mmc_host_probe(host);
 731         if (ret < 0)
 732                 goto edisclk;
 733
 734         /* One Gen2 SDHI incarnation does NOT have a CBSY bit */
 735         if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN2_SDR50)
 736                 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY;
 737
 738         /* Enable tuning iff we have an SCC and a supported mode */
 739         if (of_data && of_data->scc_offset &&
 740             (host->mmc->caps & MMC_CAP_UHS_SDR104 ||
 741              host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR |
 742                                  MMC_CAP2_HS400_1_8V))) {
 743                 const struct renesas_sdhi_scc *taps = of_data->taps;
 744                 bool hit = false;
 745
 746                 host->mmc->caps |= MMC_CAP_HW_RESET;
 747
 748                 for (i = 0; i < of_data->taps_num; i++) {
 749                         if (taps[i].clk_rate == 0 ||
 750                             taps[i].clk_rate == host->mmc->f_max) {
 751                                 priv->scc_tappos = taps->tap;
 752                                 hit = true;
 753                                 break;
 754                         }
 755                 }
 756
 757                 if (!hit)
 758                         dev_warn(&host->pdev->dev, "Unknown clock rate for SDR104\n");
 759
 760                 priv->scc_ctl = host->ctl + of_data->scc_offset;
 761                 host->init_tuning = renesas_sdhi_init_tuning;
 762                 host->prepare_tuning = renesas_sdhi_prepare_tuning;
 763                 host->select_tuning = renesas_sdhi_select_tuning;
 764                 host->check_scc_error = renesas_sdhi_check_scc_error;
 765                 host->hw_reset = renesas_sdhi_hw_reset;
 766                 host->prepare_hs400_tuning =
 767                         renesas_sdhi_prepare_hs400_tuning;
 768                 host->hs400_downgrade = renesas_sdhi_disable_scc;
 769                 host->hs400_complete = renesas_sdhi_hs400_complete;
 770         }
 771
 772         i = 0;
 773         while (1) {
 774                 irq = platform_get_irq(pdev, i);
 775                 if (irq < 0)
 776                         break;
 777                 i++;
 778                 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0,
 779                                        dev_name(&pdev->dev), host);
 780                 if (ret)
 781                         goto eirq;
 782         }
 783
 784         /* There must be at least one IRQ source */
 785         if (!i) {
 786                 ret = irq;
 787                 goto eirq;
 788         }
 789
 790         dev_info(&pdev->dev, "%s base at 0x%08lx max clock rate %u MHz\n",
 791                  mmc_hostname(host->mmc), (unsigned long)
 792                  (platform_get_resource(pdev, IORESOURCE_MEM, 0)->start),
 793                  host->mmc->f_max / 1000000);
 794
 795         return ret;
 796
 797 eirq:
 798         tmio_mmc_host_remove(host);
 799 edisclk:
 800         renesas_sdhi_clk_disable(host);
 801 efree:
 802         tmio_mmc_host_free(host);
 803
 804         return ret;
 805 }
 806 EXPORT_SYMBOL_GPL(renesas_sdhi_probe);
 807
 808 int renesas_sdhi_remove(struct platform_device *pdev)
 809 {
 810         struct tmio_mmc_host *host = platform_get_drvdata(pdev);
 811
 812         tmio_mmc_host_remove(host);
 813         renesas_sdhi_clk_disable(host);
 814
 815         return 0;
 816 }
 817 EXPORT_SYMBOL_GPL(renesas_sdhi_remove);
 818
 819 MODULE_LICENSE("GPL v2");