drivers/mmc/host/renesas_sdhi_internal_dmac.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * DMA support for Internal DMAC with SDHI SD/SDIO controller
   4  *
   5  * Copyright (C) 2016-17 Renesas Electronics Corporation
   6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
   7  */
   8
   9 #include <linux/bitops.h>
  10 #include <linux/device.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/io-64-nonatomic-hi-lo.h>
  13 #include <linux/mfd/tmio.h>
  14 #include <linux/mmc/host.h>
  15 #include <linux/mod_devicetable.h>
  16 #include <linux/module.h>
  17 #include <linux/pagemap.h>
  18 #include <linux/scatterlist.h>
  19 #include <linux/sys_soc.h>
  20
  21 #include "renesas_sdhi.h"
  22 #include "tmio_mmc.h"
  23
  24 #define DM_CM_DTRAN_MODE        0x820
  25 #define DM_CM_DTRAN_CTRL        0x828
  26 #define DM_CM_RST               0x830
  27 #define DM_CM_INFO1             0x840
  28 #define DM_CM_INFO1_MASK        0x848
  29 #define DM_CM_INFO2             0x850
  30 #define DM_CM_INFO2_MASK        0x858
  31 #define DM_DTRAN_ADDR           0x880
  32
  33 /* DM_CM_DTRAN_MODE */
  34 #define DTRAN_MODE_CH_NUM_CH0   0       /* "downstream" = for write commands */
  35 #define DTRAN_MODE_CH_NUM_CH1   BIT(16) /* "upstream" = for read commands */
  36 #define DTRAN_MODE_BUS_WIDTH    (BIT(5) | BIT(4))
  37 #define DTRAN_MODE_ADDR_MODE    BIT(0)  /* 1 = Increment address */
  38
  39 /* DM_CM_DTRAN_CTRL */
  40 #define DTRAN_CTRL_DM_START     BIT(0)
  41
  42 /* DM_CM_RST */
  43 #define RST_DTRANRST1           BIT(9)
  44 #define RST_DTRANRST0           BIT(8)
  45 #define RST_RESERVED_BITS       GENMASK_ULL(31, 0)
  46
  47 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
  48 #define INFO1_CLEAR             0
  49 #define INFO1_MASK_CLEAR        GENMASK_ULL(31, 0)
  50 #define INFO1_DTRANEND1         BIT(17)
  51 #define INFO1_DTRANEND0         BIT(16)
  52
  53 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
  54 #define INFO2_MASK_CLEAR        GENMASK_ULL(31, 0)
  55 #define INFO2_DTRANERR1         BIT(17)
  56 #define INFO2_DTRANERR0         BIT(16)
  57
  58 /*
  59  * Specification of this driver:
  60  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
  61  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
  62  *   need a custom accessor.
  63  */
  64
  65 static unsigned long global_flags;
  66 /*
  67  * Workaround for avoiding to use RX DMAC by multiple channels.
  68  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
  69  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
  70  * stored into the system memory even if the DMAC interrupt happened.
  71  * So, this driver then uses one RX DMAC channel only.
  72  */
  73 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY  0
  74 #define SDHI_INTERNAL_DMAC_RX_IN_USE    1
  75
  76 /* Definitions for sampling clocks */
  77 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
  78         {
  79                 .clk_rate = 0,
  80                 .tap = 0x00000300,
  81         },
  82 };
  83
  84 static const struct renesas_sdhi_of_data of_rcar_r8a7795_compatible = {
  85         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
  86                           TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2 |
  87                           TMIO_MMC_HAVE_4TAP_HS400,
  88         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
  89                           MMC_CAP_CMD23,
  90         .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
  91         .bus_shift      = 2,
  92         .scc_offset     = 0x1000,
  93         .taps           = rcar_gen3_scc_taps,
  94         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
  95         /* DMAC can handle 0xffffffff blk count but only 1 segment */
  96         .max_blk_count  = 0xffffffff,
  97         .max_segs       = 1,
  98 };
  99
 100 static const struct renesas_sdhi_of_data of_rcar_gen3_compatible = {
 101         .tmio_flags     = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
 102                           TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
 103         .capabilities   = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
 104                           MMC_CAP_CMD23,
 105         .capabilities2  = MMC_CAP2_NO_WRITE_PROTECT,
 106         .bus_shift      = 2,
 107         .scc_offset     = 0x1000,
 108         .taps           = rcar_gen3_scc_taps,
 109         .taps_num       = ARRAY_SIZE(rcar_gen3_scc_taps),
 110         /* DMAC can handle 0xffffffff blk count but only 1 segment */
 111         .max_blk_count  = 0xffffffff,
 112         .max_segs       = 1,
 113 };
 114
 115 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
 116         { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
 117         { .compatible = "renesas,sdhi-r8a7795", .data = &of_rcar_r8a7795_compatible, },
 118         { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_r8a7795_compatible, },
 119         { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
 120         {},
 121 };
 122 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
 123
 124 static void
 125 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
 126                                     int addr, u64 val)
 127 {
 128         writeq(val, host->ctl + addr);
 129 }
 130
 131 static void
 132 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
 133 {
 134         struct renesas_sdhi *priv = host_to_priv(host);
 135
 136         if (!host->chan_tx || !host->chan_rx)
 137                 return;
 138
 139         if (!enable)
 140                 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
 141                                                     INFO1_CLEAR);
 142
 143         if (priv->dma_priv.enable)
 144                 priv->dma_priv.enable(host, enable);
 145 }
 146
 147 static void
 148 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
 149         u64 val = RST_DTRANRST1 | RST_DTRANRST0;
 150
 151         renesas_sdhi_internal_dmac_enable_dma(host, false);
 152
 153         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 154                                             RST_RESERVED_BITS & ~val);
 155         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
 156                                             RST_RESERVED_BITS | val);
 157
 158         clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 159
 160         renesas_sdhi_internal_dmac_enable_dma(host, true);
 161 }
 162
 163 static void
 164 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
 165         struct renesas_sdhi *priv = host_to_priv(host);
 166
 167         tasklet_schedule(&priv->dma_priv.dma_complete);
 168 }
 169
 170 static void
 171 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
 172                                      struct mmc_data *data)
 173 {
 174         struct scatterlist *sg = host->sg_ptr;
 175         u32 dtran_mode = DTRAN_MODE_BUS_WIDTH | DTRAN_MODE_ADDR_MODE;
 176
 177         if (!dma_map_sg(&host->pdev->dev, sg, host->sg_len,
 178                         mmc_get_dma_dir(data)))
 179                 goto force_pio;
 180
 181         /* This DMAC cannot handle if buffer is not 8-bytes alignment */
 182         if (!IS_ALIGNED(sg_dma_address(sg), 8))
 183                 goto force_pio_with_unmap;
 184
 185         if (data->flags & MMC_DATA_READ) {
 186                 dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
 187                 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
 188                     test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
 189                         goto force_pio_with_unmap;
 190         } else {
 191                 dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
 192         }
 193
 194         renesas_sdhi_internal_dmac_enable_dma(host, true);
 195
 196         /* set dma parameters */
 197         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
 198                                             dtran_mode);
 199         renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
 200                                             sg_dma_address(sg));
 201
 202         host->dma_on = true;
 203
 204         return;
 205
 206 force_pio_with_unmap:
 207         dma_unmap_sg(&host->pdev->dev, sg, host->sg_len, mmc_get_dma_dir(data));
 208
 209 force_pio:
 210         renesas_sdhi_internal_dmac_enable_dma(host, false);
 211 }
 212
 213 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
 214 {
 215         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 216
 217         tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
 218
 219         /* start the DMAC */
 220         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
 221                                             DTRAN_CTRL_DM_START);
 222 }
 223
 224 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
 225 {
 226         struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
 227         enum dma_data_direction dir;
 228
 229         spin_lock_irq(&host->lock);
 230
 231         if (!host->data)
 232                 goto out;
 233
 234         if (host->data->flags & MMC_DATA_READ)
 235                 dir = DMA_FROM_DEVICE;
 236         else
 237                 dir = DMA_TO_DEVICE;
 238
 239         renesas_sdhi_internal_dmac_enable_dma(host, false);
 240         dma_unmap_sg(&host->pdev->dev, host->sg_ptr, host->sg_len, dir);
 241
 242         if (dir == DMA_FROM_DEVICE)
 243                 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
 244
 245         tmio_mmc_do_data_irq(host);
 246 out:
 247         spin_unlock_irq(&host->lock);
 248 }
 249
 250 static void
 251 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
 252                                        struct tmio_mmc_data *pdata)
 253 {
 254         struct renesas_sdhi *priv = host_to_priv(host);
 255
 256         /* Disable DMAC interrupts, we don't use them */
 257         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
 258                                             INFO1_MASK_CLEAR);
 259         renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
 260                                             INFO2_MASK_CLEAR);
 261
 262         /* Each value is set to non-zero to assume "enabling" each DMA */
 263         host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
 264
 265         tasklet_init(&priv->dma_priv.dma_complete,
 266                      renesas_sdhi_internal_dmac_complete_tasklet_fn,
 267                      (unsigned long)host);
 268         tasklet_init(&host->dma_issue,
 269                      renesas_sdhi_internal_dmac_issue_tasklet_fn,
 270                      (unsigned long)host);
 271 }
 272
 273 static void
 274 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
 275 {
 276         /* Each value is set to zero to assume "disabling" each DMA */
 277         host->chan_rx = host->chan_tx = NULL;
 278 }
 279
 280 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
 281         .start = renesas_sdhi_internal_dmac_start_dma,
 282         .enable = renesas_sdhi_internal_dmac_enable_dma,
 283         .request = renesas_sdhi_internal_dmac_request_dma,
 284         .release = renesas_sdhi_internal_dmac_release_dma,
 285         .abort = renesas_sdhi_internal_dmac_abort_dma,
 286         .dataend = renesas_sdhi_internal_dmac_dataend_dma,
 287 };
 288
 289 /*
 290  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
 291  * implementation as others may use a different implementation.
 292  */
 293 static const struct soc_device_attribute soc_whitelist[] = {
 294         /* specific ones */
 295         { .soc_id = "r8a7795", .revision = "ES1.*",
 296           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 297         { .soc_id = "r8a7796", .revision = "ES1.0",
 298           .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 299         /* generic ones */
 300         { .soc_id = "r8a774a1" },
 301         { .soc_id = "r8a77470" },
 302         { .soc_id = "r8a7795" },
 303         { .soc_id = "r8a7796" },
 304         { .soc_id = "r8a77965" },
 305         { .soc_id = "r8a77970" },
 306         { .soc_id = "r8a77980" },
 307         { .soc_id = "r8a77995" },
 308         { /* sentinel */ }
 309 };
 310
 311 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
 312 {
 313         const struct soc_device_attribute *soc = soc_device_match(soc_whitelist);
 314         struct device *dev = &pdev->dev;
 315
 316         if (!soc)
 317                 return -ENODEV;
 318
 319         global_flags |= (unsigned long)soc->data;
 320
 321         dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), GFP_KERNEL);
 322         if (!dev->dma_parms)
 323                 return -ENOMEM;
 324
 325         /* value is max of SD_SECCNT. Confirmed by HW engineers */
 326         dma_set_max_seg_size(dev, 0xffffffff);
 327
 328         return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops);
 329 }
 330
 331 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
 332         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 333                                 pm_runtime_force_resume)
 334         SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
 335                            tmio_mmc_host_runtime_resume,
 336                            NULL)
 337 };
 338
 339 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
 340         .driver         = {
 341                 .name   = "renesas_sdhi_internal_dmac",
 342                 .pm     = &renesas_sdhi_internal_dmac_dev_pm_ops,
 343                 .of_match_table = renesas_sdhi_internal_dmac_of_match,
 344         },
 345         .probe          = renesas_sdhi_internal_dmac_probe,
 346         .remove         = renesas_sdhi_remove,
 347 };
 348
 349 module_platform_driver(renesas_internal_dmac_sdhi_driver);
 350
 351 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
 352 MODULE_AUTHOR("Yoshihiro Shimoda");
 353 MODULE_LICENSE("GPL v2");