drivers/mmc/host/sdhci-iproc.c

   1 /*
   2  * Copyright (C) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 /*
  15  * iProc SDHCI platform driver
  16  */
  17
  18 #include <linux/acpi.h>
  19 #include <linux/delay.h>
  20 #include <linux/module.h>
  21 #include <linux/mmc/host.h>
  22 #include <linux/of.h>
  23 #include <linux/of_device.h>
  24 #include "sdhci-pltfm.h"
  25
  26 struct sdhci_iproc_data {
  27         const struct sdhci_pltfm_data *pdata;
  28         u32 caps;
  29         u32 caps1;
  30         u32 mmc_caps;
  31 };
  32
  33 struct sdhci_iproc_host {
  34         const struct sdhci_iproc_data *data;
  35         u32 shadow_cmd;
  36         u32 shadow_blk;
  37         bool is_cmd_shadowed;
  38         bool is_blk_shadowed;
  39 };
  40
  41 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
  42
  43 static inline u32 sdhci_iproc_readl(struct sdhci_host *host, int reg)
  44 {
  45         u32 val = readl(host->ioaddr + reg);
  46
  47         pr_debug("%s: readl [0x%02x] 0x%08x\n",
  48                  mmc_hostname(host->mmc), reg, val);
  49         return val;
  50 }
  51
  52 static u16 sdhci_iproc_readw(struct sdhci_host *host, int reg)
  53 {
  54         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  55         struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
  56         u32 val;
  57         u16 word;
  58
  59         if ((reg == SDHCI_TRANSFER_MODE) && iproc_host->is_cmd_shadowed) {
  60                 /* Get the saved transfer mode */
  61                 val = iproc_host->shadow_cmd;
  62         } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
  63                    iproc_host->is_blk_shadowed) {
  64                 /* Get the saved block info */
  65                 val = iproc_host->shadow_blk;
  66         } else {
  67                 val = sdhci_iproc_readl(host, (reg & ~3));
  68         }
  69         word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
  70         return word;
  71 }
  72
  73 static u8 sdhci_iproc_readb(struct sdhci_host *host, int reg)
  74 {
  75         u32 val = sdhci_iproc_readl(host, (reg & ~3));
  76         u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
  77         return byte;
  78 }
  79
  80 static inline void sdhci_iproc_writel(struct sdhci_host *host, u32 val, int reg)
  81 {
  82         pr_debug("%s: writel [0x%02x] 0x%08x\n",
  83                  mmc_hostname(host->mmc), reg, val);
  84
  85         writel(val, host->ioaddr + reg);
  86
  87         if (host->clock <= 400000) {
  88                 /* Round up to micro-second four SD clock delay */
  89                 if (host->clock)
  90                         udelay((4 * 1000000 + host->clock - 1) / host->clock);
  91                 else
  92                         udelay(10);
  93         }
  94 }
  95
  96 /*
  97  * The Arasan has a bugette whereby it may lose the content of successive
  98  * writes to the same register that are within two SD-card clock cycles of
  99  * each other (a clock domain crossing problem). The data
 100  * register does not have this problem, which is just as well - otherwise we'd
 101  * have to nobble the DMA engine too.
 102  *
 103  * This wouldn't be a problem with the code except that we can only write the
 104  * controller with 32-bit writes.  So two different 16-bit registers are
 105  * written back to back creates the problem.
 106  *
 107  * In reality, this only happens when SDHCI_BLOCK_SIZE and SDHCI_BLOCK_COUNT
 108  * are written followed by SDHCI_TRANSFER_MODE and SDHCI_COMMAND.
 109  * The BLOCK_SIZE and BLOCK_COUNT are meaningless until a command issued so
 110  * the work around can be further optimized. We can keep shadow values of
 111  * BLOCK_SIZE, BLOCK_COUNT, and TRANSFER_MODE until a COMMAND is issued.
 112  * Then, write the BLOCK_SIZE+BLOCK_COUNT in a single 32-bit write followed
 113  * by the TRANSFER+COMMAND in another 32-bit write.
 114  */
 115 static void sdhci_iproc_writew(struct sdhci_host *host, u16 val, int reg)
 116 {
 117         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 118         struct sdhci_iproc_host *iproc_host = sdhci_pltfm_priv(pltfm_host);
 119         u32 word_shift = REG_OFFSET_IN_BITS(reg);
 120         u32 mask = 0xffff << word_shift;
 121         u32 oldval, newval;
 122
 123         if (reg == SDHCI_COMMAND) {
 124                 /* Write the block now as we are issuing a command */
 125                 if (iproc_host->is_blk_shadowed) {
 126                         sdhci_iproc_writel(host, iproc_host->shadow_blk,
 127                                 SDHCI_BLOCK_SIZE);
 128                         iproc_host->is_blk_shadowed = false;
 129                 }
 130                 oldval = iproc_host->shadow_cmd;
 131                 iproc_host->is_cmd_shadowed = false;
 132         } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
 133                    iproc_host->is_blk_shadowed) {
 134                 /* Block size and count are stored in shadow reg */
 135                 oldval = iproc_host->shadow_blk;
 136         } else {
 137                 /* Read reg, all other registers are not shadowed */
 138                 oldval = sdhci_iproc_readl(host, (reg & ~3));
 139         }
 140         newval = (oldval & ~mask) | (val << word_shift);
 141
 142         if (reg == SDHCI_TRANSFER_MODE) {
 143                 /* Save the transfer mode until the command is issued */
 144                 iproc_host->shadow_cmd = newval;
 145                 iproc_host->is_cmd_shadowed = true;
 146         } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
 147                 /* Save the block info until the command is issued */
 148                 iproc_host->shadow_blk = newval;
 149                 iproc_host->is_blk_shadowed = true;
 150         } else {
 151                 /* Command or other regular 32-bit write */
 152                 sdhci_iproc_writel(host, newval, reg & ~3);
 153         }
 154 }
 155
 156 static void sdhci_iproc_writeb(struct sdhci_host *host, u8 val, int reg)
 157 {
 158         u32 oldval = sdhci_iproc_readl(host, (reg & ~3));
 159         u32 byte_shift = REG_OFFSET_IN_BITS(reg);
 160         u32 mask = 0xff << byte_shift;
 161         u32 newval = (oldval & ~mask) | (val << byte_shift);
 162
 163         sdhci_iproc_writel(host, newval, reg & ~3);
 164 }
 165
 166 static unsigned int sdhci_iproc_get_max_clock(struct sdhci_host *host)
 167 {
 168         struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
 169
 170         if (pltfm_host->clk)
 171                 return sdhci_pltfm_clk_get_max_clock(host);
 172         else
 173                 return pltfm_host->clock;
 174 }
 175
 176 static const struct sdhci_ops sdhci_iproc_ops = {
 177         .set_clock = sdhci_set_clock,
 178         .get_max_clock = sdhci_iproc_get_max_clock,
 179         .set_bus_width = sdhci_set_bus_width,
 180         .reset = sdhci_reset,
 181         .set_uhs_signaling = sdhci_set_uhs_signaling,
 182 };
 183
 184 static const struct sdhci_ops sdhci_iproc_32only_ops = {
 185         .read_l = sdhci_iproc_readl,
 186         .read_w = sdhci_iproc_readw,
 187         .read_b = sdhci_iproc_readb,
 188         .write_l = sdhci_iproc_writel,
 189         .write_w = sdhci_iproc_writew,
 190         .write_b = sdhci_iproc_writeb,
 191         .set_clock = sdhci_set_clock,
 192         .get_max_clock = sdhci_iproc_get_max_clock,
 193         .set_bus_width = sdhci_set_bus_width,
 194         .reset = sdhci_reset,
 195         .set_uhs_signaling = sdhci_set_uhs_signaling,
 196 };
 197
 198 static const struct sdhci_pltfm_data sdhci_iproc_cygnus_pltfm_data = {
 199         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK,
 200         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN | SDHCI_QUIRK2_HOST_OFF_CARD_ON,
 201         .ops = &sdhci_iproc_32only_ops,
 202 };
 203
 204 static const struct sdhci_iproc_data iproc_cygnus_data = {
 205         .pdata = &sdhci_iproc_cygnus_pltfm_data,
 206         .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
 207                         & SDHCI_MAX_BLOCK_MASK) |
 208                 SDHCI_CAN_VDD_330 |
 209                 SDHCI_CAN_VDD_180 |
 210                 SDHCI_CAN_DO_SUSPEND |
 211                 SDHCI_CAN_DO_HISPD |
 212                 SDHCI_CAN_DO_ADMA2 |
 213                 SDHCI_CAN_DO_SDMA,
 214         .caps1 = SDHCI_DRIVER_TYPE_C |
 215                  SDHCI_DRIVER_TYPE_D |
 216                  SDHCI_SUPPORT_DDR50,
 217         .mmc_caps = MMC_CAP_1_8V_DDR,
 218 };
 219
 220 static const struct sdhci_pltfm_data sdhci_iproc_pltfm_data = {
 221         .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 222                   SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12,
 223         .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN,
 224         .ops = &sdhci_iproc_ops,
 225 };
 226
 227 static const struct sdhci_iproc_data iproc_data = {
 228         .pdata = &sdhci_iproc_pltfm_data,
 229         .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
 230                         & SDHCI_MAX_BLOCK_MASK) |
 231                 SDHCI_CAN_VDD_330 |
 232                 SDHCI_CAN_VDD_180 |
 233                 SDHCI_CAN_DO_SUSPEND |
 234                 SDHCI_CAN_DO_HISPD |
 235                 SDHCI_CAN_DO_ADMA2 |
 236                 SDHCI_CAN_DO_SDMA,
 237         .caps1 = SDHCI_DRIVER_TYPE_C |
 238                  SDHCI_DRIVER_TYPE_D |
 239                  SDHCI_SUPPORT_DDR50,
 240 };
 241
 242 static const struct sdhci_pltfm_data sdhci_bcm2835_pltfm_data = {
 243         .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
 244                   SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
 245                   SDHCI_QUIRK_MISSING_CAPS |
 246                   SDHCI_QUIRK_NO_HISPD_BIT,
 247         .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
 248         .ops = &sdhci_iproc_32only_ops,
 249 };
 250
 251 static const struct sdhci_iproc_data bcm2835_data = {
 252         .pdata = &sdhci_bcm2835_pltfm_data,
 253         .caps = ((0x1 << SDHCI_MAX_BLOCK_SHIFT)
 254                         & SDHCI_MAX_BLOCK_MASK) |
 255                 SDHCI_CAN_VDD_330 |
 256                 SDHCI_CAN_DO_HISPD,
 257         .caps1 = SDHCI_DRIVER_TYPE_A |
 258                  SDHCI_DRIVER_TYPE_C,
 259         .mmc_caps = 0x00000000,
 260 };
 261
 262 static const struct of_device_id sdhci_iproc_of_match[] = {
 263         { .compatible = "brcm,bcm2835-sdhci", .data = &bcm2835_data },
 264         { .compatible = "brcm,sdhci-iproc-cygnus", .data = &iproc_cygnus_data},
 265         { .compatible = "brcm,sdhci-iproc", .data = &iproc_data },
 266         { }
 267 };
 268 MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match);
 269
 270 static const struct acpi_device_id sdhci_iproc_acpi_ids[] = {
 271         { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data },
 272         { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data },
 273         { /* sentinel */ }
 274 };
 275 MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids);
 276
 277 static int sdhci_iproc_probe(struct platform_device *pdev)
 278 {
 279         struct device *dev = &pdev->dev;
 280         const struct sdhci_iproc_data *iproc_data = NULL;
 281         struct sdhci_host *host;
 282         struct sdhci_iproc_host *iproc_host;
 283         struct sdhci_pltfm_host *pltfm_host;
 284         int ret;
 285
 286         iproc_data = device_get_match_data(dev);
 287         if (!iproc_data)
 288                 return -ENODEV;
 289
 290         host = sdhci_pltfm_init(pdev, iproc_data->pdata, sizeof(*iproc_host));
 291         if (IS_ERR(host))
 292                 return PTR_ERR(host);
 293
 294         pltfm_host = sdhci_priv(host);
 295         iproc_host = sdhci_pltfm_priv(pltfm_host);
 296
 297         iproc_host->data = iproc_data;
 298
 299         mmc_of_parse(host->mmc);
 300         sdhci_get_property(pdev);
 301
 302         host->mmc->caps |= iproc_host->data->mmc_caps;
 303
 304         if (dev->of_node) {
 305                 pltfm_host->clk = devm_clk_get(dev, NULL);
 306                 if (IS_ERR(pltfm_host->clk)) {
 307                         ret = PTR_ERR(pltfm_host->clk);
 308                         goto err;
 309                 }
 310                 ret = clk_prepare_enable(pltfm_host->clk);
 311                 if (ret) {
 312                         dev_err(dev, "failed to enable host clk\n");
 313                         goto err;
 314                 }
 315         }
 316
 317         if (iproc_host->data->pdata->quirks & SDHCI_QUIRK_MISSING_CAPS) {
 318                 host->caps = iproc_host->data->caps;
 319                 host->caps1 = iproc_host->data->caps1;
 320         }
 321
 322         ret = sdhci_add_host(host);
 323         if (ret)
 324                 goto err_clk;
 325
 326         return 0;
 327
 328 err_clk:
 329         if (dev->of_node)
 330                 clk_disable_unprepare(pltfm_host->clk);
 331 err:
 332         sdhci_pltfm_free(pdev);
 333         return ret;
 334 }
 335
 336 static struct platform_driver sdhci_iproc_driver = {
 337         .driver = {
 338                 .name = "sdhci-iproc",
 339                 .of_match_table = sdhci_iproc_of_match,
 340                 .acpi_match_table = ACPI_PTR(sdhci_iproc_acpi_ids),
 341                 .pm = &sdhci_pltfm_pmops,
 342         },
 343         .probe = sdhci_iproc_probe,
 344         .remove = sdhci_pltfm_unregister,
 345 };
 346 module_platform_driver(sdhci_iproc_driver);
 347
 348 MODULE_AUTHOR("Broadcom");
 349 MODULE_DESCRIPTION("IPROC SDHCI driver");
 350 MODULE_LICENSE("GPL v2");