drivers/mmc/host/sdhci-pci-o2micro.c

   1 /*
   2  * Copyright (C) 2013 BayHub Technology Ltd.
   3  *
   4  * Authors: Peter Guo <peter.guo@bayhubtech.com>
   5  *          Adam Lee <adam.lee@canonical.com>
   6  *          Ernest Zhang <ernest.zhang@bayhubtech.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/pci.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/mmc.h>
  22 #include <linux/delay.h>
  23
  24 #include "sdhci.h"
  25 #include "sdhci-pci.h"
  26
  27 /*
  28  * O2Micro device registers
  29  */
  30
  31 #define O2_SD_MISC_REG5         0x64
  32 #define O2_SD_LD0_CTRL          0x68
  33 #define O2_SD_DEV_CTRL          0x88
  34 #define O2_SD_LOCK_WP           0xD3
  35 #define O2_SD_TEST_REG          0xD4
  36 #define O2_SD_FUNC_REG0         0xDC
  37 #define O2_SD_MULTI_VCC3V       0xEE
  38 #define O2_SD_CLKREQ            0xEC
  39 #define O2_SD_CAPS              0xE0
  40 #define O2_SD_ADMA1             0xE2
  41 #define O2_SD_ADMA2             0xE7
  42 #define O2_SD_INF_MOD           0xF1
  43 #define O2_SD_MISC_CTRL4        0xFC
  44 #define O2_SD_TUNING_CTRL       0x300
  45 #define O2_SD_PLL_SETTING       0x304
  46 #define O2_SD_MISC_SETTING      0x308
  47 #define O2_SD_CLK_SETTING       0x328
  48 #define O2_SD_CAP_REG2          0x330
  49 #define O2_SD_CAP_REG0          0x334
  50 #define O2_SD_UHS1_CAP_SETTING  0x33C
  51 #define O2_SD_DELAY_CTRL        0x350
  52 #define O2_SD_UHS2_L1_CTRL      0x35C
  53 #define O2_SD_FUNC_REG3         0x3E0
  54 #define O2_SD_FUNC_REG4         0x3E4
  55 #define O2_SD_LED_ENABLE        BIT(6)
  56 #define O2_SD_FREG0_LEDOFF      BIT(13)
  57 #define O2_SD_FREG4_ENABLE_CLK_SET      BIT(22)
  58
  59 #define O2_SD_VENDOR_SETTING    0x110
  60 #define O2_SD_VENDOR_SETTING2   0x1C8
  61 #define O2_SD_HW_TUNING_DISABLE BIT(4)
  62
  63 static void sdhci_o2_set_tuning_mode(struct sdhci_host *host)
  64 {
  65         u16 reg;
  66
  67         /* enable hardware tuning */
  68         reg = sdhci_readw(host, O2_SD_VENDOR_SETTING);
  69         reg &= ~O2_SD_HW_TUNING_DISABLE;
  70         sdhci_writew(host, reg, O2_SD_VENDOR_SETTING);
  71 }
  72
  73 static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode)
  74 {
  75         int i;
  76
  77         sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200);
  78
  79         for (i = 0; i < 150; i++) {
  80                 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  81
  82                 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
  83                         if (ctrl & SDHCI_CTRL_TUNED_CLK) {
  84                                 host->tuning_done = true;
  85                                 return;
  86                         }
  87                         pr_warn("%s: HW tuning failed !\n",
  88                                 mmc_hostname(host->mmc));
  89                         break;
  90                 }
  91
  92                 mdelay(1);
  93         }
  94
  95         pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
  96                 mmc_hostname(host->mmc));
  97         sdhci_reset_tuning(host);
  98 }
  99
 100 static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)
 101 {
 102         struct sdhci_host *host = mmc_priv(mmc);
 103         int current_bus_width = 0;
 104
 105         /*
 106          * This handler only implements the eMMC tuning that is specific to
 107          * this controller.  Fall back to the standard method for other TIMING.
 108          */
 109         if (host->timing != MMC_TIMING_MMC_HS200)
 110                 return sdhci_execute_tuning(mmc, opcode);
 111
 112         if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
 113                 return -EINVAL;
 114
 115         /*
 116          * o2 sdhci host didn't support 8bit emmc tuning
 117          */
 118         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
 119                 current_bus_width = mmc->ios.bus_width;
 120                 sdhci_set_bus_width(host, MMC_BUS_WIDTH_4);
 121         }
 122
 123         sdhci_o2_set_tuning_mode(host);
 124
 125         sdhci_start_tuning(host);
 126
 127         __sdhci_o2_execute_tuning(host, opcode);
 128
 129         sdhci_end_tuning(host);
 130
 131         if (current_bus_width == MMC_BUS_WIDTH_8)
 132                 sdhci_set_bus_width(host, current_bus_width);
 133
 134         host->flags &= ~SDHCI_HS400_TUNING;
 135         return 0;
 136 }
 137
 138 static void o2_pci_set_baseclk(struct sdhci_pci_chip *chip, u32 value)
 139 {
 140         u32 scratch_32;
 141         pci_read_config_dword(chip->pdev,
 142                               O2_SD_PLL_SETTING, &scratch_32);
 143
 144         scratch_32 &= 0x0000FFFF;
 145         scratch_32 |= value;
 146
 147         pci_write_config_dword(chip->pdev,
 148                                O2_SD_PLL_SETTING, scratch_32);
 149 }
 150
 151 static void o2_pci_led_enable(struct sdhci_pci_chip *chip)
 152 {
 153         int ret;
 154         u32 scratch_32;
 155
 156         /* Set led of SD host function enable */
 157         ret = pci_read_config_dword(chip->pdev,
 158                                     O2_SD_FUNC_REG0, &scratch_32);
 159         if (ret)
 160                 return;
 161
 162         scratch_32 &= ~O2_SD_FREG0_LEDOFF;
 163         pci_write_config_dword(chip->pdev,
 164                                O2_SD_FUNC_REG0, scratch_32);
 165
 166         ret = pci_read_config_dword(chip->pdev,
 167                                     O2_SD_TEST_REG, &scratch_32);
 168         if (ret)
 169                 return;
 170
 171         scratch_32 |= O2_SD_LED_ENABLE;
 172         pci_write_config_dword(chip->pdev,
 173                                O2_SD_TEST_REG, scratch_32);
 174
 175 }
 176
 177 static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip)
 178 {
 179         u32 scratch_32;
 180         int ret;
 181         /* Improve write performance for SD3.0 */
 182         ret = pci_read_config_dword(chip->pdev, O2_SD_DEV_CTRL, &scratch_32);
 183         if (ret)
 184                 return;
 185         scratch_32 &= ~((1 << 12) | (1 << 13) | (1 << 14));
 186         pci_write_config_dword(chip->pdev, O2_SD_DEV_CTRL, scratch_32);
 187
 188         /* Enable Link abnormal reset generating Reset */
 189         ret = pci_read_config_dword(chip->pdev, O2_SD_MISC_REG5, &scratch_32);
 190         if (ret)
 191                 return;
 192         scratch_32 &= ~((1 << 19) | (1 << 11));
 193         scratch_32 |= (1 << 10);
 194         pci_write_config_dword(chip->pdev, O2_SD_MISC_REG5, scratch_32);
 195
 196         /* set card power over current protection */
 197         ret = pci_read_config_dword(chip->pdev, O2_SD_TEST_REG, &scratch_32);
 198         if (ret)
 199                 return;
 200         scratch_32 |= (1 << 4);
 201         pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32);
 202
 203         /* adjust the output delay for SD mode */
 204         pci_write_config_dword(chip->pdev, O2_SD_DELAY_CTRL, 0x00002492);
 205
 206         /* Set the output voltage setting of Aux 1.2v LDO */
 207         ret = pci_read_config_dword(chip->pdev, O2_SD_LD0_CTRL, &scratch_32);
 208         if (ret)
 209                 return;
 210         scratch_32 &= ~(3 << 12);
 211         pci_write_config_dword(chip->pdev, O2_SD_LD0_CTRL, scratch_32);
 212
 213         /* Set Max power supply capability of SD host */
 214         ret = pci_read_config_dword(chip->pdev, O2_SD_CAP_REG0, &scratch_32);
 215         if (ret)
 216                 return;
 217         scratch_32 &= ~(0x01FE);
 218         scratch_32 |= 0x00CC;
 219         pci_write_config_dword(chip->pdev, O2_SD_CAP_REG0, scratch_32);
 220         /* Set DLL Tuning Window */
 221         ret = pci_read_config_dword(chip->pdev,
 222                                     O2_SD_TUNING_CTRL, &scratch_32);
 223         if (ret)
 224                 return;
 225         scratch_32 &= ~(0x000000FF);
 226         scratch_32 |= 0x00000066;
 227         pci_write_config_dword(chip->pdev, O2_SD_TUNING_CTRL, scratch_32);
 228
 229         /* Set UHS2 T_EIDLE */
 230         ret = pci_read_config_dword(chip->pdev,
 231                                     O2_SD_UHS2_L1_CTRL, &scratch_32);
 232         if (ret)
 233                 return;
 234         scratch_32 &= ~(0x000000FC);
 235         scratch_32 |= 0x00000084;
 236         pci_write_config_dword(chip->pdev, O2_SD_UHS2_L1_CTRL, scratch_32);
 237
 238         /* Set UHS2 Termination */
 239         ret = pci_read_config_dword(chip->pdev, O2_SD_FUNC_REG3, &scratch_32);
 240         if (ret)
 241                 return;
 242         scratch_32 &= ~((1 << 21) | (1 << 30));
 243
 244         pci_write_config_dword(chip->pdev, O2_SD_FUNC_REG3, scratch_32);
 245
 246         /* Set L1 Entrance Timer */
 247         ret = pci_read_config_dword(chip->pdev, O2_SD_CAPS, &scratch_32);
 248         if (ret)
 249                 return;
 250         scratch_32 &= ~(0xf0000000);
 251         scratch_32 |= 0x30000000;
 252         pci_write_config_dword(chip->pdev, O2_SD_CAPS, scratch_32);
 253
 254         ret = pci_read_config_dword(chip->pdev,
 255                                     O2_SD_MISC_CTRL4, &scratch_32);
 256         if (ret)
 257                 return;
 258         scratch_32 &= ~(0x000f0000);
 259         scratch_32 |= 0x00080000;
 260         pci_write_config_dword(chip->pdev, O2_SD_MISC_CTRL4, scratch_32);
 261 }
 262
 263 static void sdhci_pci_o2_enable_msi(struct sdhci_pci_chip *chip,
 264                                     struct sdhci_host *host)
 265 {
 266         int ret;
 267
 268         ret = pci_find_capability(chip->pdev, PCI_CAP_ID_MSI);
 269         if (!ret) {
 270                 pr_info("%s: unsupport msi, use INTx irq\n",
 271                         mmc_hostname(host->mmc));
 272                 return;
 273         }
 274
 275         ret = pci_alloc_irq_vectors(chip->pdev, 1, 1,
 276                                     PCI_IRQ_MSI | PCI_IRQ_MSIX);
 277         if (ret < 0) {
 278                 pr_err("%s: enable PCI MSI failed, err=%d\n",
 279                        mmc_hostname(host->mmc), ret);
 280                 return;
 281         }
 282
 283         host->irq = pci_irq_vector(chip->pdev, 0);
 284 }
 285
 286 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot)
 287 {
 288         struct sdhci_pci_chip *chip;
 289         struct sdhci_host *host;
 290         u32 reg;
 291         int ret;
 292
 293         chip = slot->chip;
 294         host = slot->host;
 295         switch (chip->pdev->device) {
 296         case PCI_DEVICE_ID_O2_SDS0:
 297         case PCI_DEVICE_ID_O2_SEABIRD0:
 298         case PCI_DEVICE_ID_O2_SEABIRD1:
 299         case PCI_DEVICE_ID_O2_SDS1:
 300         case PCI_DEVICE_ID_O2_FUJIN2:
 301                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING);
 302                 if (reg & 0x1)
 303                         host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12;
 304
 305                 sdhci_pci_o2_enable_msi(chip, host);
 306
 307                 if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD0) {
 308                         ret = pci_read_config_dword(chip->pdev,
 309                                                     O2_SD_MISC_SETTING, &reg);
 310                         if (ret)
 311                                 return -EIO;
 312                         if (reg & (1 << 4)) {
 313                                 pr_info("%s: emmc 1.8v flag is set, force 1.8v signaling voltage\n",
 314                                         mmc_hostname(host->mmc));
 315                                 host->flags &= ~SDHCI_SIGNALING_330;
 316                                 host->flags |= SDHCI_SIGNALING_180;
 317                                 host->mmc->caps2 |= MMC_CAP2_NO_SD;
 318                                 host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
 319                         }
 320                 }
 321
 322                 host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning;
 323
 324                 if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2)
 325                         break;
 326                 /* set dll watch dog timer */
 327                 reg = sdhci_readl(host, O2_SD_VENDOR_SETTING2);
 328                 reg |= (1 << 12);
 329                 sdhci_writel(host, reg, O2_SD_VENDOR_SETTING2);
 330
 331                 break;
 332         default:
 333                 break;
 334         }
 335
 336         return 0;
 337 }
 338
 339 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip)
 340 {
 341         int ret;
 342         u8 scratch;
 343         u32 scratch_32;
 344
 345         switch (chip->pdev->device) {
 346         case PCI_DEVICE_ID_O2_8220:
 347         case PCI_DEVICE_ID_O2_8221:
 348         case PCI_DEVICE_ID_O2_8320:
 349         case PCI_DEVICE_ID_O2_8321:
 350                 /* This extra setup is required due to broken ADMA. */
 351                 ret = pci_read_config_byte(chip->pdev,
 352                                 O2_SD_LOCK_WP, &scratch);
 353                 if (ret)
 354                         return ret;
 355                 scratch &= 0x7f;
 356                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 357
 358                 /* Set Multi 3 to VCC3V# */
 359                 pci_write_config_byte(chip->pdev, O2_SD_MULTI_VCC3V, 0x08);
 360
 361                 /* Disable CLK_REQ# support after media DET */
 362                 ret = pci_read_config_byte(chip->pdev,
 363                                 O2_SD_CLKREQ, &scratch);
 364                 if (ret)
 365                         return ret;
 366                 scratch |= 0x20;
 367                 pci_write_config_byte(chip->pdev, O2_SD_CLKREQ, scratch);
 368
 369                 /* Choose capabilities, enable SDMA.  We have to write 0x01
 370                  * to the capabilities register first to unlock it.
 371                  */
 372                 ret = pci_read_config_byte(chip->pdev, O2_SD_CAPS, &scratch);
 373                 if (ret)
 374                         return ret;
 375                 scratch |= 0x01;
 376                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, scratch);
 377                 pci_write_config_byte(chip->pdev, O2_SD_CAPS, 0x73);
 378
 379                 /* Disable ADMA1/2 */
 380                 pci_write_config_byte(chip->pdev, O2_SD_ADMA1, 0x39);
 381                 pci_write_config_byte(chip->pdev, O2_SD_ADMA2, 0x08);
 382
 383                 /* Disable the infinite transfer mode */
 384                 ret = pci_read_config_byte(chip->pdev,
 385                                 O2_SD_INF_MOD, &scratch);
 386                 if (ret)
 387                         return ret;
 388                 scratch |= 0x08;
 389                 pci_write_config_byte(chip->pdev, O2_SD_INF_MOD, scratch);
 390
 391                 /* Lock WP */
 392                 ret = pci_read_config_byte(chip->pdev,
 393                                 O2_SD_LOCK_WP, &scratch);
 394                 if (ret)
 395                         return ret;
 396                 scratch |= 0x80;
 397                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 398                 break;
 399         case PCI_DEVICE_ID_O2_SDS0:
 400         case PCI_DEVICE_ID_O2_SDS1:
 401         case PCI_DEVICE_ID_O2_FUJIN2:
 402                 /* UnLock WP */
 403                 ret = pci_read_config_byte(chip->pdev,
 404                                 O2_SD_LOCK_WP, &scratch);
 405                 if (ret)
 406                         return ret;
 407
 408                 scratch &= 0x7f;
 409                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 410
 411                 /* DevId=8520 subId= 0x11 or 0x12  Type Chip support */
 412                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2) {
 413                         ret = pci_read_config_dword(chip->pdev,
 414                                                     O2_SD_FUNC_REG0,
 415                                                     &scratch_32);
 416                         scratch_32 = ((scratch_32 & 0xFF000000) >> 24);
 417
 418                         /* Check Whether subId is 0x11 or 0x12 */
 419                         if ((scratch_32 == 0x11) || (scratch_32 == 0x12)) {
 420                                 scratch_32 = 0x25100000;
 421
 422                                 o2_pci_set_baseclk(chip, scratch_32);
 423                                 ret = pci_read_config_dword(chip->pdev,
 424                                                             O2_SD_FUNC_REG4,
 425                                                             &scratch_32);
 426
 427                                 /* Enable Base Clk setting change */
 428                                 scratch_32 |= O2_SD_FREG4_ENABLE_CLK_SET;
 429                                 pci_write_config_dword(chip->pdev,
 430                                                        O2_SD_FUNC_REG4,
 431                                                        scratch_32);
 432
 433                                 /* Set Tuning Window to 4 */
 434                                 pci_write_config_byte(chip->pdev,
 435                                                       O2_SD_TUNING_CTRL, 0x44);
 436
 437                                 break;
 438                         }
 439                 }
 440
 441                 /* Enable 8520 led function */
 442                 o2_pci_led_enable(chip);
 443
 444                 /* Set timeout CLK */
 445                 ret = pci_read_config_dword(chip->pdev,
 446                                             O2_SD_CLK_SETTING, &scratch_32);
 447                 if (ret)
 448                         return ret;
 449
 450                 scratch_32 &= ~(0xFF00);
 451                 scratch_32 |= 0x07E0C800;
 452                 pci_write_config_dword(chip->pdev,
 453                                        O2_SD_CLK_SETTING, scratch_32);
 454
 455                 ret = pci_read_config_dword(chip->pdev,
 456                                             O2_SD_CLKREQ, &scratch_32);
 457                 if (ret)
 458                         return ret;
 459                 scratch_32 |= 0x3;
 460                 pci_write_config_dword(chip->pdev, O2_SD_CLKREQ, scratch_32);
 461
 462                 ret = pci_read_config_dword(chip->pdev,
 463                                             O2_SD_PLL_SETTING, &scratch_32);
 464                 if (ret)
 465                         return ret;
 466
 467                 scratch_32 &= ~(0x1F3F070E);
 468                 scratch_32 |= 0x18270106;
 469                 pci_write_config_dword(chip->pdev,
 470                                        O2_SD_PLL_SETTING, scratch_32);
 471
 472                 /* Disable UHS1 funciton */
 473                 ret = pci_read_config_dword(chip->pdev,
 474                                             O2_SD_CAP_REG2, &scratch_32);
 475                 if (ret)
 476                         return ret;
 477                 scratch_32 &= ~(0xE0);
 478                 pci_write_config_dword(chip->pdev,
 479                                        O2_SD_CAP_REG2, scratch_32);
 480
 481                 if (chip->pdev->device == PCI_DEVICE_ID_O2_FUJIN2)
 482                         sdhci_pci_o2_fujin2_pci_init(chip);
 483
 484                 /* Lock WP */
 485                 ret = pci_read_config_byte(chip->pdev,
 486                                            O2_SD_LOCK_WP, &scratch);
 487                 if (ret)
 488                         return ret;
 489                 scratch |= 0x80;
 490                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 491                 break;
 492         case PCI_DEVICE_ID_O2_SEABIRD0:
 493                 if (chip->pdev->revision == 0x01)
 494                         chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
 495                 /* fall through */
 496         case PCI_DEVICE_ID_O2_SEABIRD1:
 497                 /* UnLock WP */
 498                 ret = pci_read_config_byte(chip->pdev,
 499                                 O2_SD_LOCK_WP, &scratch);
 500                 if (ret)
 501                         return ret;
 502
 503                 scratch &= 0x7f;
 504                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 505
 506                 ret = pci_read_config_dword(chip->pdev,
 507                                             O2_SD_PLL_SETTING, &scratch_32);
 508
 509                 if ((scratch_32 & 0xff000000) == 0x01000000) {
 510                         scratch_32 &= 0x0000FFFF;
 511                         scratch_32 |= 0x1F340000;
 512
 513                         pci_write_config_dword(chip->pdev,
 514                                                O2_SD_PLL_SETTING, scratch_32);
 515                 } else {
 516                         scratch_32 &= 0x0000FFFF;
 517                         scratch_32 |= 0x25100000;
 518
 519                         pci_write_config_dword(chip->pdev,
 520                                                O2_SD_PLL_SETTING, scratch_32);
 521
 522                         ret = pci_read_config_dword(chip->pdev,
 523                                                     O2_SD_FUNC_REG4,
 524                                                     &scratch_32);
 525                         scratch_32 |= (1 << 22);
 526                         pci_write_config_dword(chip->pdev,
 527                                                O2_SD_FUNC_REG4, scratch_32);
 528                 }
 529
 530                 /* Set Tuning Windows to 5 */
 531                 pci_write_config_byte(chip->pdev,
 532                                 O2_SD_TUNING_CTRL, 0x55);
 533                 /* Lock WP */
 534                 ret = pci_read_config_byte(chip->pdev,
 535                                            O2_SD_LOCK_WP, &scratch);
 536                 if (ret)
 537                         return ret;
 538                 scratch |= 0x80;
 539                 pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch);
 540                 break;
 541         }
 542
 543         return 0;
 544 }
 545
 546 #ifdef CONFIG_PM_SLEEP
 547 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip)
 548 {
 549         sdhci_pci_o2_probe(chip);
 550         return sdhci_pci_resume_host(chip);
 551 }
 552 #endif