2 * PHY support for Xenon SDHC
4 * Copyright (C) 2016 Marvell, All Rights Reserved.
6 * Author: Hu Ziji <huziji@marvell.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation version 2.
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/ktime.h>
17 #include <linux/of_address.h>
19 #include "sdhci-pltfm.h"
20 #include "sdhci-xenon.h"
22 /* Register base for eMMC PHY 5.0 Version */
23 #define XENON_EMMC_5_0_PHY_REG_BASE 0x0160
24 /* Register base for eMMC PHY 5.1 Version */
25 #define XENON_EMMC_PHY_REG_BASE 0x0170
27 #define XENON_EMMC_PHY_TIMING_ADJUST XENON_EMMC_PHY_REG_BASE
28 #define XENON_EMMC_5_0_PHY_TIMING_ADJUST XENON_EMMC_5_0_PHY_REG_BASE
29 #define XENON_TIMING_ADJUST_SLOW_MODE BIT(29)
30 #define XENON_TIMING_ADJUST_SDIO_MODE BIT(28)
31 #define XENON_SAMPL_INV_QSP_PHASE_SELECT BIT(18)
32 #define XENON_SAMPL_INV_QSP_PHASE_SELECT_SHIFT 18
33 #define XENON_PHY_INITIALIZAION BIT(31)
34 #define XENON_WAIT_CYCLE_BEFORE_USING_MASK 0xF
35 #define XENON_WAIT_CYCLE_BEFORE_USING_SHIFT 12
36 #define XENON_FC_SYNC_EN_DURATION_MASK 0xF
37 #define XENON_FC_SYNC_EN_DURATION_SHIFT 8
38 #define XENON_FC_SYNC_RST_EN_DURATION_MASK 0xF
39 #define XENON_FC_SYNC_RST_EN_DURATION_SHIFT 4
40 #define XENON_FC_SYNC_RST_DURATION_MASK 0xF
41 #define XENON_FC_SYNC_RST_DURATION_SHIFT 0
43 #define XENON_EMMC_PHY_FUNC_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x4)
44 #define XENON_EMMC_5_0_PHY_FUNC_CONTROL \
45 (XENON_EMMC_5_0_PHY_REG_BASE + 0x4)
46 #define XENON_ASYNC_DDRMODE_MASK BIT(23)
47 #define XENON_ASYNC_DDRMODE_SHIFT 23
48 #define XENON_CMD_DDR_MODE BIT(16)
49 #define XENON_DQ_DDR_MODE_SHIFT 8
50 #define XENON_DQ_DDR_MODE_MASK 0xFF
51 #define XENON_DQ_ASYNC_MODE BIT(4)
53 #define XENON_EMMC_PHY_PAD_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x8)
54 #define XENON_EMMC_5_0_PHY_PAD_CONTROL \
55 (XENON_EMMC_5_0_PHY_REG_BASE + 0x8)
56 #define XENON_REC_EN_SHIFT 24
57 #define XENON_REC_EN_MASK 0xF
58 #define XENON_FC_DQ_RECEN BIT(24)
59 #define XENON_FC_CMD_RECEN BIT(25)
60 #define XENON_FC_QSP_RECEN BIT(26)
61 #define XENON_FC_QSN_RECEN BIT(27)
62 #define XENON_OEN_QSN BIT(28)
63 #define XENON_AUTO_RECEN_CTRL BIT(30)
64 #define XENON_FC_ALL_CMOS_RECEIVER 0xF000
66 #define XENON_EMMC5_FC_QSP_PD BIT(18)
67 #define XENON_EMMC5_FC_QSP_PU BIT(22)
68 #define XENON_EMMC5_FC_CMD_PD BIT(17)
69 #define XENON_EMMC5_FC_CMD_PU BIT(21)
70 #define XENON_EMMC5_FC_DQ_PD BIT(16)
71 #define XENON_EMMC5_FC_DQ_PU BIT(20)
73 #define XENON_EMMC_PHY_PAD_CONTROL1 (XENON_EMMC_PHY_REG_BASE + 0xC)
74 #define XENON_EMMC5_1_FC_QSP_PD BIT(9)
75 #define XENON_EMMC5_1_FC_QSP_PU BIT(25)
76 #define XENON_EMMC5_1_FC_CMD_PD BIT(8)
77 #define XENON_EMMC5_1_FC_CMD_PU BIT(24)
78 #define XENON_EMMC5_1_FC_DQ_PD 0xFF
79 #define XENON_EMMC5_1_FC_DQ_PU (0xFF << 16)
81 #define XENON_EMMC_PHY_PAD_CONTROL2 (XENON_EMMC_PHY_REG_BASE + 0x10)
82 #define XENON_EMMC_5_0_PHY_PAD_CONTROL2 \
83 (XENON_EMMC_5_0_PHY_REG_BASE + 0xC)
84 #define XENON_ZNR_MASK 0x1F
85 #define XENON_ZNR_SHIFT 8
86 #define XENON_ZPR_MASK 0x1F
87 /* Preferred ZNR and ZPR value vary between different boards.
88 * The specific ZNR and ZPR value should be defined here
89 * according to board actual timing.
91 #define XENON_ZNR_DEF_VALUE 0xF
92 #define XENON_ZPR_DEF_VALUE 0xF
94 #define XENON_EMMC_PHY_DLL_CONTROL (XENON_EMMC_PHY_REG_BASE + 0x14)
95 #define XENON_EMMC_5_0_PHY_DLL_CONTROL \
96 (XENON_EMMC_5_0_PHY_REG_BASE + 0x10)
97 #define XENON_DLL_ENABLE BIT(31)
98 #define XENON_DLL_UPDATE_STROBE_5_0 BIT(30)
99 #define XENON_DLL_REFCLK_SEL BIT(30)
100 #define XENON_DLL_UPDATE BIT(23)
101 #define XENON_DLL_PHSEL1_SHIFT 24
102 #define XENON_DLL_PHSEL0_SHIFT 16
103 #define XENON_DLL_PHASE_MASK 0x3F
104 #define XENON_DLL_PHASE_90_DEGREE 0x1F
105 #define XENON_DLL_FAST_LOCK BIT(5)
106 #define XENON_DLL_GAIN2X BIT(3)
107 #define XENON_DLL_BYPASS_EN BIT(0)
109 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST \
110 (XENON_EMMC_5_0_PHY_REG_BASE + 0x14)
111 #define XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE 0x5A54
112 #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18)
113 #define XENON_LOGIC_TIMING_VALUE 0x00AA8977
116 * List offset of PHY registers and some special register values
117 * in eMMC PHY 5.0 or eMMC PHY 5.1
119 struct xenon_emmc_phy_regs
{
120 /* Offset of Timing Adjust register */
122 /* Offset of Func Control register */
124 /* Offset of Pad Control register */
126 /* Offset of Pad Control register 2 */
128 /* Offset of DLL Control register */
130 /* Offset of Logic Timing Adjust register */
131 u16 logic_timing_adj
;
132 /* DLL Update Enable bit */
134 /* value in Logic Timing Adjustment register */
135 u32 logic_timing_val
;
138 static const char * const phy_types
[] = {
143 enum xenon_phy_type_enum
{
149 enum soc_pad_ctrl_type
{
154 struct soc_pad_ctrl
{
155 /* Register address of SoC PHY PAD ctrl */
157 /* SoC PHY PAD ctrl type */
158 enum soc_pad_ctrl_type pad_type
;
159 /* SoC specific operation to set SoC PHY PAD */
160 void (*set_soc_pad
)(struct sdhci_host
*host
,
161 unsigned char signal_voltage
);
164 static struct xenon_emmc_phy_regs xenon_emmc_5_0_phy_regs
= {
165 .timing_adj
= XENON_EMMC_5_0_PHY_TIMING_ADJUST
,
166 .func_ctrl
= XENON_EMMC_5_0_PHY_FUNC_CONTROL
,
167 .pad_ctrl
= XENON_EMMC_5_0_PHY_PAD_CONTROL
,
168 .pad_ctrl2
= XENON_EMMC_5_0_PHY_PAD_CONTROL2
,
169 .dll_ctrl
= XENON_EMMC_5_0_PHY_DLL_CONTROL
,
170 .logic_timing_adj
= XENON_EMMC_5_0_PHY_LOGIC_TIMING_ADJUST
,
171 .dll_update
= XENON_DLL_UPDATE_STROBE_5_0
,
172 .logic_timing_val
= XENON_EMMC_5_0_PHY_LOGIC_TIMING_VALUE
,
175 static struct xenon_emmc_phy_regs xenon_emmc_5_1_phy_regs
= {
176 .timing_adj
= XENON_EMMC_PHY_TIMING_ADJUST
,
177 .func_ctrl
= XENON_EMMC_PHY_FUNC_CONTROL
,
178 .pad_ctrl
= XENON_EMMC_PHY_PAD_CONTROL
,
179 .pad_ctrl2
= XENON_EMMC_PHY_PAD_CONTROL2
,
180 .dll_ctrl
= XENON_EMMC_PHY_DLL_CONTROL
,
181 .logic_timing_adj
= XENON_EMMC_PHY_LOGIC_TIMING_ADJUST
,
182 .dll_update
= XENON_DLL_UPDATE
,
183 .logic_timing_val
= XENON_LOGIC_TIMING_VALUE
,
187 * eMMC PHY configuration and operations
189 struct xenon_emmc_phy_params
{
195 /* Nr of consecutive Sampling Points of a Valid Sampling Window */
197 /* Divider for calculating Tuning Step */
200 struct soc_pad_ctrl pad_ctrl
;
203 static int xenon_alloc_emmc_phy(struct sdhci_host
*host
)
205 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
206 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
207 struct xenon_emmc_phy_params
*params
;
209 params
= devm_kzalloc(mmc_dev(host
->mmc
), sizeof(*params
), GFP_KERNEL
);
213 priv
->phy_params
= params
;
214 if (priv
->phy_type
== EMMC_5_0_PHY
)
215 priv
->emmc_phy_regs
= &xenon_emmc_5_0_phy_regs
;
217 priv
->emmc_phy_regs
= &xenon_emmc_5_1_phy_regs
;
223 * eMMC 5.0/5.1 PHY init/re-init.
224 * eMMC PHY init should be executed after:
225 * 1. SDCLK frequency changes.
226 * 2. SDCLK is stopped and re-enabled.
227 * 3. config in emmc_phy_regs->timing_adj and emmc_phy_regs->func_ctrl
230 static int xenon_emmc_phy_init(struct sdhci_host
*host
)
234 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
235 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
236 struct xenon_emmc_phy_regs
*phy_regs
= priv
->emmc_phy_regs
;
238 reg
= sdhci_readl(host
, phy_regs
->timing_adj
);
239 reg
|= XENON_PHY_INITIALIZAION
;
240 sdhci_writel(host
, reg
, phy_regs
->timing_adj
);
242 /* Add duration of FC_SYNC_RST */
243 wait
= ((reg
>> XENON_FC_SYNC_RST_DURATION_SHIFT
) &
244 XENON_FC_SYNC_RST_DURATION_MASK
);
245 /* Add interval between FC_SYNC_EN and FC_SYNC_RST */
246 wait
+= ((reg
>> XENON_FC_SYNC_RST_EN_DURATION_SHIFT
) &
247 XENON_FC_SYNC_RST_EN_DURATION_MASK
);
248 /* Add duration of asserting FC_SYNC_EN */
249 wait
+= ((reg
>> XENON_FC_SYNC_EN_DURATION_SHIFT
) &
250 XENON_FC_SYNC_EN_DURATION_MASK
);
251 /* Add duration of waiting for PHY */
252 wait
+= ((reg
>> XENON_WAIT_CYCLE_BEFORE_USING_SHIFT
) &
253 XENON_WAIT_CYCLE_BEFORE_USING_MASK
);
254 /* 4 additional bus clock and 4 AXI bus clock are required */
260 /* Use the possibly slowest bus frequency value */
261 clock
= XENON_LOWEST_SDCLK_FREQ
;
262 /* get the wait time */
265 /* wait for host eMMC PHY init completes */
268 reg
= sdhci_readl(host
, phy_regs
->timing_adj
);
269 reg
&= XENON_PHY_INITIALIZAION
;
271 dev_err(mmc_dev(host
->mmc
), "eMMC PHY init cannot complete after %d us\n",
279 #define ARMADA_3700_SOC_PAD_1_8V 0x1
280 #define ARMADA_3700_SOC_PAD_3_3V 0x0
282 static void armada_3700_soc_pad_voltage_set(struct sdhci_host
*host
,
283 unsigned char signal_voltage
)
285 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
286 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
287 struct xenon_emmc_phy_params
*params
= priv
->phy_params
;
289 if (params
->pad_ctrl
.pad_type
== SOC_PAD_FIXED_1_8V
) {
290 writel(ARMADA_3700_SOC_PAD_1_8V
, params
->pad_ctrl
.reg
);
291 } else if (params
->pad_ctrl
.pad_type
== SOC_PAD_SD
) {
292 if (signal_voltage
== MMC_SIGNAL_VOLTAGE_180
)
293 writel(ARMADA_3700_SOC_PAD_1_8V
, params
->pad_ctrl
.reg
);
294 else if (signal_voltage
== MMC_SIGNAL_VOLTAGE_330
)
295 writel(ARMADA_3700_SOC_PAD_3_3V
, params
->pad_ctrl
.reg
);
300 * Set SoC PHY voltage PAD control register,
301 * according to the operation voltage on PAD.
302 * The detailed operation depends on SoC implementation.
304 static void xenon_emmc_phy_set_soc_pad(struct sdhci_host
*host
,
305 unsigned char signal_voltage
)
307 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
308 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
309 struct xenon_emmc_phy_params
*params
= priv
->phy_params
;
311 if (!params
->pad_ctrl
.reg
)
314 if (params
->pad_ctrl
.set_soc_pad
)
315 params
->pad_ctrl
.set_soc_pad(host
, signal_voltage
);
319 * Enable eMMC PHY HW DLL
320 * DLL should be enabled and stable before HS200/SDR104 tuning,
321 * and before HS400 data strobe setting.
323 static int xenon_emmc_phy_enable_dll(struct sdhci_host
*host
)
326 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
327 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
328 struct xenon_emmc_phy_regs
*phy_regs
= priv
->emmc_phy_regs
;
331 if (WARN_ON(host
->clock
<= MMC_HIGH_52_MAX_DTR
))
334 reg
= sdhci_readl(host
, phy_regs
->dll_ctrl
);
335 if (reg
& XENON_DLL_ENABLE
)
339 reg
= sdhci_readl(host
, phy_regs
->dll_ctrl
);
340 reg
|= (XENON_DLL_ENABLE
| XENON_DLL_FAST_LOCK
);
343 * Set Phase as 90 degree, which is most common value.
344 * Might set another value if necessary.
345 * The granularity is 1 degree.
347 reg
&= ~((XENON_DLL_PHASE_MASK
<< XENON_DLL_PHSEL0_SHIFT
) |
348 (XENON_DLL_PHASE_MASK
<< XENON_DLL_PHSEL1_SHIFT
));
349 reg
|= ((XENON_DLL_PHASE_90_DEGREE
<< XENON_DLL_PHSEL0_SHIFT
) |
350 (XENON_DLL_PHASE_90_DEGREE
<< XENON_DLL_PHSEL1_SHIFT
));
352 reg
&= ~XENON_DLL_BYPASS_EN
;
353 reg
|= phy_regs
->dll_update
;
354 if (priv
->phy_type
== EMMC_5_1_PHY
)
355 reg
&= ~XENON_DLL_REFCLK_SEL
;
356 sdhci_writel(host
, reg
, phy_regs
->dll_ctrl
);
359 timeout
= ktime_add_ms(ktime_get(), 32);
360 while (!(sdhci_readw(host
, XENON_SLOT_EXT_PRESENT_STATE
) &
361 XENON_DLL_LOCK_STATE
)) {
362 if (ktime_after(ktime_get(), timeout
)) {
363 dev_err(mmc_dev(host
->mmc
), "Wait for DLL Lock time-out\n");
372 * Config to eMMC PHY to prepare for tuning.
373 * Enable HW DLL and set the TUNING_STEP
375 static int xenon_emmc_phy_config_tuning(struct sdhci_host
*host
)
377 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
378 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
379 struct xenon_emmc_phy_params
*params
= priv
->phy_params
;
380 u32 reg
, tuning_step
;
383 if (host
->clock
<= MMC_HIGH_52_MAX_DTR
)
386 ret
= xenon_emmc_phy_enable_dll(host
);
390 /* Achieve TUNING_STEP with HW DLL help */
391 reg
= sdhci_readl(host
, XENON_SLOT_DLL_CUR_DLY_VAL
);
392 tuning_step
= reg
/ params
->tun_step_divider
;
393 if (unlikely(tuning_step
> XENON_TUNING_STEP_MASK
)) {
394 dev_warn(mmc_dev(host
->mmc
),
395 "HS200 TUNING_STEP %d is larger than MAX value\n",
397 tuning_step
= XENON_TUNING_STEP_MASK
;
400 /* Set TUNING_STEP for later tuning */
401 reg
= sdhci_readl(host
, XENON_SLOT_OP_STATUS_CTRL
);
402 reg
&= ~(XENON_TUN_CONSECUTIVE_TIMES_MASK
<<
403 XENON_TUN_CONSECUTIVE_TIMES_SHIFT
);
404 reg
|= (params
->nr_tun_times
<< XENON_TUN_CONSECUTIVE_TIMES_SHIFT
);
405 reg
&= ~(XENON_TUNING_STEP_MASK
<< XENON_TUNING_STEP_SHIFT
);
406 reg
|= (tuning_step
<< XENON_TUNING_STEP_SHIFT
);
407 sdhci_writel(host
, reg
, XENON_SLOT_OP_STATUS_CTRL
);
412 static void xenon_emmc_phy_disable_strobe(struct sdhci_host
*host
)
414 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
415 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
418 /* Disable both SDHC Data Strobe and Enhanced Strobe */
419 reg
= sdhci_readl(host
, XENON_SLOT_EMMC_CTRL
);
420 reg
&= ~(XENON_ENABLE_DATA_STROBE
| XENON_ENABLE_RESP_STROBE
);
421 sdhci_writel(host
, reg
, XENON_SLOT_EMMC_CTRL
);
423 /* Clear Strobe line Pull down or Pull up */
424 if (priv
->phy_type
== EMMC_5_0_PHY
) {
425 reg
= sdhci_readl(host
, XENON_EMMC_5_0_PHY_PAD_CONTROL
);
426 reg
&= ~(XENON_EMMC5_FC_QSP_PD
| XENON_EMMC5_FC_QSP_PU
);
427 sdhci_writel(host
, reg
, XENON_EMMC_5_0_PHY_PAD_CONTROL
);
429 reg
= sdhci_readl(host
, XENON_EMMC_PHY_PAD_CONTROL1
);
430 reg
&= ~(XENON_EMMC5_1_FC_QSP_PD
| XENON_EMMC5_1_FC_QSP_PU
);
431 sdhci_writel(host
, reg
, XENON_EMMC_PHY_PAD_CONTROL1
);
435 /* Set HS400 Data Strobe and Enhanced Strobe */
436 static void xenon_emmc_phy_strobe_delay_adj(struct sdhci_host
*host
)
438 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
439 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
442 if (WARN_ON(host
->timing
!= MMC_TIMING_MMC_HS400
))
445 if (host
->clock
<= MMC_HIGH_52_MAX_DTR
)
448 dev_dbg(mmc_dev(host
->mmc
), "starts HS400 strobe delay adjustment\n");
450 xenon_emmc_phy_enable_dll(host
);
452 /* Enable SDHC Data Strobe */
453 reg
= sdhci_readl(host
, XENON_SLOT_EMMC_CTRL
);
454 reg
|= XENON_ENABLE_DATA_STROBE
;
456 * Enable SDHC Enhanced Strobe if supported
457 * Xenon Enhanced Strobe should be enabled only when
458 * 1. card is in HS400 mode and
459 * 2. SDCLK is higher than 52MHz
462 if (host
->mmc
->ios
.enhanced_strobe
)
463 reg
|= XENON_ENABLE_RESP_STROBE
;
464 sdhci_writel(host
, reg
, XENON_SLOT_EMMC_CTRL
);
466 /* Set Data Strobe Pull down */
467 if (priv
->phy_type
== EMMC_5_0_PHY
) {
468 reg
= sdhci_readl(host
, XENON_EMMC_5_0_PHY_PAD_CONTROL
);
469 reg
|= XENON_EMMC5_FC_QSP_PD
;
470 reg
&= ~XENON_EMMC5_FC_QSP_PU
;
471 sdhci_writel(host
, reg
, XENON_EMMC_5_0_PHY_PAD_CONTROL
);
473 reg
= sdhci_readl(host
, XENON_EMMC_PHY_PAD_CONTROL1
);
474 reg
|= XENON_EMMC5_1_FC_QSP_PD
;
475 reg
&= ~XENON_EMMC5_1_FC_QSP_PU
;
476 sdhci_writel(host
, reg
, XENON_EMMC_PHY_PAD_CONTROL1
);
481 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
482 * in SDR mode, enable Slow Mode to bypass eMMC PHY.
483 * SDIO slower SDR mode also requires Slow Mode.
485 * If Slow Mode is enabled, return true.
486 * Otherwise, return false.
488 static bool xenon_emmc_phy_slow_mode(struct sdhci_host
*host
,
489 unsigned char timing
)
491 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
492 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
493 struct xenon_emmc_phy_params
*params
= priv
->phy_params
;
494 struct xenon_emmc_phy_regs
*phy_regs
= priv
->emmc_phy_regs
;
498 if (host
->clock
> MMC_HIGH_52_MAX_DTR
)
501 reg
= sdhci_readl(host
, phy_regs
->timing_adj
);
502 /* When in slower SDR mode, enable Slow Mode for SDIO
503 * or when Slow Mode flag is set
506 case MMC_TIMING_LEGACY
:
508 * If Slow Mode is required, enable Slow Mode by default
509 * in early init phase to avoid any potential issue.
511 if (params
->slow_mode
) {
512 reg
|= XENON_TIMING_ADJUST_SLOW_MODE
;
515 reg
&= ~XENON_TIMING_ADJUST_SLOW_MODE
;
519 case MMC_TIMING_UHS_SDR25
:
520 case MMC_TIMING_UHS_SDR12
:
521 case MMC_TIMING_SD_HS
:
522 case MMC_TIMING_MMC_HS
:
523 if ((priv
->init_card_type
== MMC_TYPE_SDIO
) ||
525 reg
|= XENON_TIMING_ADJUST_SLOW_MODE
;
529 /* else: fall through */
531 reg
&= ~XENON_TIMING_ADJUST_SLOW_MODE
;
535 sdhci_writel(host
, reg
, phy_regs
->timing_adj
);
540 * Set-up eMMC 5.0/5.1 PHY.
541 * Specific configuration depends on the current speed mode in use.
543 static void xenon_emmc_phy_set(struct sdhci_host
*host
,
544 unsigned char timing
)
547 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
548 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
549 struct xenon_emmc_phy_params
*params
= priv
->phy_params
;
550 struct xenon_emmc_phy_regs
*phy_regs
= priv
->emmc_phy_regs
;
552 dev_dbg(mmc_dev(host
->mmc
), "eMMC PHY setting starts\n");
554 /* Setup pad, set bit[28] and bits[26:24] */
555 reg
= sdhci_readl(host
, phy_regs
->pad_ctrl
);
556 reg
|= (XENON_FC_DQ_RECEN
| XENON_FC_CMD_RECEN
|
557 XENON_FC_QSP_RECEN
| XENON_OEN_QSN
);
558 /* All FC_XX_RECEIVCE should be set as CMOS Type */
559 reg
|= XENON_FC_ALL_CMOS_RECEIVER
;
560 sdhci_writel(host
, reg
, phy_regs
->pad_ctrl
);
562 /* Set CMD and DQ Pull Up */
563 if (priv
->phy_type
== EMMC_5_0_PHY
) {
564 reg
= sdhci_readl(host
, XENON_EMMC_5_0_PHY_PAD_CONTROL
);
565 reg
|= (XENON_EMMC5_FC_CMD_PU
| XENON_EMMC5_FC_DQ_PU
);
566 reg
&= ~(XENON_EMMC5_FC_CMD_PD
| XENON_EMMC5_FC_DQ_PD
);
567 sdhci_writel(host
, reg
, XENON_EMMC_5_0_PHY_PAD_CONTROL
);
569 reg
= sdhci_readl(host
, XENON_EMMC_PHY_PAD_CONTROL1
);
570 reg
|= (XENON_EMMC5_1_FC_CMD_PU
| XENON_EMMC5_1_FC_DQ_PU
);
571 reg
&= ~(XENON_EMMC5_1_FC_CMD_PD
| XENON_EMMC5_1_FC_DQ_PD
);
572 sdhci_writel(host
, reg
, XENON_EMMC_PHY_PAD_CONTROL1
);
575 if (timing
== MMC_TIMING_LEGACY
) {
576 xenon_emmc_phy_slow_mode(host
, timing
);
581 * If SDIO card, set SDIO Mode
582 * Otherwise, clear SDIO Mode
584 reg
= sdhci_readl(host
, phy_regs
->timing_adj
);
585 if (priv
->init_card_type
== MMC_TYPE_SDIO
)
586 reg
|= XENON_TIMING_ADJUST_SDIO_MODE
;
588 reg
&= ~XENON_TIMING_ADJUST_SDIO_MODE
;
589 sdhci_writel(host
, reg
, phy_regs
->timing_adj
);
591 if (xenon_emmc_phy_slow_mode(host
, timing
))
595 * Set preferred ZNR and ZPR value
596 * The ZNR and ZPR value vary between different boards.
597 * Define them both in sdhci-xenon-emmc-phy.h.
599 reg
= sdhci_readl(host
, phy_regs
->pad_ctrl2
);
600 reg
&= ~((XENON_ZNR_MASK
<< XENON_ZNR_SHIFT
) | XENON_ZPR_MASK
);
601 reg
|= ((params
->znr
<< XENON_ZNR_SHIFT
) | params
->zpr
);
602 sdhci_writel(host
, reg
, phy_regs
->pad_ctrl2
);
605 * When setting EMMC_PHY_FUNC_CONTROL register,
606 * SD clock should be disabled
608 reg
= sdhci_readl(host
, SDHCI_CLOCK_CONTROL
);
609 reg
&= ~SDHCI_CLOCK_CARD_EN
;
610 sdhci_writew(host
, reg
, SDHCI_CLOCK_CONTROL
);
612 reg
= sdhci_readl(host
, phy_regs
->func_ctrl
);
614 case MMC_TIMING_MMC_HS400
:
615 reg
|= (XENON_DQ_DDR_MODE_MASK
<< XENON_DQ_DDR_MODE_SHIFT
) |
617 reg
&= ~XENON_DQ_ASYNC_MODE
;
619 case MMC_TIMING_UHS_DDR50
:
620 case MMC_TIMING_MMC_DDR52
:
621 reg
|= (XENON_DQ_DDR_MODE_MASK
<< XENON_DQ_DDR_MODE_SHIFT
) |
622 XENON_CMD_DDR_MODE
| XENON_DQ_ASYNC_MODE
;
625 reg
&= ~((XENON_DQ_DDR_MODE_MASK
<< XENON_DQ_DDR_MODE_SHIFT
) |
627 reg
|= XENON_DQ_ASYNC_MODE
;
629 sdhci_writel(host
, reg
, phy_regs
->func_ctrl
);
631 /* Enable bus clock */
632 reg
= sdhci_readl(host
, SDHCI_CLOCK_CONTROL
);
633 reg
|= SDHCI_CLOCK_CARD_EN
;
634 sdhci_writew(host
, reg
, SDHCI_CLOCK_CONTROL
);
636 if (timing
== MMC_TIMING_MMC_HS400
)
637 /* Hardware team recommend a value for HS400 */
638 sdhci_writel(host
, phy_regs
->logic_timing_val
,
639 phy_regs
->logic_timing_adj
);
641 xenon_emmc_phy_disable_strobe(host
);
644 xenon_emmc_phy_init(host
);
646 dev_dbg(mmc_dev(host
->mmc
), "eMMC PHY setting completes\n");
649 static int get_dt_pad_ctrl_data(struct sdhci_host
*host
,
650 struct device_node
*np
,
651 struct xenon_emmc_phy_params
*params
)
655 struct resource iomem
;
657 if (of_device_is_compatible(np
, "marvell,armada-3700-sdhci"))
658 params
->pad_ctrl
.set_soc_pad
= armada_3700_soc_pad_voltage_set
;
662 if (of_address_to_resource(np
, 1, &iomem
)) {
663 dev_err(mmc_dev(host
->mmc
), "Unable to find SoC PAD ctrl register address for %pOFn\n",
668 params
->pad_ctrl
.reg
= devm_ioremap_resource(mmc_dev(host
->mmc
),
670 if (IS_ERR(params
->pad_ctrl
.reg
))
671 return PTR_ERR(params
->pad_ctrl
.reg
);
673 ret
= of_property_read_string(np
, "marvell,pad-type", &name
);
675 dev_err(mmc_dev(host
->mmc
), "Unable to determine SoC PHY PAD ctrl type\n");
678 if (!strcmp(name
, "sd")) {
679 params
->pad_ctrl
.pad_type
= SOC_PAD_SD
;
680 } else if (!strcmp(name
, "fixed-1-8v")) {
681 params
->pad_ctrl
.pad_type
= SOC_PAD_FIXED_1_8V
;
683 dev_err(mmc_dev(host
->mmc
), "Unsupported SoC PHY PAD ctrl type %s\n",
691 static int xenon_emmc_phy_parse_param_dt(struct sdhci_host
*host
,
692 struct device_node
*np
,
693 struct xenon_emmc_phy_params
*params
)
697 params
->slow_mode
= false;
698 if (of_property_read_bool(np
, "marvell,xenon-phy-slow-mode"))
699 params
->slow_mode
= true;
701 params
->znr
= XENON_ZNR_DEF_VALUE
;
702 if (!of_property_read_u32(np
, "marvell,xenon-phy-znr", &value
))
703 params
->znr
= value
& XENON_ZNR_MASK
;
705 params
->zpr
= XENON_ZPR_DEF_VALUE
;
706 if (!of_property_read_u32(np
, "marvell,xenon-phy-zpr", &value
))
707 params
->zpr
= value
& XENON_ZPR_MASK
;
709 params
->nr_tun_times
= XENON_TUN_CONSECUTIVE_TIMES
;
710 if (!of_property_read_u32(np
, "marvell,xenon-phy-nr-success-tun",
712 params
->nr_tun_times
= value
& XENON_TUN_CONSECUTIVE_TIMES_MASK
;
714 params
->tun_step_divider
= XENON_TUNING_STEP_DIVIDER
;
715 if (!of_property_read_u32(np
, "marvell,xenon-phy-tun-step-divider",
717 params
->tun_step_divider
= value
& 0xFF;
719 return get_dt_pad_ctrl_data(host
, np
, params
);
722 /* Set SoC PHY Voltage PAD */
723 void xenon_soc_pad_ctrl(struct sdhci_host
*host
,
724 unsigned char signal_voltage
)
726 xenon_emmc_phy_set_soc_pad(host
, signal_voltage
);
730 * Setting PHY when card is working in High Speed Mode.
731 * HS400 set Data Strobe and Enhanced Strobe if it is supported.
732 * HS200/SDR104 set tuning config to prepare for tuning.
734 static int xenon_hs_delay_adj(struct sdhci_host
*host
)
738 if (WARN_ON(host
->clock
<= XENON_DEFAULT_SDCLK_FREQ
))
741 switch (host
->timing
) {
742 case MMC_TIMING_MMC_HS400
:
743 xenon_emmc_phy_strobe_delay_adj(host
);
745 case MMC_TIMING_MMC_HS200
:
746 case MMC_TIMING_UHS_SDR104
:
747 return xenon_emmc_phy_config_tuning(host
);
748 case MMC_TIMING_MMC_DDR52
:
749 case MMC_TIMING_UHS_DDR50
:
751 * DDR Mode requires driver to scan Sampling Fixed Delay Line,
752 * to find out a perfect operation sampling point.
753 * It is hard to implement such a scan in host driver
754 * since initiating commands by host driver is not safe.
755 * Thus so far just keep PHY Sampling Fixed Delay in
756 * default value of DDR mode.
758 * If any timing issue occurs in DDR mode on Marvell products,
759 * please contact maintainer for internal support in Marvell.
761 dev_warn_once(mmc_dev(host
->mmc
), "Timing issue might occur in DDR mode\n");
769 * Adjust PHY setting.
770 * PHY setting should be adjusted when SDCLK frequency, Bus Width
771 * or Speed Mode is changed.
772 * Additional config are required when card is working in High Speed mode,
773 * after leaving Legacy Mode.
775 int xenon_phy_adj(struct sdhci_host
*host
, struct mmc_ios
*ios
)
777 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
778 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
787 * The timing, frequency or bus width is changed,
788 * better to set eMMC PHY based on current setting
789 * and adjust Xenon SDHC delay.
791 if ((host
->clock
== priv
->clock
) &&
792 (ios
->bus_width
== priv
->bus_width
) &&
793 (ios
->timing
== priv
->timing
))
796 xenon_emmc_phy_set(host
, ios
->timing
);
798 /* Update the record */
799 priv
->bus_width
= ios
->bus_width
;
801 priv
->timing
= ios
->timing
;
802 priv
->clock
= host
->clock
;
804 /* Legacy mode is a special case */
805 if (ios
->timing
== MMC_TIMING_LEGACY
)
808 if (host
->clock
> XENON_DEFAULT_SDCLK_FREQ
)
809 ret
= xenon_hs_delay_adj(host
);
813 static int xenon_add_phy(struct device_node
*np
, struct sdhci_host
*host
,
814 const char *phy_name
)
816 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
817 struct xenon_priv
*priv
= sdhci_pltfm_priv(pltfm_host
);
820 priv
->phy_type
= match_string(phy_types
, NR_PHY_TYPES
, phy_name
);
821 if (priv
->phy_type
< 0) {
822 dev_err(mmc_dev(host
->mmc
),
823 "Unable to determine PHY name %s. Use default eMMC 5.1 PHY\n",
825 priv
->phy_type
= EMMC_5_1_PHY
;
828 ret
= xenon_alloc_emmc_phy(host
);
832 return xenon_emmc_phy_parse_param_dt(host
, np
, priv
->phy_params
);
835 int xenon_phy_parse_dt(struct device_node
*np
, struct sdhci_host
*host
)
837 const char *phy_type
= NULL
;
839 if (!of_property_read_string(np
, "marvell,xenon-phy-type", &phy_type
))
840 return xenon_add_phy(np
, host
, phy_type
);
842 return xenon_add_phy(np
, host
, "emmc 5.1 phy");