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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / net / ethernet / allwinner / sun4i-emac.c
blobe1acafa82214133044765421109a84ff2168dd91
1 /*
2 * Allwinner EMAC Fast Ethernet driver for Linux.
3 *
4 * Copyright 2012-2013 Stefan Roese <sr@denx.de>
5 * Copyright 2013 Maxime Ripard <maxime.ripard@free-electrons.com>
6 *
7 * Based on the Linux driver provided by Allwinner:
8 * Copyright (C) 1997 Sten Wang
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/gpio.h>
19 #include <linux/interrupt.h>
20 #include <linux/irq.h>
21 #include <linux/mii.h>
22 #include <linux/module.h>
23 #include <linux/netdevice.h>
24 #include <linux/of_address.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/of_platform.h>
29 #include <linux/platform_device.h>
30 #include <linux/phy.h>
31 #include <linux/soc/sunxi/sunxi_sram.h>
32
33 #include "sun4i-emac.h"
34
35 #define DRV_NAME "sun4i-emac"
36 #define DRV_VERSION "1.02"
37
38 #define EMAC_MAX_FRAME_LEN 0x0600
39
40 #define EMAC_DEFAULT_MSG_ENABLE 0x0000
41 static int debug = -1; /* defaults above */;
42 module_param(debug, int, 0);
43 MODULE_PARM_DESC(debug, "debug message flags");
44
45 /* Transmit timeout, default 5 seconds. */
46 static int watchdog = 5000;
47 module_param(watchdog, int, 0400);
48 MODULE_PARM_DESC(watchdog, "transmit timeout in milliseconds");
49
50 /* EMAC register address locking.
51 *
52 * The EMAC uses an address register to control where data written
53 * to the data register goes. This means that the address register
54 * must be preserved over interrupts or similar calls.
55 *
56 * During interrupt and other critical calls, a spinlock is used to
57 * protect the system, but the calls themselves save the address
58 * in the address register in case they are interrupting another
59 * access to the device.
60 *
61 * For general accesses a lock is provided so that calls which are
62 * allowed to sleep are serialised so that the address register does
63 * not need to be saved. This lock also serves to serialise access
64 * to the EEPROM and PHY access registers which are shared between
65 * these two devices.
66 */
67
68 /* The driver supports the original EMACE, and now the two newer
69 * devices, EMACA and EMACB.
70 */
71
72 struct emac_board_info {
73 struct clk *clk;
74 struct device *dev;
75 struct platform_device *pdev;
76 spinlock_t lock;
77 void __iomem *membase;
78 u32 msg_enable;
79 struct net_device *ndev;
80 struct sk_buff *skb_last;
81 u16 tx_fifo_stat;
82
83 int emacrx_completed_flag;
84
85 struct device_node *phy_node;
86 unsigned int link;
87 unsigned int speed;
88 unsigned int duplex;
89
90 phy_interface_t phy_interface;
91 };
92
93 static void emac_update_speed(struct net_device *dev)
94 {
95 struct emac_board_info *db = netdev_priv(dev);
96 unsigned int reg_val;
97
98 /* set EMAC SPEED, depend on PHY */
99 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG);
100 reg_val &= ~(0x1 << 8);
101 if (db->speed == SPEED_100)
102 reg_val |= 1 << 8;
103 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG);
104 }
105
106 static void emac_update_duplex(struct net_device *dev)
107 {
108 struct emac_board_info *db = netdev_priv(dev);
109 unsigned int reg_val;
110
111 /* set duplex depend on phy */
112 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
113 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN;
114 if (db->duplex)
115 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN;
116 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
117 }
118
119 static void emac_handle_link_change(struct net_device *dev)
120 {
121 struct emac_board_info *db = netdev_priv(dev);
122 struct phy_device *phydev = dev->phydev;
123 unsigned long flags;
124 int status_change = 0;
125
126 if (phydev->link) {
127 if (db->speed != phydev->speed) {
128 spin_lock_irqsave(&db->lock, flags);
129 db->speed = phydev->speed;
130 emac_update_speed(dev);
131 spin_unlock_irqrestore(&db->lock, flags);
132 status_change = 1;
133 }
134
135 if (db->duplex != phydev->duplex) {
136 spin_lock_irqsave(&db->lock, flags);
137 db->duplex = phydev->duplex;
138 emac_update_duplex(dev);
139 spin_unlock_irqrestore(&db->lock, flags);
140 status_change = 1;
141 }
142 }
143
144 if (phydev->link != db->link) {
145 if (!phydev->link) {
146 db->speed = 0;
147 db->duplex = -1;
148 }
149 db->link = phydev->link;
150
151 status_change = 1;
152 }
153
154 if (status_change)
155 phy_print_status(phydev);
156 }
157
158 static int emac_mdio_probe(struct net_device *dev)
159 {
160 struct emac_board_info *db = netdev_priv(dev);
161 struct phy_device *phydev;
162
163 /* to-do: PHY interrupts are currently not supported */
164
165 /* attach the mac to the phy */
166 phydev = of_phy_connect(db->ndev, db->phy_node,
167 &emac_handle_link_change, 0,
168 db->phy_interface);
169 if (!phydev) {
170 netdev_err(db->ndev, "could not find the PHY\n");
171 return -ENODEV;
172 }
173
174 /* mask with MAC supported features */
175 phy_set_max_speed(phydev, SPEED_100);
176
177 db->link = 0;
178 db->speed = 0;
179 db->duplex = -1;
180
181 return 0;
182 }
183
184 static void emac_mdio_remove(struct net_device *dev)
185 {
186 phy_disconnect(dev->phydev);
187 }
188
189 static void emac_reset(struct emac_board_info *db)
190 {
191 dev_dbg(db->dev, "resetting device\n");
192
193 /* RESET device */
194 writel(0, db->membase + EMAC_CTL_REG);
195 udelay(200);
196 writel(EMAC_CTL_RESET, db->membase + EMAC_CTL_REG);
197 udelay(200);
198 }
199
200 static void emac_outblk_32bit(void __iomem *reg, void *data, int count)
201 {
202 writesl(reg, data, round_up(count, 4) / 4);
203 }
204
205 static void emac_inblk_32bit(void __iomem *reg, void *data, int count)
206 {
207 readsl(reg, data, round_up(count, 4) / 4);
208 }
209
210 static int emac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
211 {
212 struct phy_device *phydev = dev->phydev;
213
214 if (!netif_running(dev))
215 return -EINVAL;
216
217 if (!phydev)
218 return -ENODEV;
219
220 return phy_mii_ioctl(phydev, rq, cmd);
221 }
222
223 /* ethtool ops */
224 static void emac_get_drvinfo(struct net_device *dev,
225 struct ethtool_drvinfo *info)
226 {
227 strlcpy(info->driver, DRV_NAME, sizeof(DRV_NAME));
228 strlcpy(info->version, DRV_VERSION, sizeof(DRV_VERSION));
229 strlcpy(info->bus_info, dev_name(&dev->dev), sizeof(info->bus_info));
230 }
231
232 static u32 emac_get_msglevel(struct net_device *dev)
233 {
234 struct emac_board_info *db = netdev_priv(dev);
235
236 return db->msg_enable;
237 }
238
239 static void emac_set_msglevel(struct net_device *dev, u32 value)
240 {
241 struct emac_board_info *db = netdev_priv(dev);
242
243 db->msg_enable = value;
244 }
245
246 static const struct ethtool_ops emac_ethtool_ops = {
247 .get_drvinfo = emac_get_drvinfo,
248 .get_link = ethtool_op_get_link,
249 .get_link_ksettings = phy_ethtool_get_link_ksettings,
250 .set_link_ksettings = phy_ethtool_set_link_ksettings,
251 .get_msglevel = emac_get_msglevel,
252 .set_msglevel = emac_set_msglevel,
253 };
254
255 static unsigned int emac_setup(struct net_device *ndev)
256 {
257 struct emac_board_info *db = netdev_priv(ndev);
258 unsigned int reg_val;
259
260 /* set up TX */
261 reg_val = readl(db->membase + EMAC_TX_MODE_REG);
262
263 writel(reg_val | EMAC_TX_MODE_ABORTED_FRAME_EN,
264 db->membase + EMAC_TX_MODE_REG);
265
266 /* set MAC */
267 /* set MAC CTL0 */
268 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
269 writel(reg_val | EMAC_MAC_CTL0_RX_FLOW_CTL_EN |
270 EMAC_MAC_CTL0_TX_FLOW_CTL_EN,
271 db->membase + EMAC_MAC_CTL0_REG);
272
273 /* set MAC CTL1 */
274 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG);
275 reg_val |= EMAC_MAC_CTL1_LEN_CHECK_EN;
276 reg_val |= EMAC_MAC_CTL1_CRC_EN;
277 reg_val |= EMAC_MAC_CTL1_PAD_EN;
278 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG);
279
280 /* set up IPGT */
281 writel(EMAC_MAC_IPGT_FULL_DUPLEX, db->membase + EMAC_MAC_IPGT_REG);
282
283 /* set up IPGR */
284 writel((EMAC_MAC_IPGR_IPG1 << 8) | EMAC_MAC_IPGR_IPG2,
285 db->membase + EMAC_MAC_IPGR_REG);
286
287 /* set up Collison window */
288 writel((EMAC_MAC_CLRT_COLLISION_WINDOW << 8) | EMAC_MAC_CLRT_RM,
289 db->membase + EMAC_MAC_CLRT_REG);
290
291 /* set up Max Frame Length */
292 writel(EMAC_MAX_FRAME_LEN,
293 db->membase + EMAC_MAC_MAXF_REG);
294
295 return 0;
296 }
297
298 static void emac_set_rx_mode(struct net_device *ndev)
299 {
300 struct emac_board_info *db = netdev_priv(ndev);
301 unsigned int reg_val;
302
303 /* set up RX */
304 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
305
306 if (ndev->flags & IFF_PROMISC)
307 reg_val |= EMAC_RX_CTL_PASS_ALL_EN;
308 else
309 reg_val &= ~EMAC_RX_CTL_PASS_ALL_EN;
310
311 writel(reg_val | EMAC_RX_CTL_PASS_LEN_OOR_EN |
312 EMAC_RX_CTL_ACCEPT_UNICAST_EN | EMAC_RX_CTL_DA_FILTER_EN |
313 EMAC_RX_CTL_ACCEPT_MULTICAST_EN |
314 EMAC_RX_CTL_ACCEPT_BROADCAST_EN,
315 db->membase + EMAC_RX_CTL_REG);
316 }
317
318 static unsigned int emac_powerup(struct net_device *ndev)
319 {
320 struct emac_board_info *db = netdev_priv(ndev);
321 unsigned int reg_val;
322
323 /* initial EMAC */
324 /* flush RX FIFO */
325 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
326 reg_val |= 0x8;
327 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
328 udelay(1);
329
330 /* initial MAC */
331 /* soft reset MAC */
332 reg_val = readl(db->membase + EMAC_MAC_CTL0_REG);
333 reg_val &= ~EMAC_MAC_CTL0_SOFT_RESET;
334 writel(reg_val, db->membase + EMAC_MAC_CTL0_REG);
335
336 /* set MII clock */
337 reg_val = readl(db->membase + EMAC_MAC_MCFG_REG);
338 reg_val &= (~(0xf << 2));
339 reg_val |= (0xD << 2);
340 writel(reg_val, db->membase + EMAC_MAC_MCFG_REG);
341
342 /* clear RX counter */
343 writel(0x0, db->membase + EMAC_RX_FBC_REG);
344
345 /* disable all interrupt and clear interrupt status */
346 writel(0, db->membase + EMAC_INT_CTL_REG);
347 reg_val = readl(db->membase + EMAC_INT_STA_REG);
348 writel(reg_val, db->membase + EMAC_INT_STA_REG);
349
350 udelay(1);
351
352 /* set up EMAC */
353 emac_setup(ndev);
354
355 /* set mac_address to chip */
356 writel(ndev->dev_addr[0] << 16 | ndev->dev_addr[1] << 8 | ndev->
357 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
358 writel(ndev->dev_addr[3] << 16 | ndev->dev_addr[4] << 8 | ndev->
359 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
360
361 mdelay(1);
362
363 return 0;
364 }
365
366 static int emac_set_mac_address(struct net_device *dev, void *p)
367 {
368 struct sockaddr *addr = p;
369 struct emac_board_info *db = netdev_priv(dev);
370
371 if (netif_running(dev))
372 return -EBUSY;
373
374 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
375
376 writel(dev->dev_addr[0] << 16 | dev->dev_addr[1] << 8 | dev->
377 dev_addr[2], db->membase + EMAC_MAC_A1_REG);
378 writel(dev->dev_addr[3] << 16 | dev->dev_addr[4] << 8 | dev->
379 dev_addr[5], db->membase + EMAC_MAC_A0_REG);
380
381 return 0;
382 }
383
384 /* Initialize emac board */
385 static void emac_init_device(struct net_device *dev)
386 {
387 struct emac_board_info *db = netdev_priv(dev);
388 unsigned long flags;
389 unsigned int reg_val;
390
391 spin_lock_irqsave(&db->lock, flags);
392
393 emac_update_speed(dev);
394 emac_update_duplex(dev);
395
396 /* enable RX/TX */
397 reg_val = readl(db->membase + EMAC_CTL_REG);
398 writel(reg_val | EMAC_CTL_RESET | EMAC_CTL_TX_EN | EMAC_CTL_RX_EN,
399 db->membase + EMAC_CTL_REG);
400
401 /* enable RX/TX0/RX Hlevel interrup */
402 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
403 reg_val |= (0xf << 0) | (0x01 << 8);
404 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
405
406 spin_unlock_irqrestore(&db->lock, flags);
407 }
408
409 /* Our watchdog timed out. Called by the networking layer */
410 static void emac_timeout(struct net_device *dev)
411 {
412 struct emac_board_info *db = netdev_priv(dev);
413 unsigned long flags;
414
415 if (netif_msg_timer(db))
416 dev_err(db->dev, "tx time out.\n");
417
418 /* Save previous register address */
419 spin_lock_irqsave(&db->lock, flags);
420
421 netif_stop_queue(dev);
422 emac_reset(db);
423 emac_init_device(dev);
424 /* We can accept TX packets again */
425 netif_trans_update(dev);
426 netif_wake_queue(dev);
427
428 /* Restore previous register address */
429 spin_unlock_irqrestore(&db->lock, flags);
430 }
431
432 /* Hardware start transmission.
433 * Send a packet to media from the upper layer.
434 */
435 static int emac_start_xmit(struct sk_buff *skb, struct net_device *dev)
436 {
437 struct emac_board_info *db = netdev_priv(dev);
438 unsigned long channel;
439 unsigned long flags;
440
441 channel = db->tx_fifo_stat & 3;
442 if (channel == 3)
443 return 1;
444
445 channel = (channel == 1 ? 1 : 0);
446
447 spin_lock_irqsave(&db->lock, flags);
448
449 writel(channel, db->membase + EMAC_TX_INS_REG);
450
451 emac_outblk_32bit(db->membase + EMAC_TX_IO_DATA_REG,
452 skb->data, skb->len);
453 dev->stats.tx_bytes += skb->len;
454
455 db->tx_fifo_stat |= 1 << channel;
456 /* TX control: First packet immediately send, second packet queue */
457 if (channel == 0) {
458 /* set TX len */
459 writel(skb->len, db->membase + EMAC_TX_PL0_REG);
460 /* start translate from fifo to phy */
461 writel(readl(db->membase + EMAC_TX_CTL0_REG) | 1,
462 db->membase + EMAC_TX_CTL0_REG);
463
464 /* save the time stamp */
465 netif_trans_update(dev);
466 } else if (channel == 1) {
467 /* set TX len */
468 writel(skb->len, db->membase + EMAC_TX_PL1_REG);
469 /* start translate from fifo to phy */
470 writel(readl(db->membase + EMAC_TX_CTL1_REG) | 1,
471 db->membase + EMAC_TX_CTL1_REG);
472
473 /* save the time stamp */
474 netif_trans_update(dev);
475 }
476
477 if ((db->tx_fifo_stat & 3) == 3) {
478 /* Second packet */
479 netif_stop_queue(dev);
480 }
481
482 spin_unlock_irqrestore(&db->lock, flags);
483
484 /* free this SKB */
485 dev_consume_skb_any(skb);
486
487 return NETDEV_TX_OK;
488 }
489
490 /* EMAC interrupt handler
491 * receive the packet to upper layer, free the transmitted packet
492 */
493 static void emac_tx_done(struct net_device *dev, struct emac_board_info *db,
494 unsigned int tx_status)
495 {
496 /* One packet sent complete */
497 db->tx_fifo_stat &= ~(tx_status & 3);
498 if (3 == (tx_status & 3))
499 dev->stats.tx_packets += 2;
500 else
501 dev->stats.tx_packets++;
502
503 if (netif_msg_tx_done(db))
504 dev_dbg(db->dev, "tx done, NSR %02x\n", tx_status);
505
506 netif_wake_queue(dev);
507 }
508
509 /* Received a packet and pass to upper layer
510 */
511 static void emac_rx(struct net_device *dev)
512 {
513 struct emac_board_info *db = netdev_priv(dev);
514 struct sk_buff *skb;
515 u8 *rdptr;
516 bool good_packet;
517 static int rxlen_last;
518 unsigned int reg_val;
519 u32 rxhdr, rxstatus, rxcount, rxlen;
520
521 /* Check packet ready or not */
522 while (1) {
523 /* race warning: the first packet might arrive with
524 * the interrupts disabled, but the second will fix
525 * it
526 */
527 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
528
529 if (netif_msg_rx_status(db))
530 dev_dbg(db->dev, "RXCount: %x\n", rxcount);
531
532 if ((db->skb_last != NULL) && (rxlen_last > 0)) {
533 dev->stats.rx_bytes += rxlen_last;
534
535 /* Pass to upper layer */
536 db->skb_last->protocol = eth_type_trans(db->skb_last,
537 dev);
538 netif_rx(db->skb_last);
539 dev->stats.rx_packets++;
540 db->skb_last = NULL;
541 rxlen_last = 0;
542
543 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
544 reg_val &= ~EMAC_RX_CTL_DMA_EN;
545 writel(reg_val, db->membase + EMAC_RX_CTL_REG);
546 }
547
548 if (!rxcount) {
549 db->emacrx_completed_flag = 1;
550 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
551 reg_val |= (0xf << 0) | (0x01 << 8);
552 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
553
554 /* had one stuck? */
555 rxcount = readl(db->membase + EMAC_RX_FBC_REG);
556 if (!rxcount)
557 return;
558 }
559
560 reg_val = readl(db->membase + EMAC_RX_IO_DATA_REG);
561 if (netif_msg_rx_status(db))
562 dev_dbg(db->dev, "receive header: %x\n", reg_val);
563 if (reg_val != EMAC_UNDOCUMENTED_MAGIC) {
564 /* disable RX */
565 reg_val = readl(db->membase + EMAC_CTL_REG);
566 writel(reg_val & ~EMAC_CTL_RX_EN,
567 db->membase + EMAC_CTL_REG);
568
569 /* Flush RX FIFO */
570 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
571 writel(reg_val | (1 << 3),
572 db->membase + EMAC_RX_CTL_REG);
573
574 do {
575 reg_val = readl(db->membase + EMAC_RX_CTL_REG);
576 } while (reg_val & (1 << 3));
577
578 /* enable RX */
579 reg_val = readl(db->membase + EMAC_CTL_REG);
580 writel(reg_val | EMAC_CTL_RX_EN,
581 db->membase + EMAC_CTL_REG);
582 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
583 reg_val |= (0xf << 0) | (0x01 << 8);
584 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
585
586 db->emacrx_completed_flag = 1;
587
588 return;
589 }
590
591 /* A packet ready now & Get status/length */
592 good_packet = true;
593
594 rxhdr = readl(db->membase + EMAC_RX_IO_DATA_REG);
595
596 if (netif_msg_rx_status(db))
597 dev_dbg(db->dev, "rxhdr: %x\n", *((int *)(&rxhdr)));
598
599 rxlen = EMAC_RX_IO_DATA_LEN(rxhdr);
600 rxstatus = EMAC_RX_IO_DATA_STATUS(rxhdr);
601
602 if (netif_msg_rx_status(db))
603 dev_dbg(db->dev, "RX: status %02x, length %04x\n",
604 rxstatus, rxlen);
605
606 /* Packet Status check */
607 if (rxlen < 0x40) {
608 good_packet = false;
609 if (netif_msg_rx_err(db))
610 dev_dbg(db->dev, "RX: Bad Packet (runt)\n");
611 }
612
613 if (unlikely(!(rxstatus & EMAC_RX_IO_DATA_STATUS_OK))) {
614 good_packet = false;
615
616 if (rxstatus & EMAC_RX_IO_DATA_STATUS_CRC_ERR) {
617 if (netif_msg_rx_err(db))
618 dev_dbg(db->dev, "crc error\n");
619 dev->stats.rx_crc_errors++;
620 }
621
622 if (rxstatus & EMAC_RX_IO_DATA_STATUS_LEN_ERR) {
623 if (netif_msg_rx_err(db))
624 dev_dbg(db->dev, "length error\n");
625 dev->stats.rx_length_errors++;
626 }
627 }
628
629 /* Move data from EMAC */
630 if (good_packet) {
631 skb = netdev_alloc_skb(dev, rxlen + 4);
632 if (!skb)
633 continue;
634 skb_reserve(skb, 2);
635 rdptr = skb_put(skb, rxlen - 4);
636
637 /* Read received packet from RX SRAM */
638 if (netif_msg_rx_status(db))
639 dev_dbg(db->dev, "RxLen %x\n", rxlen);
640
641 emac_inblk_32bit(db->membase + EMAC_RX_IO_DATA_REG,
642 rdptr, rxlen);
643 dev->stats.rx_bytes += rxlen;
644
645 /* Pass to upper layer */
646 skb->protocol = eth_type_trans(skb, dev);
647 netif_rx(skb);
648 dev->stats.rx_packets++;
649 }
650 }
651 }
652
653 static irqreturn_t emac_interrupt(int irq, void *dev_id)
654 {
655 struct net_device *dev = dev_id;
656 struct emac_board_info *db = netdev_priv(dev);
657 int int_status;
658 unsigned long flags;
659 unsigned int reg_val;
660
661 /* A real interrupt coming */
662
663 /* holders of db->lock must always block IRQs */
664 spin_lock_irqsave(&db->lock, flags);
665
666 /* Disable all interrupts */
667 writel(0, db->membase + EMAC_INT_CTL_REG);
668
669 /* Got EMAC interrupt status */
670 /* Got ISR */
671 int_status = readl(db->membase + EMAC_INT_STA_REG);
672 /* Clear ISR status */
673 writel(int_status, db->membase + EMAC_INT_STA_REG);
674
675 if (netif_msg_intr(db))
676 dev_dbg(db->dev, "emac interrupt %02x\n", int_status);
677
678 /* Received the coming packet */
679 if ((int_status & 0x100) && (db->emacrx_completed_flag == 1)) {
680 /* carrier lost */
681 db->emacrx_completed_flag = 0;
682 emac_rx(dev);
683 }
684
685 /* Transmit Interrupt check */
686 if (int_status & (0x01 | 0x02))
687 emac_tx_done(dev, db, int_status);
688
689 if (int_status & (0x04 | 0x08))
690 netdev_info(dev, " ab : %x\n", int_status);
691
692 /* Re-enable interrupt mask */
693 if (db->emacrx_completed_flag == 1) {
694 reg_val = readl(db->membase + EMAC_INT_CTL_REG);
695 reg_val |= (0xf << 0) | (0x01 << 8);
696 writel(reg_val, db->membase + EMAC_INT_CTL_REG);
697 }
698 spin_unlock_irqrestore(&db->lock, flags);
699
700 return IRQ_HANDLED;
701 }
702
703 #ifdef CONFIG_NET_POLL_CONTROLLER
704 /*
705 * Used by netconsole
706 */
707 static void emac_poll_controller(struct net_device *dev)
708 {
709 disable_irq(dev->irq);
710 emac_interrupt(dev->irq, dev);
711 enable_irq(dev->irq);
712 }
713 #endif
714
715 /* Open the interface.
716 * The interface is opened whenever "ifconfig" actives it.
717 */
718 static int emac_open(struct net_device *dev)
719 {
720 struct emac_board_info *db = netdev_priv(dev);
721 int ret;
722
723 if (netif_msg_ifup(db))
724 dev_dbg(db->dev, "enabling %s\n", dev->name);
725
726 if (request_irq(dev->irq, &emac_interrupt, 0, dev->name, dev))
727 return -EAGAIN;
728
729 /* Initialize EMAC board */
730 emac_reset(db);
731 emac_init_device(dev);
732
733 ret = emac_mdio_probe(dev);
734 if (ret < 0) {
735 free_irq(dev->irq, dev);
736 netdev_err(dev, "cannot probe MDIO bus\n");
737 return ret;
738 }
739
740 phy_start(dev->phydev);
741 netif_start_queue(dev);
742
743 return 0;
744 }
745
746 static void emac_shutdown(struct net_device *dev)
747 {
748 unsigned int reg_val;
749 struct emac_board_info *db = netdev_priv(dev);
750
751 /* Disable all interrupt */
752 writel(0, db->membase + EMAC_INT_CTL_REG);
753
754 /* clear interrupt status */
755 reg_val = readl(db->membase + EMAC_INT_STA_REG);
756 writel(reg_val, db->membase + EMAC_INT_STA_REG);
757
758 /* Disable RX/TX */
759 reg_val = readl(db->membase + EMAC_CTL_REG);
760 reg_val &= ~(EMAC_CTL_TX_EN | EMAC_CTL_RX_EN | EMAC_CTL_RESET);
761 writel(reg_val, db->membase + EMAC_CTL_REG);
762 }
763
764 /* Stop the interface.
765 * The interface is stopped when it is brought.
766 */
767 static int emac_stop(struct net_device *ndev)
768 {
769 struct emac_board_info *db = netdev_priv(ndev);
770
771 if (netif_msg_ifdown(db))
772 dev_dbg(db->dev, "shutting down %s\n", ndev->name);
773
774 netif_stop_queue(ndev);
775 netif_carrier_off(ndev);
776
777 phy_stop(ndev->phydev);
778
779 emac_mdio_remove(ndev);
780
781 emac_shutdown(ndev);
782
783 free_irq(ndev->irq, ndev);
784
785 return 0;
786 }
787
788 static const struct net_device_ops emac_netdev_ops = {
789 .ndo_open = emac_open,
790 .ndo_stop = emac_stop,
791 .ndo_start_xmit = emac_start_xmit,
792 .ndo_tx_timeout = emac_timeout,
793 .ndo_set_rx_mode = emac_set_rx_mode,
794 .ndo_do_ioctl = emac_ioctl,
795 .ndo_validate_addr = eth_validate_addr,
796 .ndo_set_mac_address = emac_set_mac_address,
797 #ifdef CONFIG_NET_POLL_CONTROLLER
798 .ndo_poll_controller = emac_poll_controller,
799 #endif
800 };
801
802 /* Search EMAC board, allocate space and register it
803 */
804 static int emac_probe(struct platform_device *pdev)
805 {
806 struct device_node *np = pdev->dev.of_node;
807 struct emac_board_info *db;
808 struct net_device *ndev;
809 int ret = 0;
810 const char *mac_addr;
811
812 ndev = alloc_etherdev(sizeof(struct emac_board_info));
813 if (!ndev) {
814 dev_err(&pdev->dev, "could not allocate device.\n");
815 return -ENOMEM;
816 }
817
818 SET_NETDEV_DEV(ndev, &pdev->dev);
819
820 db = netdev_priv(ndev);
821 memset(db, 0, sizeof(*db));
822
823 db->dev = &pdev->dev;
824 db->ndev = ndev;
825 db->pdev = pdev;
826 db->msg_enable = netif_msg_init(debug, EMAC_DEFAULT_MSG_ENABLE);
827
828 spin_lock_init(&db->lock);
829
830 db->membase = of_iomap(np, 0);
831 if (!db->membase) {
832 dev_err(&pdev->dev, "failed to remap registers\n");
833 ret = -ENOMEM;
834 goto out;
835 }
836
837 /* fill in parameters for net-dev structure */
838 ndev->base_addr = (unsigned long)db->membase;
839 ndev->irq = irq_of_parse_and_map(np, 0);
840 if (ndev->irq == -ENXIO) {
841 netdev_err(ndev, "No irq resource\n");
842 ret = ndev->irq;
843 goto out_iounmap;
844 }
845
846 db->clk = devm_clk_get(&pdev->dev, NULL);
847 if (IS_ERR(db->clk)) {
848 ret = PTR_ERR(db->clk);
849 goto out_iounmap;
850 }
851
852 ret = clk_prepare_enable(db->clk);
853 if (ret) {
854 dev_err(&pdev->dev, "Error couldn't enable clock (%d)\n", ret);
855 goto out_iounmap;
856 }
857
858 ret = sunxi_sram_claim(&pdev->dev);
859 if (ret) {
860 dev_err(&pdev->dev, "Error couldn't map SRAM to device\n");
861 goto out_clk_disable_unprepare;
862 }
863
864 db->phy_node = of_parse_phandle(np, "phy", 0);
865 if (!db->phy_node) {
866 dev_err(&pdev->dev, "no associated PHY\n");
867 ret = -ENODEV;
868 goto out_release_sram;
869 }
870
871 /* Read MAC-address from DT */
872 mac_addr = of_get_mac_address(np);
873 if (mac_addr)
874 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
875
876 /* Check if the MAC address is valid, if not get a random one */
877 if (!is_valid_ether_addr(ndev->dev_addr)) {
878 eth_hw_addr_random(ndev);
879 dev_warn(&pdev->dev, "using random MAC address %pM\n",
880 ndev->dev_addr);
881 }
882
883 db->emacrx_completed_flag = 1;
884 emac_powerup(ndev);
885 emac_reset(db);
886
887 ndev->netdev_ops = &emac_netdev_ops;
888 ndev->watchdog_timeo = msecs_to_jiffies(watchdog);
889 ndev->ethtool_ops = &emac_ethtool_ops;
890
891 platform_set_drvdata(pdev, ndev);
892
893 /* Carrier starts down, phylib will bring it up */
894 netif_carrier_off(ndev);
895
896 ret = register_netdev(ndev);
897 if (ret) {
898 dev_err(&pdev->dev, "Registering netdev failed!\n");
899 ret = -ENODEV;
900 goto out_release_sram;
901 }
902
903 dev_info(&pdev->dev, "%s: at %p, IRQ %d MAC: %pM\n",
904 ndev->name, db->membase, ndev->irq, ndev->dev_addr);
905
906 return 0;
907
908 out_release_sram:
909 sunxi_sram_release(&pdev->dev);
910 out_clk_disable_unprepare:
911 clk_disable_unprepare(db->clk);
912 out_iounmap:
913 iounmap(db->membase);
914 out:
915 dev_err(db->dev, "not found (%d).\n", ret);
916
917 free_netdev(ndev);
918
919 return ret;
920 }
921
922 static int emac_remove(struct platform_device *pdev)
923 {
924 struct net_device *ndev = platform_get_drvdata(pdev);
925 struct emac_board_info *db = netdev_priv(ndev);
926
927 unregister_netdev(ndev);
928 sunxi_sram_release(&pdev->dev);
929 clk_disable_unprepare(db->clk);
930 iounmap(db->membase);
931 free_netdev(ndev);
932
933 dev_dbg(&pdev->dev, "released and freed device\n");
934 return 0;
935 }
936
937 static int emac_suspend(struct platform_device *dev, pm_message_t state)
938 {
939 struct net_device *ndev = platform_get_drvdata(dev);
940
941 netif_carrier_off(ndev);
942 netif_device_detach(ndev);
943 emac_shutdown(ndev);
944
945 return 0;
946 }
947
948 static int emac_resume(struct platform_device *dev)
949 {
950 struct net_device *ndev = platform_get_drvdata(dev);
951 struct emac_board_info *db = netdev_priv(ndev);
952
953 emac_reset(db);
954 emac_init_device(ndev);
955 netif_device_attach(ndev);
956
957 return 0;
958 }
959
960 static const struct of_device_id emac_of_match[] = {
961 {.compatible = "allwinner,sun4i-a10-emac",},
962
963 /* Deprecated */
964 {.compatible = "allwinner,sun4i-emac",},
965 {},
966 };
967
968 MODULE_DEVICE_TABLE(of, emac_of_match);
969
970 static struct platform_driver emac_driver = {
971 .driver = {
972 .name = "sun4i-emac",
973 .of_match_table = emac_of_match,
974 },
975 .probe = emac_probe,
976 .remove = emac_remove,
977 .suspend = emac_suspend,
978 .resume = emac_resume,
979 };
980
981 module_platform_driver(emac_driver);
982
983 MODULE_AUTHOR("Stefan Roese <sr@denx.de>");
984 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
985 MODULE_DESCRIPTION("Allwinner A10 emac network driver");
986 MODULE_LICENSE("GPL");
Linux with added FPC-III support