drivers/net/ethernet/ti/davinci_cpdma.h

   1 /*
   2  * Texas Instruments CPDMA Driver
   3  *
   4  * Copyright (C) 2010 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #ifndef __DAVINCI_CPDMA_H__
  16 #define __DAVINCI_CPDMA_H__
  17
  18 #define CPDMA_MAX_CHANNELS      BITS_PER_LONG
  19
  20 #define CPDMA_RX_SOURCE_PORT(__status__)        ((__status__ >> 16) & 0x7)
  21
  22 #define CPDMA_RX_VLAN_ENCAP BIT(19)
  23
  24 #define CPDMA_EOI_RX_THRESH     0x0
  25 #define CPDMA_EOI_RX            0x1
  26 #define CPDMA_EOI_TX            0x2
  27 #define CPDMA_EOI_MISC          0x3
  28
  29 struct cpdma_params {
  30         struct device           *dev;
  31         void __iomem            *dmaregs;
  32         void __iomem            *txhdp, *rxhdp, *txcp, *rxcp;
  33         void __iomem            *rxthresh, *rxfree;
  34         int                     num_chan;
  35         bool                    has_soft_reset;
  36         int                     min_packet_size;
  37         u32                     desc_mem_phys;
  38         u32                     desc_hw_addr;
  39         int                     desc_mem_size;
  40         int                     desc_align;
  41         u32                     bus_freq_mhz;
  42         u32                     descs_pool_size;
  43
  44         /*
  45          * Some instances of embedded cpdma controllers have extra control and
  46          * status registers.  The following flag enables access to these
  47          * "extended" registers.
  48          */
  49         bool                    has_ext_regs;
  50 };
  51
  52 struct cpdma_chan_stats {
  53         u32                     head_enqueue;
  54         u32                     tail_enqueue;
  55         u32                     pad_enqueue;
  56         u32                     misqueued;
  57         u32                     desc_alloc_fail;
  58         u32                     pad_alloc_fail;
  59         u32                     runt_receive_buff;
  60         u32                     runt_transmit_buff;
  61         u32                     empty_dequeue;
  62         u32                     busy_dequeue;
  63         u32                     good_dequeue;
  64         u32                     requeue;
  65         u32                     teardown_dequeue;
  66 };
  67
  68 struct cpdma_ctlr;
  69 struct cpdma_chan;
  70
  71 typedef void (*cpdma_handler_fn)(void *token, int len, int status);
  72
  73 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params);
  74 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr);
  75 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr);
  76 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr);
  77
  78 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num,
  79                                      cpdma_handler_fn handler, int rx_type);
  80 int cpdma_chan_get_rx_buf_num(struct cpdma_chan *chan);
  81 int cpdma_chan_destroy(struct cpdma_chan *chan);
  82 int cpdma_chan_start(struct cpdma_chan *chan);
  83 int cpdma_chan_stop(struct cpdma_chan *chan);
  84
  85 int cpdma_chan_get_stats(struct cpdma_chan *chan,
  86                          struct cpdma_chan_stats *stats);
  87 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data,
  88                       int len, int directed);
  89 int cpdma_chan_process(struct cpdma_chan *chan, int quota);
  90
  91 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable);
  92 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr, u32 value);
  93 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable);
  94 u32 cpdma_ctrl_rxchs_state(struct cpdma_ctlr *ctlr);
  95 u32 cpdma_ctrl_txchs_state(struct cpdma_ctlr *ctlr);
  96 bool cpdma_check_free_tx_desc(struct cpdma_chan *chan);
  97 int cpdma_chan_set_weight(struct cpdma_chan *ch, int weight);
  98 int cpdma_chan_set_rate(struct cpdma_chan *ch, u32 rate);
  99 u32 cpdma_chan_get_rate(struct cpdma_chan *ch);
 100 u32 cpdma_chan_get_min_rate(struct cpdma_ctlr *ctlr);
 101
 102 enum cpdma_control {
 103         CPDMA_TX_RLIM,                  /* read-write */
 104         CPDMA_CMD_IDLE,                 /* write-only */
 105         CPDMA_COPY_ERROR_FRAMES,        /* read-write */
 106         CPDMA_RX_OFF_LEN_UPDATE,        /* read-write */
 107         CPDMA_RX_OWNERSHIP_FLIP,        /* read-write */
 108         CPDMA_TX_PRIO_FIXED,            /* read-write */
 109         CPDMA_STAT_IDLE,                /* read-only */
 110         CPDMA_STAT_TX_ERR_CHAN,         /* read-only */
 111         CPDMA_STAT_TX_ERR_CODE,         /* read-only */
 112         CPDMA_STAT_RX_ERR_CHAN,         /* read-only */
 113         CPDMA_STAT_RX_ERR_CODE,         /* read-only */
 114         CPDMA_RX_BUFFER_OFFSET,         /* read-write */
 115 };
 116
 117 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control);
 118 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value);
 119 int cpdma_get_num_rx_descs(struct cpdma_ctlr *ctlr);
 120 void cpdma_set_num_rx_descs(struct cpdma_ctlr *ctlr, int num_rx_desc);
 121 int cpdma_get_num_tx_descs(struct cpdma_ctlr *ctlr);
 122 int cpdma_chan_split_pool(struct cpdma_ctlr *ctlr);
 123
 124 #endif