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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / scsi / megaraid / megaraid_sas_fusion.h
blob8e5ebee6517f0994faf7a7a7cfb55e1a98e00307
1 /*
2 * Linux MegaRAID driver for SAS based RAID controllers
3 *
4 * Copyright (c) 2009-2013 LSI Corporation
5 * Copyright (c) 2013-2014 Avago Technologies
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 *
20 * FILE: megaraid_sas_fusion.h
21 *
22 * Authors: Avago Technologies
23 * Manoj Jose
24 * Sumant Patro
25 * Kashyap Desai <kashyap.desai@avagotech.com>
26 * Sumit Saxena <sumit.saxena@avagotech.com>
27 *
28 * Send feedback to: megaraidlinux.pdl@avagotech.com
29 *
30 * Mail to: Avago Technologies, 350 West Trimble Road, Building 90,
31 * San Jose, California 95131
32 */
33
34 #ifndef _MEGARAID_SAS_FUSION_H_
35 #define _MEGARAID_SAS_FUSION_H_
36
37 /* Fusion defines */
38 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024
39 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009)
40 #define MEGASAS_MAX_CHAIN_SHIFT 5
41 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000
42 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0
43 #define MEGASAS_256K_IO 128
44 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4)
45 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256
46 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0
47 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1
48 #define MEGASAS_LOAD_BALANCE_FLAG 0x1
49 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1
50 #define HOST_DIAG_WRITE_ENABLE 0x80
51 #define HOST_DIAG_RESET_ADAPTER 0x4
52 #define MEGASAS_FUSION_MAX_RESET_TRIES 3
53 #define MAX_MSIX_QUEUES_FUSION 128
54 #define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
55 #define RDPQ_MAX_CHUNK_COUNT (MAX_MSIX_QUEUES_FUSION / RDPQ_MAX_INDEX_IN_ONE_CHUNK)
56
57 /* Invader defines */
58 #define MPI2_TYPE_CUDA 0x2
59 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000
60 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00
61 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10
62 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80
63 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8
64 #define MR_RL_WRITE_THROUGH_MODE 0x00
65 #define MR_RL_WRITE_BACK_MODE 0x01
66
67 /* T10 PI defines */
68 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8
69 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f
70 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9
71 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB
72 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18
73 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20
74 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60
75
76 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C)
77 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
78
79 /*
80 * Raid context flags
81 */
82
83 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
84 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
85 enum MR_RAID_FLAGS_IO_SUB_TYPE {
86 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
87 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1,
88 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2,
89 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3,
90 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4,
91 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6,
92 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7
93 };
94
95 /*
96 * Request descriptor types
97 */
98 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7
99 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1
100 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2
101 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1
102
103 #define MEGASAS_FP_CMD_LEN 16
104 #define MEGASAS_FUSION_IN_RESET 0
105 #define THRESHOLD_REPLY_COUNT 50
106 #define RAID_1_PEER_CMDS 2
107 #define JBOD_MAPS_COUNT 2
108 #define MEGASAS_REDUCE_QD_COUNT 64
109 #define IOC_INIT_FRAME_SIZE 4096
110
111 /*
112 * Raid Context structure which describes MegaRAID specific IO Parameters
113 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames
114 */
115
116 struct RAID_CONTEXT {
117 #if defined(__BIG_ENDIAN_BITFIELD)
118 u8 nseg:4;
119 u8 type:4;
120 #else
121 u8 type:4;
122 u8 nseg:4;
123 #endif
124 u8 resvd0;
125 __le16 timeout_value;
126 u8 reg_lock_flags;
127 u8 resvd1;
128 __le16 virtual_disk_tgt_id;
129 __le64 reg_lock_row_lba;
130 __le32 reg_lock_length;
131 __le16 next_lmid;
132 u8 ex_status;
133 u8 status;
134 u8 raid_flags;
135 u8 num_sge;
136 __le16 config_seq_num;
137 u8 span_arm;
138 u8 priority;
139 u8 num_sge_ext;
140 u8 resvd2;
141 };
142
143 /*
144 * Raid Context structure which describes ventura MegaRAID specific
145 * IO Paramenters ,This resides at offset 0x60 where the SGL normally
146 * starts in MPT IO Frames
147 */
148 struct RAID_CONTEXT_G35 {
149 #define RAID_CONTEXT_NSEG_MASK 0x00F0
150 #define RAID_CONTEXT_NSEG_SHIFT 4
151 #define RAID_CONTEXT_TYPE_MASK 0x000F
152 #define RAID_CONTEXT_TYPE_SHIFT 0
153 u16 nseg_type;
154 u16 timeout_value; /* 0x02 -0x03 */
155 u16 routing_flags; // 0x04 -0x05 routing flags
156 u16 virtual_disk_tgt_id; /* 0x06 -0x07 */
157 u64 reg_lock_row_lba; /* 0x08 - 0x0F */
158 u32 reg_lock_length; /* 0x10 - 0x13 */
159 union {
160 u16 next_lmid; /* 0x14 - 0x15 */
161 u16 peer_smid; /* used for the raid 1/10 fp writes */
162 } smid;
163 u8 ex_status; /* 0x16 : OUT */
164 u8 status; /* 0x17 status */
165 u8 raid_flags; /* 0x18 resvd[7:6], ioSubType[5:4],
166 * resvd[3:1], preferredCpu[0]
167 */
168 u8 span_arm; /* 0x1C span[7:5], arm[4:0] */
169 u16 config_seq_num; /* 0x1A -0x1B */
170 union {
171 /*
172 * Bit format:
173 * ---------------------------------
174 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
175 * ---------------------------------
176 * Byte0 | numSGE[7]- numSGE[0] |
177 * ---------------------------------
178 * Byte1 |SD | resvd | numSGE 8-11 |
179 * --------------------------------
180 */
181 #define NUM_SGE_MASK_LOWER 0xFF
182 #define NUM_SGE_MASK_UPPER 0x0F
183 #define NUM_SGE_SHIFT_UPPER 8
184 #define STREAM_DETECT_SHIFT 7
185 #define STREAM_DETECT_MASK 0x80
186 struct {
187 #if defined(__BIG_ENDIAN_BITFIELD) /* 0x1C - 0x1D */
188 u16 stream_detected:1;
189 u16 reserved:3;
190 u16 num_sge:12;
191 #else
192 u16 num_sge:12;
193 u16 reserved:3;
194 u16 stream_detected:1;
195 #endif
196 } bits;
197 u8 bytes[2];
198 } u;
199 u8 resvd2[2]; /* 0x1E-0x1F */
200 };
201
202 #define MR_RAID_CTX_ROUTINGFLAGS_SLD_SHIFT 1
203 #define MR_RAID_CTX_ROUTINGFLAGS_C2D_SHIFT 2
204 #define MR_RAID_CTX_ROUTINGFLAGS_FWD_SHIFT 3
205 #define MR_RAID_CTX_ROUTINGFLAGS_SQN_SHIFT 4
206 #define MR_RAID_CTX_ROUTINGFLAGS_SBS_SHIFT 5
207 #define MR_RAID_CTX_ROUTINGFLAGS_RW_SHIFT 6
208 #define MR_RAID_CTX_ROUTINGFLAGS_LOG_SHIFT 7
209 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_SHIFT 8
210 #define MR_RAID_CTX_ROUTINGFLAGS_CPUSEL_MASK 0x0F00
211 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_SHIFT 12
212 #define MR_RAID_CTX_ROUTINGFLAGS_SETDIVERT_MASK 0xF000
213
214 static inline void set_num_sge(struct RAID_CONTEXT_G35 *rctx_g35,
215 u16 sge_count)
216 {
217 rctx_g35->u.bytes[0] = (u8)(sge_count & NUM_SGE_MASK_LOWER);
218 rctx_g35->u.bytes[1] |= (u8)((sge_count >> NUM_SGE_SHIFT_UPPER)
219 & NUM_SGE_MASK_UPPER);
220 }
221
222 static inline u16 get_num_sge(struct RAID_CONTEXT_G35 *rctx_g35)
223 {
224 u16 sge_count;
225
226 sge_count = (u16)(((rctx_g35->u.bytes[1] & NUM_SGE_MASK_UPPER)
227 << NUM_SGE_SHIFT_UPPER) | (rctx_g35->u.bytes[0]));
228 return sge_count;
229 }
230
231 #define SET_STREAM_DETECTED(rctx_g35) \
232 (rctx_g35.u.bytes[1] |= STREAM_DETECT_MASK)
233
234 #define CLEAR_STREAM_DETECTED(rctx_g35) \
235 (rctx_g35.u.bytes[1] &= ~(STREAM_DETECT_MASK))
236
237 static inline bool is_stream_detected(struct RAID_CONTEXT_G35 *rctx_g35)
238 {
239 return ((rctx_g35->u.bytes[1] & STREAM_DETECT_MASK));
240 }
241
242 union RAID_CONTEXT_UNION {
243 struct RAID_CONTEXT raid_context;
244 struct RAID_CONTEXT_G35 raid_context_g35;
245 };
246
247 #define RAID_CTX_SPANARM_ARM_SHIFT (0)
248 #define RAID_CTX_SPANARM_ARM_MASK (0x1f)
249
250 #define RAID_CTX_SPANARM_SPAN_SHIFT (5)
251 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0)
252
253 /* number of bits per index in U32 TrackStream */
254 #define BITS_PER_INDEX_STREAM 4
255 #define INVALID_STREAM_NUM 16
256 #define MR_STREAM_BITMAP 0x76543210
257 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1)
258 #define ZERO_LAST_STREAM 0x0fffffff
259 #define MAX_STREAMS_TRACKED 8
260
261 /*
262 * define region lock types
263 */
264 enum REGION_TYPE {
265 REGION_TYPE_UNUSED = 0,
266 REGION_TYPE_SHARED_READ = 1,
267 REGION_TYPE_SHARED_WRITE = 2,
268 REGION_TYPE_EXCLUSIVE = 3,
269 };
270
271 /* MPI2 defines */
272 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */
273 #define MPI2_WHOINIT_HOST_DRIVER (0x04)
274 #define MPI2_VERSION_MAJOR (0x02)
275 #define MPI2_VERSION_MINOR (0x00)
276 #define MPI2_VERSION_MAJOR_MASK (0xFF00)
277 #define MPI2_VERSION_MAJOR_SHIFT (8)
278 #define MPI2_VERSION_MINOR_MASK (0x00FF)
279 #define MPI2_VERSION_MINOR_SHIFT (0)
280 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
281 MPI2_VERSION_MINOR)
282 #define MPI2_HEADER_VERSION_UNIT (0x10)
283 #define MPI2_HEADER_VERSION_DEV (0x00)
284 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
285 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
286 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
287 #define MPI2_HEADER_VERSION_DEV_SHIFT (0)
288 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
289 MPI2_HEADER_VERSION_DEV)
290 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
291 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
292 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
293 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
294 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
295 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
296 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
297 /* EEDP escape mode */
298 #define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
299 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */
300 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
301 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03)
302 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06)
303 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
304 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
305 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
306 #define MPI2_SCSIIO_CONTROL_READ (0x02000000)
307 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
308 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
309 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
310 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
311 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
312 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
313 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
314 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
315 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
316 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
317 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
318 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
319
320 struct MPI25_IEEE_SGE_CHAIN64 {
321 __le64 Address;
322 __le32 Length;
323 __le16 Reserved1;
324 u8 NextChainOffset;
325 u8 Flags;
326 };
327
328 struct MPI2_SGE_SIMPLE_UNION {
329 __le32 FlagsLength;
330 union {
331 __le32 Address32;
332 __le64 Address64;
333 } u;
334 };
335
336 struct MPI2_SCSI_IO_CDB_EEDP32 {
337 u8 CDB[20]; /* 0x00 */
338 __be32 PrimaryReferenceTag; /* 0x14 */
339 __be16 PrimaryApplicationTag; /* 0x18 */
340 __be16 PrimaryApplicationTagMask; /* 0x1A */
341 __le32 TransferLength; /* 0x1C */
342 };
343
344 struct MPI2_SGE_CHAIN_UNION {
345 __le16 Length;
346 u8 NextChainOffset;
347 u8 Flags;
348 union {
349 __le32 Address32;
350 __le64 Address64;
351 } u;
352 };
353
354 struct MPI2_IEEE_SGE_SIMPLE32 {
355 __le32 Address;
356 __le32 FlagsLength;
357 };
358
359 struct MPI2_IEEE_SGE_CHAIN32 {
360 __le32 Address;
361 __le32 FlagsLength;
362 };
363
364 struct MPI2_IEEE_SGE_SIMPLE64 {
365 __le64 Address;
366 __le32 Length;
367 __le16 Reserved1;
368 u8 Reserved2;
369 u8 Flags;
370 };
371
372 struct MPI2_IEEE_SGE_CHAIN64 {
373 __le64 Address;
374 __le32 Length;
375 __le16 Reserved1;
376 u8 Reserved2;
377 u8 Flags;
378 };
379
380 union MPI2_IEEE_SGE_SIMPLE_UNION {
381 struct MPI2_IEEE_SGE_SIMPLE32 Simple32;
382 struct MPI2_IEEE_SGE_SIMPLE64 Simple64;
383 };
384
385 union MPI2_IEEE_SGE_CHAIN_UNION {
386 struct MPI2_IEEE_SGE_CHAIN32 Chain32;
387 struct MPI2_IEEE_SGE_CHAIN64 Chain64;
388 };
389
390 union MPI2_SGE_IO_UNION {
391 struct MPI2_SGE_SIMPLE_UNION MpiSimple;
392 struct MPI2_SGE_CHAIN_UNION MpiChain;
393 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
394 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
395 };
396
397 union MPI2_SCSI_IO_CDB_UNION {
398 u8 CDB32[32];
399 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
400 struct MPI2_SGE_SIMPLE_UNION SGE;
401 };
402
403 /****************************************************************************
404 * SCSI Task Management messages
405 ****************************************************************************/
406
407 /*SCSI Task Management Request Message */
408 struct MPI2_SCSI_TASK_MANAGE_REQUEST {
409 u16 DevHandle; /*0x00 */
410 u8 ChainOffset; /*0x02 */
411 u8 Function; /*0x03 */
412 u8 Reserved1; /*0x04 */
413 u8 TaskType; /*0x05 */
414 u8 Reserved2; /*0x06 */
415 u8 MsgFlags; /*0x07 */
416 u8 VP_ID; /*0x08 */
417 u8 VF_ID; /*0x09 */
418 u16 Reserved3; /*0x0A */
419 u8 LUN[8]; /*0x0C */
420 u32 Reserved4[7]; /*0x14 */
421 u16 TaskMID; /*0x30 */
422 u16 Reserved5; /*0x32 */
423 };
424
425
426 /*SCSI Task Management Reply Message */
427 struct MPI2_SCSI_TASK_MANAGE_REPLY {
428 u16 DevHandle; /*0x00 */
429 u8 MsgLength; /*0x02 */
430 u8 Function; /*0x03 */
431 u8 ResponseCode; /*0x04 */
432 u8 TaskType; /*0x05 */
433 u8 Reserved1; /*0x06 */
434 u8 MsgFlags; /*0x07 */
435 u8 VP_ID; /*0x08 */
436 u8 VF_ID; /*0x09 */
437 u16 Reserved2; /*0x0A */
438 u16 Reserved3; /*0x0C */
439 u16 IOCStatus; /*0x0E */
440 u32 IOCLogInfo; /*0x10 */
441 u32 TerminationCount; /*0x14 */
442 u32 ResponseInfo; /*0x18 */
443 };
444
445 struct MR_TM_REQUEST {
446 char request[128];
447 };
448
449 struct MR_TM_REPLY {
450 char reply[128];
451 };
452
453 /* SCSI Task Management Request Message */
454 struct MR_TASK_MANAGE_REQUEST {
455 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */
456 struct MR_TM_REQUEST TmRequest;
457 union {
458 struct {
459 #if defined(__BIG_ENDIAN_BITFIELD)
460 u32 reserved1:30;
461 u32 isTMForPD:1;
462 u32 isTMForLD:1;
463 #else
464 u32 isTMForLD:1;
465 u32 isTMForPD:1;
466 u32 reserved1:30;
467 #endif
468 u32 reserved2;
469 } tmReqFlags;
470 struct MR_TM_REPLY TMReply;
471 };
472 };
473
474 /* TaskType values */
475
476 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
477 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
478 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
479 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
480 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
481 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
482 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
483 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
484 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
485
486 /* ResponseCode values */
487
488 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
489 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
490 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
491 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
492 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
493 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
494 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
495 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
496
497 /*
498 * RAID SCSI IO Request Message
499 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST
500 */
501 struct MPI2_RAID_SCSI_IO_REQUEST {
502 __le16 DevHandle; /* 0x00 */
503 u8 ChainOffset; /* 0x02 */
504 u8 Function; /* 0x03 */
505 __le16 Reserved1; /* 0x04 */
506 u8 Reserved2; /* 0x06 */
507 u8 MsgFlags; /* 0x07 */
508 u8 VP_ID; /* 0x08 */
509 u8 VF_ID; /* 0x09 */
510 __le16 Reserved3; /* 0x0A */
511 __le32 SenseBufferLowAddress; /* 0x0C */
512 __le16 SGLFlags; /* 0x10 */
513 u8 SenseBufferLength; /* 0x12 */
514 u8 Reserved4; /* 0x13 */
515 u8 SGLOffset0; /* 0x14 */
516 u8 SGLOffset1; /* 0x15 */
517 u8 SGLOffset2; /* 0x16 */
518 u8 SGLOffset3; /* 0x17 */
519 __le32 SkipCount; /* 0x18 */
520 __le32 DataLength; /* 0x1C */
521 __le32 BidirectionalDataLength; /* 0x20 */
522 __le16 IoFlags; /* 0x24 */
523 __le16 EEDPFlags; /* 0x26 */
524 __le32 EEDPBlockSize; /* 0x28 */
525 __le32 SecondaryReferenceTag; /* 0x2C */
526 __le16 SecondaryApplicationTag; /* 0x30 */
527 __le16 ApplicationTagTranslationMask; /* 0x32 */
528 u8 LUN[8]; /* 0x34 */
529 __le32 Control; /* 0x3C */
530 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */
531 union RAID_CONTEXT_UNION RaidContext; /* 0x60 */
532 union MPI2_SGE_IO_UNION SGL; /* 0x80 */
533 };
534
535 /*
536 * MPT RAID MFA IO Descriptor.
537 */
538 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR {
539 u32 RequestFlags:8;
540 u32 MessageAddress1:24;
541 u32 MessageAddress2;
542 };
543
544 /* Default Request Descriptor */
545 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR {
546 u8 RequestFlags; /* 0x00 */
547 u8 MSIxIndex; /* 0x01 */
548 __le16 SMID; /* 0x02 */
549 __le16 LMID; /* 0x04 */
550 __le16 DescriptorTypeDependent; /* 0x06 */
551 };
552
553 /* High Priority Request Descriptor */
554 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
555 u8 RequestFlags; /* 0x00 */
556 u8 MSIxIndex; /* 0x01 */
557 __le16 SMID; /* 0x02 */
558 __le16 LMID; /* 0x04 */
559 __le16 Reserved1; /* 0x06 */
560 };
561
562 /* SCSI IO Request Descriptor */
563 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
564 u8 RequestFlags; /* 0x00 */
565 u8 MSIxIndex; /* 0x01 */
566 __le16 SMID; /* 0x02 */
567 __le16 LMID; /* 0x04 */
568 __le16 DevHandle; /* 0x06 */
569 };
570
571 /* SCSI Target Request Descriptor */
572 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
573 u8 RequestFlags; /* 0x00 */
574 u8 MSIxIndex; /* 0x01 */
575 __le16 SMID; /* 0x02 */
576 __le16 LMID; /* 0x04 */
577 __le16 IoIndex; /* 0x06 */
578 };
579
580 /* RAID Accelerator Request Descriptor */
581 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
582 u8 RequestFlags; /* 0x00 */
583 u8 MSIxIndex; /* 0x01 */
584 __le16 SMID; /* 0x02 */
585 __le16 LMID; /* 0x04 */
586 __le16 Reserved; /* 0x06 */
587 };
588
589 /* union of Request Descriptors */
590 union MEGASAS_REQUEST_DESCRIPTOR_UNION {
591 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
592 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
593 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
594 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
595 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
596 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo;
597 union {
598 struct {
599 __le32 low;
600 __le32 high;
601 } u;
602 __le64 Words;
603 };
604 };
605
606 /* Default Reply Descriptor */
607 struct MPI2_DEFAULT_REPLY_DESCRIPTOR {
608 u8 ReplyFlags; /* 0x00 */
609 u8 MSIxIndex; /* 0x01 */
610 __le16 DescriptorTypeDependent1; /* 0x02 */
611 __le32 DescriptorTypeDependent2; /* 0x04 */
612 };
613
614 /* Address Reply Descriptor */
615 struct MPI2_ADDRESS_REPLY_DESCRIPTOR {
616 u8 ReplyFlags; /* 0x00 */
617 u8 MSIxIndex; /* 0x01 */
618 __le16 SMID; /* 0x02 */
619 __le32 ReplyFrameAddress; /* 0x04 */
620 };
621
622 /* SCSI IO Success Reply Descriptor */
623 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
624 u8 ReplyFlags; /* 0x00 */
625 u8 MSIxIndex; /* 0x01 */
626 __le16 SMID; /* 0x02 */
627 __le16 TaskTag; /* 0x04 */
628 __le16 Reserved1; /* 0x06 */
629 };
630
631 /* TargetAssist Success Reply Descriptor */
632 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
633 u8 ReplyFlags; /* 0x00 */
634 u8 MSIxIndex; /* 0x01 */
635 __le16 SMID; /* 0x02 */
636 u8 SequenceNumber; /* 0x04 */
637 u8 Reserved1; /* 0x05 */
638 __le16 IoIndex; /* 0x06 */
639 };
640
641 /* Target Command Buffer Reply Descriptor */
642 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
643 u8 ReplyFlags; /* 0x00 */
644 u8 MSIxIndex; /* 0x01 */
645 u8 VP_ID; /* 0x02 */
646 u8 Flags; /* 0x03 */
647 __le16 InitiatorDevHandle; /* 0x04 */
648 __le16 IoIndex; /* 0x06 */
649 };
650
651 /* RAID Accelerator Success Reply Descriptor */
652 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
653 u8 ReplyFlags; /* 0x00 */
654 u8 MSIxIndex; /* 0x01 */
655 __le16 SMID; /* 0x02 */
656 __le32 Reserved; /* 0x04 */
657 };
658
659 /* union of Reply Descriptors */
660 union MPI2_REPLY_DESCRIPTORS_UNION {
661 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
662 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
663 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
664 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
665 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
666 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR
667 RAIDAcceleratorSuccess;
668 __le64 Words;
669 };
670
671 /* IOCInit Request message */
672 struct MPI2_IOC_INIT_REQUEST {
673 u8 WhoInit; /* 0x00 */
674 u8 Reserved1; /* 0x01 */
675 u8 ChainOffset; /* 0x02 */
676 u8 Function; /* 0x03 */
677 __le16 Reserved2; /* 0x04 */
678 u8 Reserved3; /* 0x06 */
679 u8 MsgFlags; /* 0x07 */
680 u8 VP_ID; /* 0x08 */
681 u8 VF_ID; /* 0x09 */
682 __le16 Reserved4; /* 0x0A */
683 __le16 MsgVersion; /* 0x0C */
684 __le16 HeaderVersion; /* 0x0E */
685 u32 Reserved5; /* 0x10 */
686 __le16 Reserved6; /* 0x14 */
687 u8 HostPageSize; /* 0x16 */
688 u8 HostMSIxVectors; /* 0x17 */
689 __le16 Reserved8; /* 0x18 */
690 __le16 SystemRequestFrameSize; /* 0x1A */
691 __le16 ReplyDescriptorPostQueueDepth; /* 0x1C */
692 __le16 ReplyFreeQueueDepth; /* 0x1E */
693 __le32 SenseBufferAddressHigh; /* 0x20 */
694 __le32 SystemReplyAddressHigh; /* 0x24 */
695 __le64 SystemRequestFrameBaseAddress; /* 0x28 */
696 __le64 ReplyDescriptorPostQueueAddress;/* 0x30 */
697 __le64 ReplyFreeQueueAddress; /* 0x38 */
698 __le64 TimeStamp; /* 0x40 */
699 };
700
701 /* mrpriv defines */
702 #define MR_PD_INVALID 0xFFFF
703 #define MR_DEVHANDLE_INVALID 0xFFFF
704 #define MAX_SPAN_DEPTH 8
705 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH
706 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH)
707 #define MAX_ROW_SIZE 32
708 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE)
709 #define MAX_LOGICAL_DRIVES 64
710 #define MAX_LOGICAL_DRIVES_EXT 256
711 #define MAX_LOGICAL_DRIVES_DYN 512
712 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES)
713 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES)
714 #define MAX_ARRAYS 128
715 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS)
716 #define MAX_ARRAYS_EXT 256
717 #define MAX_API_ARRAYS_EXT (MAX_ARRAYS_EXT)
718 #define MAX_API_ARRAYS_DYN 512
719 #define MAX_PHYSICAL_DEVICES 256
720 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES)
721 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512
722 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101
723 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102
724 #define MR_DCMD_DRV_GET_TARGET_PROP 0x0200e103
725 #define MR_DCMD_CTRL_SHARED_HOST_MEM_ALLOC 0x010e8485 /* SR-IOV HB alloc*/
726 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS_111 0x03200200
727 #define MR_DCMD_LD_VF_MAP_GET_ALL_LDS 0x03150200
728
729 struct MR_DEV_HANDLE_INFO {
730 __le16 curDevHdl;
731 u8 validHandles;
732 u8 interfaceType;
733 __le16 devHandle[2];
734 };
735
736 struct MR_ARRAY_INFO {
737 __le16 pd[MAX_RAIDMAP_ROW_SIZE];
738 };
739
740 struct MR_QUAD_ELEMENT {
741 __le64 logStart;
742 __le64 logEnd;
743 __le64 offsetInSpan;
744 __le32 diff;
745 __le32 reserved1;
746 };
747
748 struct MR_SPAN_INFO {
749 __le32 noElements;
750 __le32 reserved1;
751 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH];
752 };
753
754 struct MR_LD_SPAN {
755 __le64 startBlk;
756 __le64 numBlks;
757 __le16 arrayRef;
758 u8 spanRowSize;
759 u8 spanRowDataSize;
760 u8 reserved[4];
761 };
762
763 struct MR_SPAN_BLOCK_INFO {
764 __le64 num_rows;
765 struct MR_LD_SPAN span;
766 struct MR_SPAN_INFO block_span_info;
767 };
768
769 #define MR_RAID_CTX_CPUSEL_0 0
770 #define MR_RAID_CTX_CPUSEL_1 1
771 #define MR_RAID_CTX_CPUSEL_2 2
772 #define MR_RAID_CTX_CPUSEL_3 3
773 #define MR_RAID_CTX_CPUSEL_FCFS 0xF
774
775 struct MR_CPU_AFFINITY_MASK {
776 union {
777 struct {
778 #ifndef MFI_BIG_ENDIAN
779 u8 hw_path:1;
780 u8 cpu0:1;
781 u8 cpu1:1;
782 u8 cpu2:1;
783 u8 cpu3:1;
784 u8 reserved:3;
785 #else
786 u8 reserved:3;
787 u8 cpu3:1;
788 u8 cpu2:1;
789 u8 cpu1:1;
790 u8 cpu0:1;
791 u8 hw_path:1;
792 #endif
793 };
794 u8 core_mask;
795 };
796 };
797
798 struct MR_IO_AFFINITY {
799 union {
800 struct {
801 struct MR_CPU_AFFINITY_MASK pdRead;
802 struct MR_CPU_AFFINITY_MASK pdWrite;
803 struct MR_CPU_AFFINITY_MASK ldRead;
804 struct MR_CPU_AFFINITY_MASK ldWrite;
805 };
806 u32 word;
807 };
808 u8 maxCores; /* Total cores + HW Path in ROC */
809 u8 reserved[3];
810 };
811
812 struct MR_LD_RAID {
813 struct {
814 #if defined(__BIG_ENDIAN_BITFIELD)
815 u32 reserved4:2;
816 u32 fp_cache_bypass_capable:1;
817 u32 fp_rmw_capable:1;
818 u32 disable_coalescing:1;
819 u32 fpBypassRegionLock:1;
820 u32 tmCapable:1;
821 u32 fpNonRWCapable:1;
822 u32 fpReadAcrossStripe:1;
823 u32 fpWriteAcrossStripe:1;
824 u32 fpReadCapable:1;
825 u32 fpWriteCapable:1;
826 u32 encryptionType:8;
827 u32 pdPiMode:4;
828 u32 ldPiMode:4;
829 u32 reserved5:2;
830 u32 ra_capable:1;
831 u32 fpCapable:1;
832 #else
833 u32 fpCapable:1;
834 u32 ra_capable:1;
835 u32 reserved5:2;
836 u32 ldPiMode:4;
837 u32 pdPiMode:4;
838 u32 encryptionType:8;
839 u32 fpWriteCapable:1;
840 u32 fpReadCapable:1;
841 u32 fpWriteAcrossStripe:1;
842 u32 fpReadAcrossStripe:1;
843 u32 fpNonRWCapable:1;
844 u32 tmCapable:1;
845 u32 fpBypassRegionLock:1;
846 u32 disable_coalescing:1;
847 u32 fp_rmw_capable:1;
848 u32 fp_cache_bypass_capable:1;
849 u32 reserved4:2;
850 #endif
851 } capability;
852 __le32 reserved6;
853 __le64 size;
854 u8 spanDepth;
855 u8 level;
856 u8 stripeShift;
857 u8 rowSize;
858 u8 rowDataSize;
859 u8 writeMode;
860 u8 PRL;
861 u8 SRL;
862 __le16 targetId;
863 u8 ldState;
864 u8 regTypeReqOnWrite;
865 u8 modFactor;
866 u8 regTypeReqOnRead;
867 __le16 seqNum;
868
869 struct {
870 u32 ldSyncRequired:1;
871 u32 reserved:31;
872 } flags;
873
874 u8 LUN[8]; /* 0x24 8 byte LUN field used for SCSI IO's */
875 u8 fpIoTimeoutForLd;/*0x2C timeout value used by driver in FP IO*/
876 /* Ox2D This LD accept priority boost of this type */
877 u8 ld_accept_priority_type;
878 u8 reserved2[2]; /* 0x2E - 0x2F */
879 /* 0x30 - 0x33, Logical block size for the LD */
880 u32 logical_block_length;
881 struct {
882 #ifndef MFI_BIG_ENDIAN
883 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
884 u32 ld_pi_exp:4;
885 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
886 * BLOCK EXPONENT from READ CAPACITY 16
887 */
888 u32 ld_logical_block_exp:4;
889 u32 reserved1:24; /* 0x34 */
890 #else
891 u32 reserved1:24; /* 0x34 */
892 /* 0x34, LOGICAL BLOCKS PER PHYSICAL
893 * BLOCK EXPONENT from READ CAPACITY 16
894 */
895 u32 ld_logical_block_exp:4;
896 /* 0x34, P_I_EXPONENT from READ CAPACITY 16 */
897 u32 ld_pi_exp:4;
898 #endif
899 }; /* 0x34 - 0x37 */
900 /* 0x38 - 0x3f, This will determine which
901 * core will process LD IO and PD IO.
902 */
903 struct MR_IO_AFFINITY cpuAffinity;
904 /* Bit definiations are specified by MR_IO_AFFINITY */
905 u8 reserved3[0x80 - 0x40]; /* 0x40 - 0x7f */
906 };
907
908 struct MR_LD_SPAN_MAP {
909 struct MR_LD_RAID ldRaid;
910 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE];
911 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH];
912 };
913
914 struct MR_FW_RAID_MAP {
915 __le32 totalSize;
916 union {
917 struct {
918 __le32 maxLd;
919 __le32 maxSpanDepth;
920 __le32 maxRowSize;
921 __le32 maxPdCount;
922 __le32 maxArrays;
923 } validationInfo;
924 __le32 version[5];
925 };
926
927 __le32 ldCount;
928 __le32 Reserved1;
929 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+
930 MAX_RAIDMAP_VIEWS];
931 u8 fpPdIoTimeoutSec;
932 u8 reserved2[7];
933 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS];
934 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
935 struct MR_LD_SPAN_MAP ldSpanMap[1];
936 };
937
938 struct IO_REQUEST_INFO {
939 u64 ldStartBlock;
940 u32 numBlocks;
941 u16 ldTgtId;
942 u8 isRead;
943 __le16 devHandle;
944 u8 pd_interface;
945 u64 pdBlock;
946 u8 fpOkForIo;
947 u8 IoforUnevenSpan;
948 u8 start_span;
949 u8 do_fp_rlbypass;
950 u64 start_row;
951 u8 span_arm; /* span[7:5], arm[4:0] */
952 u8 pd_after_lb;
953 u16 r1_alt_dev_handle; /* raid 1/10 only */
954 bool ra_capable;
955 };
956
957 struct MR_LD_TARGET_SYNC {
958 u8 targetId;
959 u8 reserved;
960 __le16 seqNum;
961 };
962
963 /*
964 * RAID Map descriptor Types.
965 * Each element should uniquely idetify one data structure in the RAID map
966 */
967 enum MR_RAID_MAP_DESC_TYPE {
968 /* MR_DEV_HANDLE_INFO data */
969 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0x0,
970 /* target to Ld num Index map */
971 RAID_MAP_DESC_TYPE_TGTID_INFO = 0x1,
972 /* MR_ARRAY_INFO data */
973 RAID_MAP_DESC_TYPE_ARRAY_INFO = 0x2,
974 /* MR_LD_SPAN_MAP data */
975 RAID_MAP_DESC_TYPE_SPAN_INFO = 0x3,
976 RAID_MAP_DESC_TYPE_COUNT,
977 };
978
979 /*
980 * This table defines the offset, size and num elements of each descriptor
981 * type in the RAID Map buffer
982 */
983 struct MR_RAID_MAP_DESC_TABLE {
984 /* Raid map descriptor type */
985 u32 raid_map_desc_type;
986 /* Offset into the RAID map buffer where
987 * descriptor data is saved
988 */
989 u32 raid_map_desc_offset;
990 /* total size of the
991 * descriptor buffer
992 */
993 u32 raid_map_desc_buffer_size;
994 /* Number of elements contained in the
995 * descriptor buffer
996 */
997 u32 raid_map_desc_elements;
998 };
999
1000 /*
1001 * Dynamic Raid Map Structure.
1002 */
1003 struct MR_FW_RAID_MAP_DYNAMIC {
1004 u32 raid_map_size; /* total size of RAID Map structure */
1005 u32 desc_table_offset;/* Offset of desc table into RAID map*/
1006 u32 desc_table_size; /* Total Size of desc table */
1007 /* Total Number of elements in the desc table */
1008 u32 desc_table_num_elements;
1009 u64 reserved1;
1010 u32 reserved2[3]; /*future use */
1011 /* timeout value used by driver in FP IOs */
1012 u8 fp_pd_io_timeout_sec;
1013 u8 reserved3[3];
1014 /* when this seqNum increments, driver needs to
1015 * release RMW buffers asap
1016 */
1017 u32 rmw_fp_seq_num;
1018 u16 ld_count; /* count of lds. */
1019 u16 ar_count; /* count of arrays */
1020 u16 span_count; /* count of spans */
1021 u16 reserved4[3];
1022 /*
1023 * The below structure of pointers is only to be used by the driver.
1024 * This is added in the ,API to reduce the amount of code changes
1025 * needed in the driver to support dynamic RAID map Firmware should
1026 * not update these pointers while preparing the raid map
1027 */
1028 union {
1029 struct {
1030 struct MR_DEV_HANDLE_INFO *dev_hndl_info;
1031 u16 *ld_tgt_id_to_ld;
1032 struct MR_ARRAY_INFO *ar_map_info;
1033 struct MR_LD_SPAN_MAP *ld_span_map;
1034 };
1035 u64 ptr_structure_size[RAID_MAP_DESC_TYPE_COUNT];
1036 };
1037 /*
1038 * RAID Map descriptor table defines the layout of data in the RAID Map.
1039 * The size of the descriptor table itself could change.
1040 */
1041 /* Variable Size descriptor Table. */
1042 struct MR_RAID_MAP_DESC_TABLE
1043 raid_map_desc_table[RAID_MAP_DESC_TYPE_COUNT];
1044 /* Variable Size buffer containing all data */
1045 u32 raid_map_desc_data[1];
1046 }; /* Dynamicaly sized RAID MAp structure */
1047
1048 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1049 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1050 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1051 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1052 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1053 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1054 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1055
1056 #define MPI2_SGE_FLAGS_SHIFT (0x02)
1057 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0)
1058 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00)
1059 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02)
1060
1061 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C)
1062 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00)
1063 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08)
1064 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10)
1065
1066 struct megasas_register_set;
1067 struct megasas_instance;
1068
1069 union desc_word {
1070 u64 word;
1071 struct {
1072 u32 low;
1073 u32 high;
1074 } u;
1075 };
1076
1077 struct megasas_cmd_fusion {
1078 struct MPI2_RAID_SCSI_IO_REQUEST *io_request;
1079 dma_addr_t io_request_phys_addr;
1080
1081 union MPI2_SGE_IO_UNION *sg_frame;
1082 dma_addr_t sg_frame_phys_addr;
1083
1084 u8 *sense;
1085 dma_addr_t sense_phys_addr;
1086
1087 struct list_head list;
1088 struct scsi_cmnd *scmd;
1089 struct megasas_instance *instance;
1090
1091 u8 retry_for_fw_reset;
1092 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc;
1093
1094 /*
1095 * Context for a MFI frame.
1096 * Used to get the mfi cmd from list when a MFI cmd is completed
1097 */
1098 u32 sync_cmd_idx;
1099 u32 index;
1100 u8 pd_r1_lb;
1101 struct completion done;
1102 u8 pd_interface;
1103 u16 r1_alt_dev_handle; /* raid 1/10 only*/
1104 bool cmd_completed; /* raid 1/10 fp writes status holder */
1105
1106 };
1107
1108 struct LD_LOAD_BALANCE_INFO {
1109 u8 loadBalanceFlag;
1110 u8 reserved1;
1111 atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES];
1112 u64 last_accessed_block[MAX_PHYSICAL_DEVICES];
1113 };
1114
1115 /* SPAN_SET is info caclulated from span info from Raid map per LD */
1116 typedef struct _LD_SPAN_SET {
1117 u64 log_start_lba;
1118 u64 log_end_lba;
1119 u64 span_row_start;
1120 u64 span_row_end;
1121 u64 data_strip_start;
1122 u64 data_strip_end;
1123 u64 data_row_start;
1124 u64 data_row_end;
1125 u8 strip_offset[MAX_SPAN_DEPTH];
1126 u32 span_row_data_width;
1127 u32 diff;
1128 u32 reserved[2];
1129 } LD_SPAN_SET, *PLD_SPAN_SET;
1130
1131 typedef struct LOG_BLOCK_SPAN_INFO {
1132 LD_SPAN_SET span_set[MAX_SPAN_DEPTH];
1133 } LD_SPAN_INFO, *PLD_SPAN_INFO;
1134
1135 struct MR_FW_RAID_MAP_ALL {
1136 struct MR_FW_RAID_MAP raidMap;
1137 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1];
1138 } __attribute__ ((packed));
1139
1140 struct MR_DRV_RAID_MAP {
1141 /* total size of this structure, including this field.
1142 * This feild will be manupulated by driver for ext raid map,
1143 * else pick the value from firmware raid map.
1144 */
1145 __le32 totalSize;
1146
1147 union {
1148 struct {
1149 __le32 maxLd;
1150 __le32 maxSpanDepth;
1151 __le32 maxRowSize;
1152 __le32 maxPdCount;
1153 __le32 maxArrays;
1154 } validationInfo;
1155 __le32 version[5];
1156 };
1157
1158 /* timeout value used by driver in FP IOs*/
1159 u8 fpPdIoTimeoutSec;
1160 u8 reserved2[7];
1161
1162 __le16 ldCount;
1163 __le16 arCount;
1164 __le16 spanCount;
1165 __le16 reserve3;
1166
1167 struct MR_DEV_HANDLE_INFO
1168 devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN];
1169 u16 ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN];
1170 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN];
1171 struct MR_LD_SPAN_MAP ldSpanMap[1];
1172
1173 };
1174
1175 /* Driver raid map size is same as raid map ext
1176 * MR_DRV_RAID_MAP_ALL is created to sync with old raid.
1177 * And it is mainly for code re-use purpose.
1178 */
1179 struct MR_DRV_RAID_MAP_ALL {
1180
1181 struct MR_DRV_RAID_MAP raidMap;
1182 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1];
1183 } __packed;
1184
1185
1186
1187 struct MR_FW_RAID_MAP_EXT {
1188 /* Not usred in new map */
1189 u32 reserved;
1190
1191 union {
1192 struct {
1193 u32 maxLd;
1194 u32 maxSpanDepth;
1195 u32 maxRowSize;
1196 u32 maxPdCount;
1197 u32 maxArrays;
1198 } validationInfo;
1199 u32 version[5];
1200 };
1201
1202 u8 fpPdIoTimeoutSec;
1203 u8 reserved2[7];
1204
1205 __le16 ldCount;
1206 __le16 arCount;
1207 __le16 spanCount;
1208 __le16 reserve3;
1209
1210 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES];
1211 u8 ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT];
1212 struct MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT];
1213 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT];
1214 };
1215
1216 /*
1217 * * define MR_PD_CFG_SEQ structure for system PDs
1218 * */
1219 struct MR_PD_CFG_SEQ {
1220 u16 seqNum;
1221 u16 devHandle;
1222 struct {
1223 #if defined(__BIG_ENDIAN_BITFIELD)
1224 u8 reserved:7;
1225 u8 tmCapable:1;
1226 #else
1227 u8 tmCapable:1;
1228 u8 reserved:7;
1229 #endif
1230 } capability;
1231 u8 reserved;
1232 u16 pd_target_id;
1233 } __packed;
1234
1235 struct MR_PD_CFG_SEQ_NUM_SYNC {
1236 __le32 size;
1237 __le32 count;
1238 struct MR_PD_CFG_SEQ seq[1];
1239 } __packed;
1240
1241 /* stream detection */
1242 struct STREAM_DETECT {
1243 u64 next_seq_lba; /* next LBA to match sequential access */
1244 struct megasas_cmd_fusion *first_cmd_fusion; /* first cmd in group */
1245 struct megasas_cmd_fusion *last_cmd_fusion; /* last cmd in group */
1246 u32 count_cmds_in_stream; /* count of host commands in this stream */
1247 u16 num_sges_in_group; /* total number of SGEs in grouped IOs */
1248 u8 is_read; /* SCSI OpCode for this stream */
1249 u8 group_depth; /* total number of host commands in group */
1250 /* TRUE if cannot add any more commands to this group */
1251 bool group_flush;
1252 u8 reserved[7]; /* pad to 64-bit alignment */
1253 };
1254
1255 struct LD_STREAM_DETECT {
1256 bool write_back; /* TRUE if WB, FALSE if WT */
1257 bool fp_write_enabled;
1258 bool members_ssds;
1259 bool fp_cache_bypass_capable;
1260 u32 mru_bit_map; /* bitmap used to track MRU and LRU stream indicies */
1261 /* this is the array of stream detect structures (one per stream) */
1262 struct STREAM_DETECT stream_track[MAX_STREAMS_TRACKED];
1263 };
1264
1265 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY {
1266 u64 RDPQBaseAddress;
1267 u32 Reserved1;
1268 u32 Reserved2;
1269 };
1270
1271 struct rdpq_alloc_detail {
1272 struct dma_pool *dma_pool_ptr;
1273 dma_addr_t pool_entry_phys;
1274 union MPI2_REPLY_DESCRIPTORS_UNION *pool_entry_virt;
1275 };
1276
1277 struct fusion_context {
1278 struct megasas_cmd_fusion **cmd_list;
1279 dma_addr_t req_frames_desc_phys;
1280 u8 *req_frames_desc;
1281
1282 struct dma_pool *io_request_frames_pool;
1283 dma_addr_t io_request_frames_phys;
1284 u8 *io_request_frames;
1285
1286 struct dma_pool *sg_dma_pool;
1287 struct dma_pool *sense_dma_pool;
1288
1289 u8 *sense;
1290 dma_addr_t sense_phys_addr;
1291
1292 dma_addr_t reply_frames_desc_phys[MAX_MSIX_QUEUES_FUSION];
1293 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc[MAX_MSIX_QUEUES_FUSION];
1294 struct rdpq_alloc_detail rdpq_tracker[RDPQ_MAX_CHUNK_COUNT];
1295 struct dma_pool *reply_frames_desc_pool;
1296 struct dma_pool *reply_frames_desc_pool_align;
1297
1298 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION];
1299
1300 u32 reply_q_depth;
1301 u32 request_alloc_sz;
1302 u32 reply_alloc_sz;
1303 u32 io_frames_alloc_sz;
1304
1305 struct MPI2_IOC_INIT_RDPQ_ARRAY_ENTRY *rdpq_virt;
1306 dma_addr_t rdpq_phys;
1307 u16 max_sge_in_main_msg;
1308 u16 max_sge_in_chain;
1309
1310 u8 chain_offset_io_request;
1311 u8 chain_offset_mfi_pthru;
1312
1313 struct MR_FW_RAID_MAP_DYNAMIC *ld_map[2];
1314 dma_addr_t ld_map_phys[2];
1315
1316 /*Non dma-able memory. Driver local copy.*/
1317 struct MR_DRV_RAID_MAP_ALL *ld_drv_map[2];
1318
1319 u32 max_map_sz;
1320 u32 current_map_sz;
1321 u32 old_map_sz;
1322 u32 new_map_sz;
1323 u32 drv_map_sz;
1324 u32 drv_map_pages;
1325 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_seq_sync[JBOD_MAPS_COUNT];
1326 dma_addr_t pd_seq_phys[JBOD_MAPS_COUNT];
1327 u8 fast_path_io;
1328 struct LD_LOAD_BALANCE_INFO *load_balance_info;
1329 u32 load_balance_info_pages;
1330 LD_SPAN_INFO *log_to_span;
1331 u32 log_to_span_pages;
1332 struct LD_STREAM_DETECT **stream_detect_by_ld;
1333 dma_addr_t ioc_init_request_phys;
1334 struct MPI2_IOC_INIT_REQUEST *ioc_init_request;
1335 struct megasas_cmd *ioc_init_cmd;
1336
1337 };
1338
1339 union desc_value {
1340 __le64 word;
1341 struct {
1342 __le32 low;
1343 __le32 high;
1344 } u;
1345 };
1346
1347 enum CMD_RET_VALUES {
1348 REFIRE_CMD = 1,
1349 COMPLETE_CMD = 2,
1350 RETURN_CMD = 3,
1351 };
1352
1353 void megasas_free_cmds_fusion(struct megasas_instance *instance);
1354 int megasas_ioc_init_fusion(struct megasas_instance *instance);
1355 u8 megasas_get_map_info(struct megasas_instance *instance);
1356 int megasas_sync_map_info(struct megasas_instance *instance);
1357 void megasas_release_fusion(struct megasas_instance *instance);
1358 void megasas_reset_reply_desc(struct megasas_instance *instance);
1359 int megasas_check_mpio_paths(struct megasas_instance *instance,
1360 struct scsi_cmnd *scmd);
1361 void megasas_fusion_ocr_wq(struct work_struct *work);
1362
1363 #endif /* _MEGARAID_SAS_FUSION_H_ */
Linux with added FPC-III support