drivers/spi/spi-at91-usart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Driver for AT91 USART Controllers as SPI
   4 //
   5 // Copyright (C) 2018 Microchip Technology Inc.
   6 //
   7 // Author: Radu Pirea <radu.pirea@microchip.com>
   8
   9 #include <linux/clk.h>
  10 #include <linux/delay.h>
  11 #include <linux/interrupt.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of_gpio.h>
  15 #include <linux/platform_device.h>
  16
  17 #include <linux/spi/spi.h>
  18
  19 #define US_CR                   0x00
  20 #define US_MR                   0x04
  21 #define US_IER                  0x08
  22 #define US_IDR                  0x0C
  23 #define US_CSR                  0x14
  24 #define US_RHR                  0x18
  25 #define US_THR                  0x1C
  26 #define US_BRGR                 0x20
  27 #define US_VERSION              0xFC
  28
  29 #define US_CR_RSTRX             BIT(2)
  30 #define US_CR_RSTTX             BIT(3)
  31 #define US_CR_RXEN              BIT(4)
  32 #define US_CR_RXDIS             BIT(5)
  33 #define US_CR_TXEN              BIT(6)
  34 #define US_CR_TXDIS             BIT(7)
  35
  36 #define US_MR_SPI_MASTER        0x0E
  37 #define US_MR_CHRL              GENMASK(7, 6)
  38 #define US_MR_CPHA              BIT(8)
  39 #define US_MR_CPOL              BIT(16)
  40 #define US_MR_CLKO              BIT(18)
  41 #define US_MR_WRDBT             BIT(20)
  42 #define US_MR_LOOP              BIT(15)
  43
  44 #define US_IR_RXRDY             BIT(0)
  45 #define US_IR_TXRDY             BIT(1)
  46 #define US_IR_OVRE              BIT(5)
  47
  48 #define US_BRGR_SIZE            BIT(16)
  49
  50 #define US_MIN_CLK_DIV          0x06
  51 #define US_MAX_CLK_DIV          BIT(16)
  52
  53 #define US_RESET                (US_CR_RSTRX | US_CR_RSTTX)
  54 #define US_DISABLE              (US_CR_RXDIS | US_CR_TXDIS)
  55 #define US_ENABLE               (US_CR_RXEN | US_CR_TXEN)
  56 #define US_OVRE_RXRDY_IRQS      (US_IR_OVRE | US_IR_RXRDY)
  57
  58 #define US_INIT \
  59         (US_MR_SPI_MASTER | US_MR_CHRL | US_MR_CLKO | US_MR_WRDBT)
  60
  61 /* Register access macros */
  62 #define at91_usart_spi_readl(port, reg) \
  63         readl_relaxed((port)->regs + US_##reg)
  64 #define at91_usart_spi_writel(port, reg, value) \
  65         writel_relaxed((value), (port)->regs + US_##reg)
  66
  67 #define at91_usart_spi_readb(port, reg) \
  68         readb_relaxed((port)->regs + US_##reg)
  69 #define at91_usart_spi_writeb(port, reg, value) \
  70         writeb_relaxed((value), (port)->regs + US_##reg)
  71
  72 struct at91_usart_spi {
  73         struct spi_transfer     *current_transfer;
  74         void __iomem            *regs;
  75         struct device           *dev;
  76         struct clk              *clk;
  77
  78         /*used in interrupt to protect data reading*/
  79         spinlock_t              lock;
  80
  81         int                     irq;
  82         unsigned int            current_tx_remaining_bytes;
  83         unsigned int            current_rx_remaining_bytes;
  84
  85         u32                     spi_clk;
  86         u32                     status;
  87
  88         bool                    xfer_failed;
  89 };
  90
  91 static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
  92 {
  93         return aus->status & US_IR_TXRDY;
  94 }
  95
  96 static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
  97 {
  98         return aus->status & US_IR_RXRDY;
  99 }
 100
 101 static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
 102 {
 103         return aus->status & US_IR_OVRE;
 104 }
 105
 106 static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
 107 {
 108         aus->status = at91_usart_spi_readl(aus, CSR);
 109         return aus->status;
 110 }
 111
 112 static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
 113 {
 114         unsigned int len = aus->current_transfer->len;
 115         unsigned int remaining = aus->current_tx_remaining_bytes;
 116         const u8  *tx_buf = aus->current_transfer->tx_buf;
 117
 118         if (!remaining)
 119                 return;
 120
 121         if (at91_usart_spi_tx_ready(aus)) {
 122                 at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
 123                 aus->current_tx_remaining_bytes--;
 124         }
 125 }
 126
 127 static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
 128 {
 129         int len = aus->current_transfer->len;
 130         int remaining = aus->current_rx_remaining_bytes;
 131         u8  *rx_buf = aus->current_transfer->rx_buf;
 132
 133         if (!remaining)
 134                 return;
 135
 136         rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
 137         aus->current_rx_remaining_bytes--;
 138 }
 139
 140 static inline void
 141 at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
 142                               struct spi_transfer *xfer)
 143 {
 144         at91_usart_spi_writel(aus, BRGR,
 145                               DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
 146 }
 147
 148 static irqreturn_t at91_usart_spi_interrupt(int irq, void *dev_id)
 149 {
 150         struct spi_controller *controller = dev_id;
 151         struct at91_usart_spi *aus = spi_master_get_devdata(controller);
 152
 153         spin_lock(&aus->lock);
 154         at91_usart_spi_read_status(aus);
 155
 156         if (at91_usart_spi_check_overrun(aus)) {
 157                 aus->xfer_failed = true;
 158                 at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
 159                 spin_unlock(&aus->lock);
 160                 return IRQ_HANDLED;
 161         }
 162
 163         if (at91_usart_spi_rx_ready(aus)) {
 164                 at91_usart_spi_rx(aus);
 165                 spin_unlock(&aus->lock);
 166                 return IRQ_HANDLED;
 167         }
 168
 169         spin_unlock(&aus->lock);
 170
 171         return IRQ_NONE;
 172 }
 173
 174 static int at91_usart_spi_setup(struct spi_device *spi)
 175 {
 176         struct at91_usart_spi *aus = spi_master_get_devdata(spi->controller);
 177         u32 *ausd = spi->controller_state;
 178         unsigned int mr = at91_usart_spi_readl(aus, MR);
 179         u8 bits = spi->bits_per_word;
 180
 181         if (bits != 8) {
 182                 dev_dbg(&spi->dev, "Only 8 bits per word are supported\n");
 183                 return -EINVAL;
 184         }
 185
 186         if (spi->mode & SPI_CPOL)
 187                 mr |= US_MR_CPOL;
 188         else
 189                 mr &= ~US_MR_CPOL;
 190
 191         if (spi->mode & SPI_CPHA)
 192                 mr |= US_MR_CPHA;
 193         else
 194                 mr &= ~US_MR_CPHA;
 195
 196         if (spi->mode & SPI_LOOP)
 197                 mr |= US_MR_LOOP;
 198         else
 199                 mr &= ~US_MR_LOOP;
 200
 201         if (!ausd) {
 202                 ausd = kzalloc(sizeof(*ausd), GFP_KERNEL);
 203                 if (!ausd)
 204                         return -ENOMEM;
 205
 206                 spi->controller_state = ausd;
 207         }
 208
 209         *ausd = mr;
 210
 211         dev_dbg(&spi->dev,
 212                 "setup: bpw %u mode 0x%x -> mr %d %08x\n",
 213                 bits, spi->mode, spi->chip_select, mr);
 214
 215         return 0;
 216 }
 217
 218 static int at91_usart_spi_transfer_one(struct spi_controller *ctlr,
 219                                        struct spi_device *spi,
 220                                        struct spi_transfer *xfer)
 221 {
 222         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 223
 224         at91_usart_spi_set_xfer_speed(aus, xfer);
 225         aus->xfer_failed = false;
 226         aus->current_transfer = xfer;
 227         aus->current_tx_remaining_bytes = xfer->len;
 228         aus->current_rx_remaining_bytes = xfer->len;
 229
 230         while ((aus->current_tx_remaining_bytes ||
 231                 aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
 232                 at91_usart_spi_read_status(aus);
 233                 at91_usart_spi_tx(aus);
 234                 cpu_relax();
 235         }
 236
 237         if (aus->xfer_failed) {
 238                 dev_err(aus->dev, "Overrun!\n");
 239                 return -EIO;
 240         }
 241
 242         return 0;
 243 }
 244
 245 static int at91_usart_spi_prepare_message(struct spi_controller *ctlr,
 246                                           struct spi_message *message)
 247 {
 248         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 249         struct spi_device *spi = message->spi;
 250         u32 *ausd = spi->controller_state;
 251
 252         at91_usart_spi_writel(aus, CR, US_ENABLE);
 253         at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
 254         at91_usart_spi_writel(aus, MR, *ausd);
 255
 256         return 0;
 257 }
 258
 259 static int at91_usart_spi_unprepare_message(struct spi_controller *ctlr,
 260                                             struct spi_message *message)
 261 {
 262         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 263
 264         at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
 265         at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
 266
 267         return 0;
 268 }
 269
 270 static void at91_usart_spi_cleanup(struct spi_device *spi)
 271 {
 272         struct at91_usart_spi_device *ausd = spi->controller_state;
 273
 274         spi->controller_state = NULL;
 275         kfree(ausd);
 276 }
 277
 278 static void at91_usart_spi_init(struct at91_usart_spi *aus)
 279 {
 280         at91_usart_spi_writel(aus, MR, US_INIT);
 281         at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
 282 }
 283
 284 static int at91_usart_gpio_setup(struct platform_device *pdev)
 285 {
 286         struct device_node *np = pdev->dev.parent->of_node;
 287         int i;
 288         int ret;
 289         int nb;
 290
 291         if (!np)
 292                 return -EINVAL;
 293
 294         nb = of_gpio_named_count(np, "cs-gpios");
 295         for (i = 0; i < nb; i++) {
 296                 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
 297
 298                 if (cs_gpio < 0)
 299                         return cs_gpio;
 300
 301                 if (gpio_is_valid(cs_gpio)) {
 302                         ret = devm_gpio_request_one(&pdev->dev, cs_gpio,
 303                                                     GPIOF_DIR_OUT,
 304                                                     dev_name(&pdev->dev));
 305                         if (ret)
 306                                 return ret;
 307                 }
 308         }
 309
 310         return 0;
 311 }
 312
 313 static int at91_usart_spi_probe(struct platform_device *pdev)
 314 {
 315         struct resource *regs;
 316         struct spi_controller *controller;
 317         struct at91_usart_spi *aus;
 318         struct clk *clk;
 319         int irq;
 320         int ret;
 321
 322         regs = platform_get_resource(to_platform_device(pdev->dev.parent),
 323                                      IORESOURCE_MEM, 0);
 324         if (!regs)
 325                 return -EINVAL;
 326
 327         irq = platform_get_irq(to_platform_device(pdev->dev.parent), 0);
 328         if (irq < 0)
 329                 return irq;
 330
 331         clk = devm_clk_get(pdev->dev.parent, "usart");
 332         if (IS_ERR(clk))
 333                 return PTR_ERR(clk);
 334
 335         ret = -ENOMEM;
 336         controller = spi_alloc_master(&pdev->dev, sizeof(*aus));
 337         if (!controller)
 338                 goto at91_usart_spi_probe_fail;
 339
 340         ret = at91_usart_gpio_setup(pdev);
 341         if (ret)
 342                 goto at91_usart_spi_probe_fail;
 343
 344         controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_CS_HIGH;
 345         controller->dev.of_node = pdev->dev.parent->of_node;
 346         controller->bits_per_word_mask = SPI_BPW_MASK(8);
 347         controller->setup = at91_usart_spi_setup;
 348         controller->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
 349         controller->transfer_one = at91_usart_spi_transfer_one;
 350         controller->prepare_message = at91_usart_spi_prepare_message;
 351         controller->unprepare_message = at91_usart_spi_unprepare_message;
 352         controller->cleanup = at91_usart_spi_cleanup;
 353         controller->max_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
 354                                                 US_MIN_CLK_DIV);
 355         controller->min_speed_hz = DIV_ROUND_UP(clk_get_rate(clk),
 356                                                 US_MAX_CLK_DIV);
 357         platform_set_drvdata(pdev, controller);
 358
 359         aus = spi_master_get_devdata(controller);
 360
 361         aus->dev = &pdev->dev;
 362         aus->regs = devm_ioremap_resource(&pdev->dev, regs);
 363         if (IS_ERR(aus->regs)) {
 364                 ret = PTR_ERR(aus->regs);
 365                 goto at91_usart_spi_probe_fail;
 366         }
 367
 368         aus->irq = irq;
 369         aus->clk = clk;
 370
 371         ret = devm_request_irq(&pdev->dev, irq, at91_usart_spi_interrupt, 0,
 372                                dev_name(&pdev->dev), controller);
 373         if (ret)
 374                 goto at91_usart_spi_probe_fail;
 375
 376         ret = clk_prepare_enable(clk);
 377         if (ret)
 378                 goto at91_usart_spi_probe_fail;
 379
 380         aus->spi_clk = clk_get_rate(clk);
 381         at91_usart_spi_init(aus);
 382
 383         spin_lock_init(&aus->lock);
 384         ret = devm_spi_register_master(&pdev->dev, controller);
 385         if (ret)
 386                 goto at91_usart_fail_register_master;
 387
 388         dev_info(&pdev->dev,
 389                  "AT91 USART SPI Controller version 0x%x at %pa (irq %d)\n",
 390                  at91_usart_spi_readl(aus, VERSION),
 391                  &regs->start, irq);
 392
 393         return 0;
 394
 395 at91_usart_fail_register_master:
 396         clk_disable_unprepare(clk);
 397 at91_usart_spi_probe_fail:
 398         spi_master_put(controller);
 399         return ret;
 400 }
 401
 402 static int at91_usart_spi_remove(struct platform_device *pdev)
 403 {
 404         struct spi_controller *ctlr = platform_get_drvdata(pdev);
 405         struct at91_usart_spi *aus = spi_master_get_devdata(ctlr);
 406
 407         clk_disable_unprepare(aus->clk);
 408
 409         return 0;
 410 }
 411
 412 static const struct of_device_id at91_usart_spi_dt_ids[] = {
 413         { .compatible = "microchip,at91sam9g45-usart-spi"},
 414         { /* sentinel */}
 415 };
 416
 417 MODULE_DEVICE_TABLE(of, at91_usart_spi_dt_ids);
 418
 419 static struct platform_driver at91_usart_spi_driver = {
 420         .driver = {
 421                 .name = "at91_usart_spi",
 422         },
 423         .probe = at91_usart_spi_probe,
 424         .remove = at91_usart_spi_remove,
 425 };
 426
 427 module_platform_driver(at91_usart_spi_driver);
 428
 429 MODULE_DESCRIPTION("Microchip AT91 USART SPI Controller driver");
 430 MODULE_AUTHOR("Radu Pirea <radu.pirea@microchip.com>");
 431 MODULE_LICENSE("GPL v2");
 432 MODULE_ALIAS("platform:at91_usart_spi");