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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / drivers / spi / spi-fsl-dspi.c
blob3082e72e4f6c62ed00651e389381ee2896336c52
1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright 2013 Freescale Semiconductor, Inc.
4 //
5 // Freescale DSPI driver
6 // This file contains a driver for the Freescale DSPI
7
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/dmaengine.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/kernel.h>
17 #include <linux/math64.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/pinctrl/consumer.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/regmap.h>
25 #include <linux/sched.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/spi-fsl-dspi.h>
28 #include <linux/spi/spi_bitbang.h>
29 #include <linux/time.h>
30
31 #define DRIVER_NAME "fsl-dspi"
32
33 #ifdef CONFIG_M5441x
34 #define DSPI_FIFO_SIZE 16
35 #else
36 #define DSPI_FIFO_SIZE 4
37 #endif
38 #define DSPI_DMA_BUFSIZE (DSPI_FIFO_SIZE * 1024)
39
40 #define SPI_MCR 0x00
41 #define SPI_MCR_MASTER (1 << 31)
42 #define SPI_MCR_PCSIS (0x3F << 16)
43 #define SPI_MCR_CLR_TXF (1 << 11)
44 #define SPI_MCR_CLR_RXF (1 << 10)
45 #define SPI_MCR_XSPI (1 << 3)
46
47 #define SPI_TCR 0x08
48 #define SPI_TCR_GET_TCNT(x) (((x) & 0xffff0000) >> 16)
49
50 #define SPI_CTAR(x) (0x0c + (((x) & 0x3) * 4))
51 #define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
52 #define SPI_CTAR_CPOL(x) ((x) << 26)
53 #define SPI_CTAR_CPHA(x) ((x) << 25)
54 #define SPI_CTAR_LSBFE(x) ((x) << 24)
55 #define SPI_CTAR_PCSSCK(x) (((x) & 0x00000003) << 22)
56 #define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
57 #define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
58 #define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
59 #define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
60 #define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
61 #define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
62 #define SPI_CTAR_BR(x) ((x) & 0x0000000f)
63 #define SPI_CTAR_SCALE_BITS 0xf
64
65 #define SPI_CTAR0_SLAVE 0x0c
66
67 #define SPI_SR 0x2c
68 #define SPI_SR_EOQF 0x10000000
69 #define SPI_SR_TCFQF 0x80000000
70 #define SPI_SR_CLEAR 0xdaad0000
71
72 #define SPI_RSER_TFFFE BIT(25)
73 #define SPI_RSER_TFFFD BIT(24)
74 #define SPI_RSER_RFDFE BIT(17)
75 #define SPI_RSER_RFDFD BIT(16)
76
77 #define SPI_RSER 0x30
78 #define SPI_RSER_EOQFE 0x10000000
79 #define SPI_RSER_TCFQE 0x80000000
80
81 #define SPI_PUSHR 0x34
82 #define SPI_PUSHR_CMD_CONT (1 << 15)
83 #define SPI_PUSHR_CONT (SPI_PUSHR_CMD_CONT << 16)
84 #define SPI_PUSHR_CMD_CTAS(x) (((x) & 0x0003) << 12)
85 #define SPI_PUSHR_CTAS(x) (SPI_PUSHR_CMD_CTAS(x) << 16)
86 #define SPI_PUSHR_CMD_EOQ (1 << 11)
87 #define SPI_PUSHR_EOQ (SPI_PUSHR_CMD_EOQ << 16)
88 #define SPI_PUSHR_CMD_CTCNT (1 << 10)
89 #define SPI_PUSHR_CTCNT (SPI_PUSHR_CMD_CTCNT << 16)
90 #define SPI_PUSHR_CMD_PCS(x) ((1 << x) & 0x003f)
91 #define SPI_PUSHR_PCS(x) (SPI_PUSHR_CMD_PCS(x) << 16)
92 #define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
93
94 #define SPI_PUSHR_SLAVE 0x34
95
96 #define SPI_POPR 0x38
97 #define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
98
99 #define SPI_TXFR0 0x3c
100 #define SPI_TXFR1 0x40
101 #define SPI_TXFR2 0x44
102 #define SPI_TXFR3 0x48
103 #define SPI_RXFR0 0x7c
104 #define SPI_RXFR1 0x80
105 #define SPI_RXFR2 0x84
106 #define SPI_RXFR3 0x88
107
108 #define SPI_CTARE(x) (0x11c + (((x) & 0x3) * 4))
109 #define SPI_CTARE_FMSZE(x) (((x) & 0x1) << 16)
110 #define SPI_CTARE_DTCP(x) ((x) & 0x7ff)
111
112 #define SPI_SREX 0x13c
113
114 #define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
115 #define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
116 #define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
117 #define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
118
119 #define SPI_FRAME_EBITS(bits) SPI_CTARE_FMSZE(((bits) - 1) >> 4)
120 #define SPI_FRAME_EBITS_MASK SPI_CTARE_FMSZE(1)
121
122 /* Register offsets for regmap_pushr */
123 #define PUSHR_CMD 0x0
124 #define PUSHR_TX 0x2
125
126 #define SPI_CS_INIT 0x01
127 #define SPI_CS_ASSERT 0x02
128 #define SPI_CS_DROP 0x04
129
130 #define DMA_COMPLETION_TIMEOUT msecs_to_jiffies(3000)
131
132 struct chip_data {
133 u32 ctar_val;
134 u16 void_write_data;
135 };
136
137 enum dspi_trans_mode {
138 DSPI_EOQ_MODE = 0,
139 DSPI_TCFQ_MODE,
140 DSPI_DMA_MODE,
141 };
142
143 struct fsl_dspi_devtype_data {
144 enum dspi_trans_mode trans_mode;
145 u8 max_clock_factor;
146 bool xspi_mode;
147 };
148
149 static const struct fsl_dspi_devtype_data vf610_data = {
150 .trans_mode = DSPI_DMA_MODE,
151 .max_clock_factor = 2,
152 };
153
154 static const struct fsl_dspi_devtype_data ls1021a_v1_data = {
155 .trans_mode = DSPI_TCFQ_MODE,
156 .max_clock_factor = 8,
157 .xspi_mode = true,
158 };
159
160 static const struct fsl_dspi_devtype_data ls2085a_data = {
161 .trans_mode = DSPI_TCFQ_MODE,
162 .max_clock_factor = 8,
163 };
164
165 static const struct fsl_dspi_devtype_data coldfire_data = {
166 .trans_mode = DSPI_EOQ_MODE,
167 .max_clock_factor = 8,
168 };
169
170 struct fsl_dspi_dma {
171 /* Length of transfer in words of DSPI_FIFO_SIZE */
172 u32 curr_xfer_len;
173
174 u32 *tx_dma_buf;
175 struct dma_chan *chan_tx;
176 dma_addr_t tx_dma_phys;
177 struct completion cmd_tx_complete;
178 struct dma_async_tx_descriptor *tx_desc;
179
180 u32 *rx_dma_buf;
181 struct dma_chan *chan_rx;
182 dma_addr_t rx_dma_phys;
183 struct completion cmd_rx_complete;
184 struct dma_async_tx_descriptor *rx_desc;
185 };
186
187 struct fsl_dspi {
188 struct spi_master *master;
189 struct platform_device *pdev;
190
191 struct regmap *regmap;
192 struct regmap *regmap_pushr;
193 int irq;
194 struct clk *clk;
195
196 struct spi_transfer *cur_transfer;
197 struct spi_message *cur_msg;
198 struct chip_data *cur_chip;
199 size_t len;
200 const void *tx;
201 void *rx;
202 void *rx_end;
203 u16 void_write_data;
204 u16 tx_cmd;
205 u8 bits_per_word;
206 u8 bytes_per_word;
207 const struct fsl_dspi_devtype_data *devtype_data;
208
209 wait_queue_head_t waitq;
210 u32 waitflags;
211
212 struct fsl_dspi_dma *dma;
213 };
214
215 static u32 dspi_pop_tx(struct fsl_dspi *dspi)
216 {
217 u32 txdata = 0;
218
219 if (dspi->tx) {
220 if (dspi->bytes_per_word == 1)
221 txdata = *(u8 *)dspi->tx;
222 else if (dspi->bytes_per_word == 2)
223 txdata = *(u16 *)dspi->tx;
224 else /* dspi->bytes_per_word == 4 */
225 txdata = *(u32 *)dspi->tx;
226 dspi->tx += dspi->bytes_per_word;
227 }
228 dspi->len -= dspi->bytes_per_word;
229 return txdata;
230 }
231
232 static u32 dspi_pop_tx_pushr(struct fsl_dspi *dspi)
233 {
234 u16 cmd = dspi->tx_cmd, data = dspi_pop_tx(dspi);
235
236 if (dspi->len > 0)
237 cmd |= SPI_PUSHR_CMD_CONT;
238 return cmd << 16 | data;
239 }
240
241 static void dspi_push_rx(struct fsl_dspi *dspi, u32 rxdata)
242 {
243 if (!dspi->rx)
244 return;
245
246 /* Mask of undefined bits */
247 rxdata &= (1 << dspi->bits_per_word) - 1;
248
249 if (dspi->bytes_per_word == 1)
250 *(u8 *)dspi->rx = rxdata;
251 else if (dspi->bytes_per_word == 2)
252 *(u16 *)dspi->rx = rxdata;
253 else /* dspi->bytes_per_word == 4 */
254 *(u32 *)dspi->rx = rxdata;
255 dspi->rx += dspi->bytes_per_word;
256 }
257
258 static void dspi_tx_dma_callback(void *arg)
259 {
260 struct fsl_dspi *dspi = arg;
261 struct fsl_dspi_dma *dma = dspi->dma;
262
263 complete(&dma->cmd_tx_complete);
264 }
265
266 static void dspi_rx_dma_callback(void *arg)
267 {
268 struct fsl_dspi *dspi = arg;
269 struct fsl_dspi_dma *dma = dspi->dma;
270 int i;
271
272 if (dspi->rx) {
273 for (i = 0; i < dma->curr_xfer_len; i++)
274 dspi_push_rx(dspi, dspi->dma->rx_dma_buf[i]);
275 }
276
277 complete(&dma->cmd_rx_complete);
278 }
279
280 static int dspi_next_xfer_dma_submit(struct fsl_dspi *dspi)
281 {
282 struct fsl_dspi_dma *dma = dspi->dma;
283 struct device *dev = &dspi->pdev->dev;
284 int time_left;
285 int i;
286
287 for (i = 0; i < dma->curr_xfer_len; i++)
288 dspi->dma->tx_dma_buf[i] = dspi_pop_tx_pushr(dspi);
289
290 dma->tx_desc = dmaengine_prep_slave_single(dma->chan_tx,
291 dma->tx_dma_phys,
292 dma->curr_xfer_len *
293 DMA_SLAVE_BUSWIDTH_4_BYTES,
294 DMA_MEM_TO_DEV,
295 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
296 if (!dma->tx_desc) {
297 dev_err(dev, "Not able to get desc for DMA xfer\n");
298 return -EIO;
299 }
300
301 dma->tx_desc->callback = dspi_tx_dma_callback;
302 dma->tx_desc->callback_param = dspi;
303 if (dma_submit_error(dmaengine_submit(dma->tx_desc))) {
304 dev_err(dev, "DMA submit failed\n");
305 return -EINVAL;
306 }
307
308 dma->rx_desc = dmaengine_prep_slave_single(dma->chan_rx,
309 dma->rx_dma_phys,
310 dma->curr_xfer_len *
311 DMA_SLAVE_BUSWIDTH_4_BYTES,
312 DMA_DEV_TO_MEM,
313 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
314 if (!dma->rx_desc) {
315 dev_err(dev, "Not able to get desc for DMA xfer\n");
316 return -EIO;
317 }
318
319 dma->rx_desc->callback = dspi_rx_dma_callback;
320 dma->rx_desc->callback_param = dspi;
321 if (dma_submit_error(dmaengine_submit(dma->rx_desc))) {
322 dev_err(dev, "DMA submit failed\n");
323 return -EINVAL;
324 }
325
326 reinit_completion(&dspi->dma->cmd_rx_complete);
327 reinit_completion(&dspi->dma->cmd_tx_complete);
328
329 dma_async_issue_pending(dma->chan_rx);
330 dma_async_issue_pending(dma->chan_tx);
331
332 time_left = wait_for_completion_timeout(&dspi->dma->cmd_tx_complete,
333 DMA_COMPLETION_TIMEOUT);
334 if (time_left == 0) {
335 dev_err(dev, "DMA tx timeout\n");
336 dmaengine_terminate_all(dma->chan_tx);
337 dmaengine_terminate_all(dma->chan_rx);
338 return -ETIMEDOUT;
339 }
340
341 time_left = wait_for_completion_timeout(&dspi->dma->cmd_rx_complete,
342 DMA_COMPLETION_TIMEOUT);
343 if (time_left == 0) {
344 dev_err(dev, "DMA rx timeout\n");
345 dmaengine_terminate_all(dma->chan_tx);
346 dmaengine_terminate_all(dma->chan_rx);
347 return -ETIMEDOUT;
348 }
349
350 return 0;
351 }
352
353 static int dspi_dma_xfer(struct fsl_dspi *dspi)
354 {
355 struct fsl_dspi_dma *dma = dspi->dma;
356 struct device *dev = &dspi->pdev->dev;
357 struct spi_message *message = dspi->cur_msg;
358 int curr_remaining_bytes;
359 int bytes_per_buffer;
360 int ret = 0;
361
362 curr_remaining_bytes = dspi->len;
363 bytes_per_buffer = DSPI_DMA_BUFSIZE / DSPI_FIFO_SIZE;
364 while (curr_remaining_bytes) {
365 /* Check if current transfer fits the DMA buffer */
366 dma->curr_xfer_len = curr_remaining_bytes
367 / dspi->bytes_per_word;
368 if (dma->curr_xfer_len > bytes_per_buffer)
369 dma->curr_xfer_len = bytes_per_buffer;
370
371 ret = dspi_next_xfer_dma_submit(dspi);
372 if (ret) {
373 dev_err(dev, "DMA transfer failed\n");
374 goto exit;
375
376 } else {
377 const int len =
378 dma->curr_xfer_len * dspi->bytes_per_word;
379 curr_remaining_bytes -= len;
380 message->actual_length += len;
381 if (curr_remaining_bytes < 0)
382 curr_remaining_bytes = 0;
383 }
384 }
385
386 exit:
387 return ret;
388 }
389
390 static int dspi_request_dma(struct fsl_dspi *dspi, phys_addr_t phy_addr)
391 {
392 struct fsl_dspi_dma *dma;
393 struct dma_slave_config cfg;
394 struct device *dev = &dspi->pdev->dev;
395 int ret;
396
397 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL);
398 if (!dma)
399 return -ENOMEM;
400
401 dma->chan_rx = dma_request_slave_channel(dev, "rx");
402 if (!dma->chan_rx) {
403 dev_err(dev, "rx dma channel not available\n");
404 ret = -ENODEV;
405 return ret;
406 }
407
408 dma->chan_tx = dma_request_slave_channel(dev, "tx");
409 if (!dma->chan_tx) {
410 dev_err(dev, "tx dma channel not available\n");
411 ret = -ENODEV;
412 goto err_tx_channel;
413 }
414
415 dma->tx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
416 &dma->tx_dma_phys, GFP_KERNEL);
417 if (!dma->tx_dma_buf) {
418 ret = -ENOMEM;
419 goto err_tx_dma_buf;
420 }
421
422 dma->rx_dma_buf = dma_alloc_coherent(dev, DSPI_DMA_BUFSIZE,
423 &dma->rx_dma_phys, GFP_KERNEL);
424 if (!dma->rx_dma_buf) {
425 ret = -ENOMEM;
426 goto err_rx_dma_buf;
427 }
428
429 cfg.src_addr = phy_addr + SPI_POPR;
430 cfg.dst_addr = phy_addr + SPI_PUSHR;
431 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
432 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
433 cfg.src_maxburst = 1;
434 cfg.dst_maxburst = 1;
435
436 cfg.direction = DMA_DEV_TO_MEM;
437 ret = dmaengine_slave_config(dma->chan_rx, &cfg);
438 if (ret) {
439 dev_err(dev, "can't configure rx dma channel\n");
440 ret = -EINVAL;
441 goto err_slave_config;
442 }
443
444 cfg.direction = DMA_MEM_TO_DEV;
445 ret = dmaengine_slave_config(dma->chan_tx, &cfg);
446 if (ret) {
447 dev_err(dev, "can't configure tx dma channel\n");
448 ret = -EINVAL;
449 goto err_slave_config;
450 }
451
452 dspi->dma = dma;
453 init_completion(&dma->cmd_tx_complete);
454 init_completion(&dma->cmd_rx_complete);
455
456 return 0;
457
458 err_slave_config:
459 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
460 dma->rx_dma_buf, dma->rx_dma_phys);
461 err_rx_dma_buf:
462 dma_free_coherent(dev, DSPI_DMA_BUFSIZE,
463 dma->tx_dma_buf, dma->tx_dma_phys);
464 err_tx_dma_buf:
465 dma_release_channel(dma->chan_tx);
466 err_tx_channel:
467 dma_release_channel(dma->chan_rx);
468
469 devm_kfree(dev, dma);
470 dspi->dma = NULL;
471
472 return ret;
473 }
474
475 static void dspi_release_dma(struct fsl_dspi *dspi)
476 {
477 struct fsl_dspi_dma *dma = dspi->dma;
478 struct device *dev = &dspi->pdev->dev;
479
480 if (dma) {
481 if (dma->chan_tx) {
482 dma_unmap_single(dev, dma->tx_dma_phys,
483 DSPI_DMA_BUFSIZE, DMA_TO_DEVICE);
484 dma_release_channel(dma->chan_tx);
485 }
486
487 if (dma->chan_rx) {
488 dma_unmap_single(dev, dma->rx_dma_phys,
489 DSPI_DMA_BUFSIZE, DMA_FROM_DEVICE);
490 dma_release_channel(dma->chan_rx);
491 }
492 }
493 }
494
495 static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
496 unsigned long clkrate)
497 {
498 /* Valid baud rate pre-scaler values */
499 int pbr_tbl[4] = {2, 3, 5, 7};
500 int brs[16] = { 2, 4, 6, 8,
501 16, 32, 64, 128,
502 256, 512, 1024, 2048,
503 4096, 8192, 16384, 32768 };
504 int scale_needed, scale, minscale = INT_MAX;
505 int i, j;
506
507 scale_needed = clkrate / speed_hz;
508 if (clkrate % speed_hz)
509 scale_needed++;
510
511 for (i = 0; i < ARRAY_SIZE(brs); i++)
512 for (j = 0; j < ARRAY_SIZE(pbr_tbl); j++) {
513 scale = brs[i] * pbr_tbl[j];
514 if (scale >= scale_needed) {
515 if (scale < minscale) {
516 minscale = scale;
517 *br = i;
518 *pbr = j;
519 }
520 break;
521 }
522 }
523
524 if (minscale == INT_MAX) {
525 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld, we use the max prescaler value.\n",
526 speed_hz, clkrate);
527 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
528 *br = ARRAY_SIZE(brs) - 1;
529 }
530 }
531
532 static void ns_delay_scale(char *psc, char *sc, int delay_ns,
533 unsigned long clkrate)
534 {
535 int pscale_tbl[4] = {1, 3, 5, 7};
536 int scale_needed, scale, minscale = INT_MAX;
537 int i, j;
538 u32 remainder;
539
540 scale_needed = div_u64_rem((u64)delay_ns * clkrate, NSEC_PER_SEC,
541 &remainder);
542 if (remainder)
543 scale_needed++;
544
545 for (i = 0; i < ARRAY_SIZE(pscale_tbl); i++)
546 for (j = 0; j <= SPI_CTAR_SCALE_BITS; j++) {
547 scale = pscale_tbl[i] * (2 << j);
548 if (scale >= scale_needed) {
549 if (scale < minscale) {
550 minscale = scale;
551 *psc = i;
552 *sc = j;
553 }
554 break;
555 }
556 }
557
558 if (minscale == INT_MAX) {
559 pr_warn("Cannot find correct scale values for %dns delay at clkrate %ld, using max prescaler value",
560 delay_ns, clkrate);
561 *psc = ARRAY_SIZE(pscale_tbl) - 1;
562 *sc = SPI_CTAR_SCALE_BITS;
563 }
564 }
565
566 static void fifo_write(struct fsl_dspi *dspi)
567 {
568 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pop_tx_pushr(dspi));
569 }
570
571 static void cmd_fifo_write(struct fsl_dspi *dspi)
572 {
573 u16 cmd = dspi->tx_cmd;
574
575 if (dspi->len > 0)
576 cmd |= SPI_PUSHR_CMD_CONT;
577 regmap_write(dspi->regmap_pushr, PUSHR_CMD, cmd);
578 }
579
580 static void tx_fifo_write(struct fsl_dspi *dspi, u16 txdata)
581 {
582 regmap_write(dspi->regmap_pushr, PUSHR_TX, txdata);
583 }
584
585 static void dspi_tcfq_write(struct fsl_dspi *dspi)
586 {
587 /* Clear transfer count */
588 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
589
590 if (dspi->devtype_data->xspi_mode && dspi->bits_per_word > 16) {
591 /* Write two TX FIFO entries first, and then the corresponding
592 * CMD FIFO entry.
593 */
594 u32 data = dspi_pop_tx(dspi);
595
596 if (dspi->cur_chip->ctar_val & SPI_CTAR_LSBFE(1)) {
597 /* LSB */
598 tx_fifo_write(dspi, data & 0xFFFF);
599 tx_fifo_write(dspi, data >> 16);
600 } else {
601 /* MSB */
602 tx_fifo_write(dspi, data >> 16);
603 tx_fifo_write(dspi, data & 0xFFFF);
604 }
605 cmd_fifo_write(dspi);
606 } else {
607 /* Write one entry to both TX FIFO and CMD FIFO
608 * simultaneously.
609 */
610 fifo_write(dspi);
611 }
612 }
613
614 static u32 fifo_read(struct fsl_dspi *dspi)
615 {
616 u32 rxdata = 0;
617
618 regmap_read(dspi->regmap, SPI_POPR, &rxdata);
619 return rxdata;
620 }
621
622 static void dspi_tcfq_read(struct fsl_dspi *dspi)
623 {
624 dspi_push_rx(dspi, fifo_read(dspi));
625 }
626
627 static void dspi_eoq_write(struct fsl_dspi *dspi)
628 {
629 int fifo_size = DSPI_FIFO_SIZE;
630 u16 xfer_cmd = dspi->tx_cmd;
631
632 /* Fill TX FIFO with as many transfers as possible */
633 while (dspi->len && fifo_size--) {
634 dspi->tx_cmd = xfer_cmd;
635 /* Request EOQF for last transfer in FIFO */
636 if (dspi->len == dspi->bytes_per_word || fifo_size == 0)
637 dspi->tx_cmd |= SPI_PUSHR_CMD_EOQ;
638 /* Clear transfer count for first transfer in FIFO */
639 if (fifo_size == (DSPI_FIFO_SIZE - 1))
640 dspi->tx_cmd |= SPI_PUSHR_CMD_CTCNT;
641 /* Write combined TX FIFO and CMD FIFO entry */
642 fifo_write(dspi);
643 }
644 }
645
646 static void dspi_eoq_read(struct fsl_dspi *dspi)
647 {
648 int fifo_size = DSPI_FIFO_SIZE;
649
650 /* Read one FIFO entry at and push to rx buffer */
651 while ((dspi->rx < dspi->rx_end) && fifo_size--)
652 dspi_push_rx(dspi, fifo_read(dspi));
653 }
654
655 static int dspi_transfer_one_message(struct spi_master *master,
656 struct spi_message *message)
657 {
658 struct fsl_dspi *dspi = spi_master_get_devdata(master);
659 struct spi_device *spi = message->spi;
660 struct spi_transfer *transfer;
661 int status = 0;
662 enum dspi_trans_mode trans_mode;
663
664 message->actual_length = 0;
665
666 list_for_each_entry(transfer, &message->transfers, transfer_list) {
667 dspi->cur_transfer = transfer;
668 dspi->cur_msg = message;
669 dspi->cur_chip = spi_get_ctldata(spi);
670 /* Prepare command word for CMD FIFO */
671 dspi->tx_cmd = SPI_PUSHR_CMD_CTAS(0) |
672 SPI_PUSHR_CMD_PCS(spi->chip_select);
673 if (list_is_last(&dspi->cur_transfer->transfer_list,
674 &dspi->cur_msg->transfers)) {
675 /* Leave PCS activated after last transfer when
676 * cs_change is set.
677 */
678 if (transfer->cs_change)
679 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
680 } else {
681 /* Keep PCS active between transfers in same message
682 * when cs_change is not set, and de-activate PCS
683 * between transfers in the same message when
684 * cs_change is set.
685 */
686 if (!transfer->cs_change)
687 dspi->tx_cmd |= SPI_PUSHR_CMD_CONT;
688 }
689
690 dspi->void_write_data = dspi->cur_chip->void_write_data;
691
692 dspi->tx = transfer->tx_buf;
693 dspi->rx = transfer->rx_buf;
694 dspi->rx_end = dspi->rx + transfer->len;
695 dspi->len = transfer->len;
696 /* Validated transfer specific frame size (defaults applied) */
697 dspi->bits_per_word = transfer->bits_per_word;
698 if (transfer->bits_per_word <= 8)
699 dspi->bytes_per_word = 1;
700 else if (transfer->bits_per_word <= 16)
701 dspi->bytes_per_word = 2;
702 else
703 dspi->bytes_per_word = 4;
704
705 regmap_update_bits(dspi->regmap, SPI_MCR,
706 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF,
707 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF);
708 regmap_write(dspi->regmap, SPI_CTAR(0),
709 dspi->cur_chip->ctar_val |
710 SPI_FRAME_BITS(transfer->bits_per_word));
711 if (dspi->devtype_data->xspi_mode)
712 regmap_write(dspi->regmap, SPI_CTARE(0),
713 SPI_FRAME_EBITS(transfer->bits_per_word)
714 | SPI_CTARE_DTCP(1));
715
716 trans_mode = dspi->devtype_data->trans_mode;
717 switch (trans_mode) {
718 case DSPI_EOQ_MODE:
719 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
720 dspi_eoq_write(dspi);
721 break;
722 case DSPI_TCFQ_MODE:
723 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_TCFQE);
724 dspi_tcfq_write(dspi);
725 break;
726 case DSPI_DMA_MODE:
727 regmap_write(dspi->regmap, SPI_RSER,
728 SPI_RSER_TFFFE | SPI_RSER_TFFFD |
729 SPI_RSER_RFDFE | SPI_RSER_RFDFD);
730 status = dspi_dma_xfer(dspi);
731 break;
732 default:
733 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
734 trans_mode);
735 status = -EINVAL;
736 goto out;
737 }
738
739 if (trans_mode != DSPI_DMA_MODE) {
740 if (wait_event_interruptible(dspi->waitq,
741 dspi->waitflags))
742 dev_err(&dspi->pdev->dev,
743 "wait transfer complete fail!\n");
744 dspi->waitflags = 0;
745 }
746
747 if (transfer->delay_usecs)
748 udelay(transfer->delay_usecs);
749 }
750
751 out:
752 message->status = status;
753 spi_finalize_current_message(master);
754
755 return status;
756 }
757
758 static int dspi_setup(struct spi_device *spi)
759 {
760 struct chip_data *chip;
761 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
762 struct fsl_dspi_platform_data *pdata;
763 u32 cs_sck_delay = 0, sck_cs_delay = 0;
764 unsigned char br = 0, pbr = 0, pcssck = 0, cssck = 0;
765 unsigned char pasc = 0, asc = 0;
766 unsigned long clkrate;
767
768 /* Only alloc on first setup */
769 chip = spi_get_ctldata(spi);
770 if (chip == NULL) {
771 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
772 if (!chip)
773 return -ENOMEM;
774 }
775
776 pdata = dev_get_platdata(&dspi->pdev->dev);
777
778 if (!pdata) {
779 of_property_read_u32(spi->dev.of_node, "fsl,spi-cs-sck-delay",
780 &cs_sck_delay);
781
782 of_property_read_u32(spi->dev.of_node, "fsl,spi-sck-cs-delay",
783 &sck_cs_delay);
784 } else {
785 cs_sck_delay = pdata->cs_sck_delay;
786 sck_cs_delay = pdata->sck_cs_delay;
787 }
788
789 chip->void_write_data = 0;
790
791 clkrate = clk_get_rate(dspi->clk);
792 hz_to_spi_baud(&pbr, &br, spi->max_speed_hz, clkrate);
793
794 /* Set PCS to SCK delay scale values */
795 ns_delay_scale(&pcssck, &cssck, cs_sck_delay, clkrate);
796
797 /* Set After SCK delay scale values */
798 ns_delay_scale(&pasc, &asc, sck_cs_delay, clkrate);
799
800 chip->ctar_val = SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
801 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
802 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
803 | SPI_CTAR_PCSSCK(pcssck)
804 | SPI_CTAR_CSSCK(cssck)
805 | SPI_CTAR_PASC(pasc)
806 | SPI_CTAR_ASC(asc)
807 | SPI_CTAR_PBR(pbr)
808 | SPI_CTAR_BR(br);
809
810 spi_set_ctldata(spi, chip);
811
812 return 0;
813 }
814
815 static void dspi_cleanup(struct spi_device *spi)
816 {
817 struct chip_data *chip = spi_get_ctldata((struct spi_device *)spi);
818
819 dev_dbg(&spi->dev, "spi_device %u.%u cleanup\n",
820 spi->master->bus_num, spi->chip_select);
821
822 kfree(chip);
823 }
824
825 static irqreturn_t dspi_interrupt(int irq, void *dev_id)
826 {
827 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
828 struct spi_message *msg = dspi->cur_msg;
829 enum dspi_trans_mode trans_mode;
830 u32 spi_sr, spi_tcr;
831 u16 spi_tcnt;
832
833 regmap_read(dspi->regmap, SPI_SR, &spi_sr);
834 regmap_write(dspi->regmap, SPI_SR, spi_sr);
835
836
837 if (spi_sr & (SPI_SR_EOQF | SPI_SR_TCFQF)) {
838 /* Get transfer counter (in number of SPI transfers). It was
839 * reset to 0 when transfer(s) were started.
840 */
841 regmap_read(dspi->regmap, SPI_TCR, &spi_tcr);
842 spi_tcnt = SPI_TCR_GET_TCNT(spi_tcr);
843 /* Update total number of bytes that were transferred */
844 msg->actual_length += spi_tcnt * dspi->bytes_per_word;
845
846 trans_mode = dspi->devtype_data->trans_mode;
847 switch (trans_mode) {
848 case DSPI_EOQ_MODE:
849 dspi_eoq_read(dspi);
850 break;
851 case DSPI_TCFQ_MODE:
852 dspi_tcfq_read(dspi);
853 break;
854 default:
855 dev_err(&dspi->pdev->dev, "unsupported trans_mode %u\n",
856 trans_mode);
857 return IRQ_HANDLED;
858 }
859
860 if (!dspi->len) {
861 dspi->waitflags = 1;
862 wake_up_interruptible(&dspi->waitq);
863 } else {
864 switch (trans_mode) {
865 case DSPI_EOQ_MODE:
866 dspi_eoq_write(dspi);
867 break;
868 case DSPI_TCFQ_MODE:
869 dspi_tcfq_write(dspi);
870 break;
871 default:
872 dev_err(&dspi->pdev->dev,
873 "unsupported trans_mode %u\n",
874 trans_mode);
875 }
876 }
877 }
878
879 return IRQ_HANDLED;
880 }
881
882 static const struct of_device_id fsl_dspi_dt_ids[] = {
883 { .compatible = "fsl,vf610-dspi", .data = &vf610_data, },
884 { .compatible = "fsl,ls1021a-v1.0-dspi", .data = &ls1021a_v1_data, },
885 { .compatible = "fsl,ls2085a-dspi", .data = &ls2085a_data, },
886 { /* sentinel */ }
887 };
888 MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
889
890 #ifdef CONFIG_PM_SLEEP
891 static int dspi_suspend(struct device *dev)
892 {
893 struct spi_master *master = dev_get_drvdata(dev);
894 struct fsl_dspi *dspi = spi_master_get_devdata(master);
895
896 spi_master_suspend(master);
897 clk_disable_unprepare(dspi->clk);
898
899 pinctrl_pm_select_sleep_state(dev);
900
901 return 0;
902 }
903
904 static int dspi_resume(struct device *dev)
905 {
906 struct spi_master *master = dev_get_drvdata(dev);
907 struct fsl_dspi *dspi = spi_master_get_devdata(master);
908 int ret;
909
910 pinctrl_pm_select_default_state(dev);
911
912 ret = clk_prepare_enable(dspi->clk);
913 if (ret)
914 return ret;
915 spi_master_resume(master);
916
917 return 0;
918 }
919 #endif /* CONFIG_PM_SLEEP */
920
921 static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
922
923 static const struct regmap_range dspi_volatile_ranges[] = {
924 regmap_reg_range(SPI_MCR, SPI_TCR),
925 regmap_reg_range(SPI_SR, SPI_SR),
926 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
927 };
928
929 static const struct regmap_access_table dspi_volatile_table = {
930 .yes_ranges = dspi_volatile_ranges,
931 .n_yes_ranges = ARRAY_SIZE(dspi_volatile_ranges),
932 };
933
934 static const struct regmap_config dspi_regmap_config = {
935 .reg_bits = 32,
936 .val_bits = 32,
937 .reg_stride = 4,
938 .max_register = 0x88,
939 .volatile_table = &dspi_volatile_table,
940 };
941
942 static const struct regmap_range dspi_xspi_volatile_ranges[] = {
943 regmap_reg_range(SPI_MCR, SPI_TCR),
944 regmap_reg_range(SPI_SR, SPI_SR),
945 regmap_reg_range(SPI_PUSHR, SPI_RXFR3),
946 regmap_reg_range(SPI_SREX, SPI_SREX),
947 };
948
949 static const struct regmap_access_table dspi_xspi_volatile_table = {
950 .yes_ranges = dspi_xspi_volatile_ranges,
951 .n_yes_ranges = ARRAY_SIZE(dspi_xspi_volatile_ranges),
952 };
953
954 static const struct regmap_config dspi_xspi_regmap_config[] = {
955 {
956 .reg_bits = 32,
957 .val_bits = 32,
958 .reg_stride = 4,
959 .max_register = 0x13c,
960 .volatile_table = &dspi_xspi_volatile_table,
961 },
962 {
963 .name = "pushr",
964 .reg_bits = 16,
965 .val_bits = 16,
966 .reg_stride = 2,
967 .max_register = 0x2,
968 },
969 };
970
971 static void dspi_init(struct fsl_dspi *dspi)
972 {
973 regmap_write(dspi->regmap, SPI_MCR, SPI_MCR_MASTER | SPI_MCR_PCSIS |
974 (dspi->devtype_data->xspi_mode ? SPI_MCR_XSPI : 0));
975 regmap_write(dspi->regmap, SPI_SR, SPI_SR_CLEAR);
976 if (dspi->devtype_data->xspi_mode)
977 regmap_write(dspi->regmap, SPI_CTARE(0),
978 SPI_CTARE_FMSZE(0) | SPI_CTARE_DTCP(1));
979 }
980
981 static int dspi_probe(struct platform_device *pdev)
982 {
983 struct device_node *np = pdev->dev.of_node;
984 struct spi_master *master;
985 struct fsl_dspi *dspi;
986 struct resource *res;
987 const struct regmap_config *regmap_config;
988 void __iomem *base;
989 struct fsl_dspi_platform_data *pdata;
990 int ret = 0, cs_num, bus_num;
991
992 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
993 if (!master)
994 return -ENOMEM;
995
996 dspi = spi_master_get_devdata(master);
997 dspi->pdev = pdev;
998 dspi->master = master;
999
1000 master->transfer = NULL;
1001 master->setup = dspi_setup;
1002 master->transfer_one_message = dspi_transfer_one_message;
1003 master->dev.of_node = pdev->dev.of_node;
1004
1005 master->cleanup = dspi_cleanup;
1006 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1007
1008 pdata = dev_get_platdata(&pdev->dev);
1009 if (pdata) {
1010 master->num_chipselect = pdata->cs_num;
1011 master->bus_num = pdata->bus_num;
1012
1013 dspi->devtype_data = &coldfire_data;
1014 } else {
1015
1016 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
1017 if (ret < 0) {
1018 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
1019 goto out_master_put;
1020 }
1021 master->num_chipselect = cs_num;
1022
1023 ret = of_property_read_u32(np, "bus-num", &bus_num);
1024 if (ret < 0) {
1025 dev_err(&pdev->dev, "can't get bus-num\n");
1026 goto out_master_put;
1027 }
1028 master->bus_num = bus_num;
1029
1030 dspi->devtype_data = of_device_get_match_data(&pdev->dev);
1031 if (!dspi->devtype_data) {
1032 dev_err(&pdev->dev, "can't get devtype_data\n");
1033 ret = -EFAULT;
1034 goto out_master_put;
1035 }
1036 }
1037
1038 if (dspi->devtype_data->xspi_mode)
1039 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1040 else
1041 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1042
1043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1044 base = devm_ioremap_resource(&pdev->dev, res);
1045 if (IS_ERR(base)) {
1046 ret = PTR_ERR(base);
1047 goto out_master_put;
1048 }
1049
1050 if (dspi->devtype_data->xspi_mode)
1051 regmap_config = &dspi_xspi_regmap_config[0];
1052 else
1053 regmap_config = &dspi_regmap_config;
1054 dspi->regmap = devm_regmap_init_mmio(&pdev->dev, base, regmap_config);
1055 if (IS_ERR(dspi->regmap)) {
1056 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
1057 PTR_ERR(dspi->regmap));
1058 ret = PTR_ERR(dspi->regmap);
1059 goto out_master_put;
1060 }
1061
1062 if (dspi->devtype_data->xspi_mode) {
1063 dspi->regmap_pushr = devm_regmap_init_mmio(
1064 &pdev->dev, base + SPI_PUSHR,
1065 &dspi_xspi_regmap_config[1]);
1066 if (IS_ERR(dspi->regmap_pushr)) {
1067 dev_err(&pdev->dev,
1068 "failed to init pushr regmap: %ld\n",
1069 PTR_ERR(dspi->regmap_pushr));
1070 ret = PTR_ERR(dspi->regmap_pushr);
1071 goto out_master_put;
1072 }
1073 }
1074
1075 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
1076 if (IS_ERR(dspi->clk)) {
1077 ret = PTR_ERR(dspi->clk);
1078 dev_err(&pdev->dev, "unable to get clock\n");
1079 goto out_master_put;
1080 }
1081 ret = clk_prepare_enable(dspi->clk);
1082 if (ret)
1083 goto out_master_put;
1084
1085 dspi_init(dspi);
1086 dspi->irq = platform_get_irq(pdev, 0);
1087 if (dspi->irq < 0) {
1088 dev_err(&pdev->dev, "can't get platform irq\n");
1089 ret = dspi->irq;
1090 goto out_clk_put;
1091 }
1092
1093 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
1094 pdev->name, dspi);
1095 if (ret < 0) {
1096 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
1097 goto out_clk_put;
1098 }
1099
1100 if (dspi->devtype_data->trans_mode == DSPI_DMA_MODE) {
1101 ret = dspi_request_dma(dspi, res->start);
1102 if (ret < 0) {
1103 dev_err(&pdev->dev, "can't get dma channels\n");
1104 goto out_clk_put;
1105 }
1106 }
1107
1108 master->max_speed_hz =
1109 clk_get_rate(dspi->clk) / dspi->devtype_data->max_clock_factor;
1110
1111 init_waitqueue_head(&dspi->waitq);
1112 platform_set_drvdata(pdev, master);
1113
1114 ret = spi_register_master(master);
1115 if (ret != 0) {
1116 dev_err(&pdev->dev, "Problem registering DSPI master\n");
1117 goto out_clk_put;
1118 }
1119
1120 return ret;
1121
1122 out_clk_put:
1123 clk_disable_unprepare(dspi->clk);
1124 out_master_put:
1125 spi_master_put(master);
1126
1127 return ret;
1128 }
1129
1130 static int dspi_remove(struct platform_device *pdev)
1131 {
1132 struct spi_master *master = platform_get_drvdata(pdev);
1133 struct fsl_dspi *dspi = spi_master_get_devdata(master);
1134
1135 /* Disconnect from the SPI framework */
1136 dspi_release_dma(dspi);
1137 clk_disable_unprepare(dspi->clk);
1138 spi_unregister_master(dspi->master);
1139
1140 return 0;
1141 }
1142
1143 static struct platform_driver fsl_dspi_driver = {
1144 .driver.name = DRIVER_NAME,
1145 .driver.of_match_table = fsl_dspi_dt_ids,
1146 .driver.owner = THIS_MODULE,
1147 .driver.pm = &dspi_pm,
1148 .probe = dspi_probe,
1149 .remove = dspi_remove,
1150 };
1151 module_platform_driver(fsl_dspi_driver);
1152
1153 MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
1154 MODULE_LICENSE("GPL");
1155 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support