include/dt-bindings/reset/mt7622-reset.h

   1 /*
   2  * Copyright (c) 2017 MediaTek Inc.
   3  * Author: Sean Wang <sean.wang@mediatek.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #ifndef _DT_BINDINGS_RESET_CONTROLLER_MT7622
  16 #define _DT_BINDINGS_RESET_CONTROLLER_MT7622
  17
  18 /* INFRACFG resets */
  19 #define MT7622_INFRA_EMI_REG_RST                0
  20 #define MT7622_INFRA_DRAMC0_A0_RST              1
  21 #define MT7622_INFRA_APCIRQ_EINT_RST            3
  22 #define MT7622_INFRA_APXGPT_RST                 4
  23 #define MT7622_INFRA_SCPSYS_RST                 5
  24 #define MT7622_INFRA_PMIC_WRAP_RST              7
  25 #define MT7622_INFRA_IRRX_RST                   9
  26 #define MT7622_INFRA_EMI_RST                    16
  27 #define MT7622_INFRA_WED0_RST                   17
  28 #define MT7622_INFRA_DRAMC_RST                  18
  29 #define MT7622_INFRA_CCI_INTF_RST               19
  30 #define MT7622_INFRA_TRNG_RST                   21
  31 #define MT7622_INFRA_SYSIRQ_RST                 22
  32 #define MT7622_INFRA_WED1_RST                   25
  33
  34 /* PERICFG Subsystem resets */
  35 #define MT7622_PERI_UART0_SW_RST                0
  36 #define MT7622_PERI_UART1_SW_RST                1
  37 #define MT7622_PERI_UART2_SW_RST                2
  38 #define MT7622_PERI_UART3_SW_RST                3
  39 #define MT7622_PERI_UART4_SW_RST                4
  40 #define MT7622_PERI_BTIF_SW_RST                 6
  41 #define MT7622_PERI_PWM_SW_RST                  8
  42 #define MT7622_PERI_AUXADC_SW_RST               10
  43 #define MT7622_PERI_DMA_SW_RST                  11
  44 #define MT7622_PERI_IRTX_SW_RST                 13
  45 #define MT7622_PERI_NFI_SW_RST                  14
  46 #define MT7622_PERI_THERM_SW_RST                16
  47 #define MT7622_PERI_MSDC0_SW_RST                19
  48 #define MT7622_PERI_MSDC1_SW_RST                20
  49 #define MT7622_PERI_I2C0_SW_RST                 22
  50 #define MT7622_PERI_I2C1_SW_RST                 23
  51 #define MT7622_PERI_I2C2_SW_RST                 24
  52 #define MT7622_PERI_SPI0_SW_RST                 33
  53 #define MT7622_PERI_SPI1_SW_RST                 34
  54 #define MT7622_PERI_FLASHIF_SW_RST              36
  55
  56 /* TOPRGU resets */
  57 #define MT7622_TOPRGU_INFRA_RST                 0
  58 #define MT7622_TOPRGU_ETHDMA_RST                1
  59 #define MT7622_TOPRGU_DDRPHY_RST                6
  60 #define MT7622_TOPRGU_INFRA_AO_RST              8
  61 #define MT7622_TOPRGU_CONN_RST                  9
  62 #define MT7622_TOPRGU_APMIXED_RST               10
  63 #define MT7622_TOPRGU_CONN_MCU_RST              12
  64
  65 /* PCIe/SATA Subsystem resets */
  66 #define MT7622_SATA_PHY_REG_RST                 12
  67 #define MT7622_SATA_PHY_SW_RST                  13
  68 #define MT7622_SATA_AXI_BUS_RST                 15
  69 #define MT7622_PCIE1_CORE_RST                   19
  70 #define MT7622_PCIE1_MMIO_RST                   20
  71 #define MT7622_PCIE1_HRST                       21
  72 #define MT7622_PCIE1_USER_RST                   22
  73 #define MT7622_PCIE1_PIPE_RST                   23
  74 #define MT7622_PCIE0_CORE_RST                   27
  75 #define MT7622_PCIE0_MMIO_RST                   28
  76 #define MT7622_PCIE0_HRST                       29
  77 #define MT7622_PCIE0_USER_RST                   30
  78 #define MT7622_PCIE0_PIPE_RST                   31
  79
  80 /* SSUSB Subsystem resets */
  81 #define MT7622_SSUSB_PHY_PWR_RST                3
  82 #define MT7622_SSUSB_MAC_PWR_RST                4
  83
  84 /* ETHSYS Subsystem resets */
  85 #define MT7622_ETHSYS_SYS_RST                   0
  86 #define MT7622_ETHSYS_MCM_RST                   2
  87 #define MT7622_ETHSYS_HSDMA_RST                 5
  88 #define MT7622_ETHSYS_FE_RST                    6
  89 #define MT7622_ETHSYS_GMAC_RST                  23
  90 #define MT7622_ETHSYS_EPHY_RST                  24
  91 #define MT7622_ETHSYS_CRYPTO_RST                29
  92 #define MT7622_ETHSYS_PPE_RST                   31
  93
  94 #endif  /* _DT_BINDINGS_RESET_CONTROLLER_MT7622 */