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perf tools: Don't clone maps from parent when synthesizing forks
[linux/fpc-iii.git] / include / uapi / drm / amdgpu_drm.h
blob1ceec56de0157671c6a42af07322ffb7fb8e1731
1 /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * Copyright 2014 Advanced Micro Devices, Inc.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 * OTHER DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32 #ifndef __AMDGPU_DRM_H__
33 #define __AMDGPU_DRM_H__
34
35 #include "drm.h"
36
37 #if defined(__cplusplus)
38 extern "C" {
39 #endif
40
41 #define DRM_AMDGPU_GEM_CREATE 0x00
42 #define DRM_AMDGPU_GEM_MMAP 0x01
43 #define DRM_AMDGPU_CTX 0x02
44 #define DRM_AMDGPU_BO_LIST 0x03
45 #define DRM_AMDGPU_CS 0x04
46 #define DRM_AMDGPU_INFO 0x05
47 #define DRM_AMDGPU_GEM_METADATA 0x06
48 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
49 #define DRM_AMDGPU_GEM_VA 0x08
50 #define DRM_AMDGPU_WAIT_CS 0x09
51 #define DRM_AMDGPU_GEM_OP 0x10
52 #define DRM_AMDGPU_GEM_USERPTR 0x11
53 #define DRM_AMDGPU_WAIT_FENCES 0x12
54 #define DRM_AMDGPU_VM 0x13
55 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
56 #define DRM_AMDGPU_SCHED 0x15
57
58 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
59 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
60 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
61 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
62 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
63 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
64 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
65 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
66 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
67 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
68 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
69 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
70 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
71 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
72 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
73 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
74
75 /**
76 * DOC: memory domains
77 *
78 * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible.
79 * Memory in this pool could be swapped out to disk if there is pressure.
80 *
81 * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
82 * GPU's virtual address space via gart. Gart memory linearizes non-contiguous
83 * pages of system memory, allows GPU access system memory in a linezrized
84 * fashion.
85 *
86 * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
87 * carved out by the BIOS.
88 *
89 * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data
90 * across shader threads.
91 *
92 * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the
93 * execution of all the waves on a device.
94 *
95 * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
96 * for appending data.
97 */
98 #define AMDGPU_GEM_DOMAIN_CPU 0x1
99 #define AMDGPU_GEM_DOMAIN_GTT 0x2
100 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
101 #define AMDGPU_GEM_DOMAIN_GDS 0x8
102 #define AMDGPU_GEM_DOMAIN_GWS 0x10
103 #define AMDGPU_GEM_DOMAIN_OA 0x20
104 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
105 AMDGPU_GEM_DOMAIN_GTT | \
106 AMDGPU_GEM_DOMAIN_VRAM | \
107 AMDGPU_GEM_DOMAIN_GDS | \
108 AMDGPU_GEM_DOMAIN_GWS | \
109 AMDGPU_GEM_DOMAIN_OA)
110
111 /* Flag that CPU access will be required for the case of VRAM domain */
112 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
113 /* Flag that CPU access will not work, this VRAM domain is invisible */
114 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
115 /* Flag that USWC attributes should be used for GTT */
116 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
117 /* Flag that the memory should be in VRAM and cleared */
118 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
119 /* Flag that create shadow bo(GTT) while allocating vram bo */
120 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
121 /* Flag that allocating the BO should use linear VRAM */
122 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
123 /* Flag that BO is always valid in this VM */
124 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
125 /* Flag that BO sharing will be explicitly synchronized */
126 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
127 /* Flag that indicates allocating MQD gart on GFX9, where the mtype
128 * for the second page onward should be set to NC.
129 */
130 #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8)
131
132 struct drm_amdgpu_gem_create_in {
133 /** the requested memory size */
134 __u64 bo_size;
135 /** physical start_addr alignment in bytes for some HW requirements */
136 __u64 alignment;
137 /** the requested memory domains */
138 __u64 domains;
139 /** allocation flags */
140 __u64 domain_flags;
141 };
142
143 struct drm_amdgpu_gem_create_out {
144 /** returned GEM object handle */
145 __u32 handle;
146 __u32 _pad;
147 };
148
149 union drm_amdgpu_gem_create {
150 struct drm_amdgpu_gem_create_in in;
151 struct drm_amdgpu_gem_create_out out;
152 };
153
154 /** Opcode to create new residency list. */
155 #define AMDGPU_BO_LIST_OP_CREATE 0
156 /** Opcode to destroy previously created residency list */
157 #define AMDGPU_BO_LIST_OP_DESTROY 1
158 /** Opcode to update resource information in the list */
159 #define AMDGPU_BO_LIST_OP_UPDATE 2
160
161 struct drm_amdgpu_bo_list_in {
162 /** Type of operation */
163 __u32 operation;
164 /** Handle of list or 0 if we want to create one */
165 __u32 list_handle;
166 /** Number of BOs in list */
167 __u32 bo_number;
168 /** Size of each element describing BO */
169 __u32 bo_info_size;
170 /** Pointer to array describing BOs */
171 __u64 bo_info_ptr;
172 };
173
174 struct drm_amdgpu_bo_list_entry {
175 /** Handle of BO */
176 __u32 bo_handle;
177 /** New (if specified) BO priority to be used during migration */
178 __u32 bo_priority;
179 };
180
181 struct drm_amdgpu_bo_list_out {
182 /** Handle of resource list */
183 __u32 list_handle;
184 __u32 _pad;
185 };
186
187 union drm_amdgpu_bo_list {
188 struct drm_amdgpu_bo_list_in in;
189 struct drm_amdgpu_bo_list_out out;
190 };
191
192 /* context related */
193 #define AMDGPU_CTX_OP_ALLOC_CTX 1
194 #define AMDGPU_CTX_OP_FREE_CTX 2
195 #define AMDGPU_CTX_OP_QUERY_STATE 3
196 #define AMDGPU_CTX_OP_QUERY_STATE2 4
197
198 /* GPU reset status */
199 #define AMDGPU_CTX_NO_RESET 0
200 /* this the context caused it */
201 #define AMDGPU_CTX_GUILTY_RESET 1
202 /* some other context caused it */
203 #define AMDGPU_CTX_INNOCENT_RESET 2
204 /* unknown cause */
205 #define AMDGPU_CTX_UNKNOWN_RESET 3
206
207 /* indicate gpu reset occured after ctx created */
208 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
209 /* indicate vram lost occured after ctx created */
210 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
211 /* indicate some job from this context once cause gpu hang */
212 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
213
214 /* Context priority level */
215 #define AMDGPU_CTX_PRIORITY_UNSET -2048
216 #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023
217 #define AMDGPU_CTX_PRIORITY_LOW -512
218 #define AMDGPU_CTX_PRIORITY_NORMAL 0
219 /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */
220 #define AMDGPU_CTX_PRIORITY_HIGH 512
221 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
222
223 struct drm_amdgpu_ctx_in {
224 /** AMDGPU_CTX_OP_* */
225 __u32 op;
226 /** For future use, no flags defined so far */
227 __u32 flags;
228 __u32 ctx_id;
229 __s32 priority;
230 };
231
232 union drm_amdgpu_ctx_out {
233 struct {
234 __u32 ctx_id;
235 __u32 _pad;
236 } alloc;
237
238 struct {
239 /** For future use, no flags defined so far */
240 __u64 flags;
241 /** Number of resets caused by this context so far. */
242 __u32 hangs;
243 /** Reset status since the last call of the ioctl. */
244 __u32 reset_status;
245 } state;
246 };
247
248 union drm_amdgpu_ctx {
249 struct drm_amdgpu_ctx_in in;
250 union drm_amdgpu_ctx_out out;
251 };
252
253 /* vm ioctl */
254 #define AMDGPU_VM_OP_RESERVE_VMID 1
255 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
256
257 struct drm_amdgpu_vm_in {
258 /** AMDGPU_VM_OP_* */
259 __u32 op;
260 __u32 flags;
261 };
262
263 struct drm_amdgpu_vm_out {
264 /** For future use, no flags defined so far */
265 __u64 flags;
266 };
267
268 union drm_amdgpu_vm {
269 struct drm_amdgpu_vm_in in;
270 struct drm_amdgpu_vm_out out;
271 };
272
273 /* sched ioctl */
274 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
275
276 struct drm_amdgpu_sched_in {
277 /* AMDGPU_SCHED_OP_* */
278 __u32 op;
279 __u32 fd;
280 __s32 priority;
281 __u32 flags;
282 };
283
284 union drm_amdgpu_sched {
285 struct drm_amdgpu_sched_in in;
286 };
287
288 /*
289 * This is not a reliable API and you should expect it to fail for any
290 * number of reasons and have fallback path that do not use userptr to
291 * perform any operation.
292 */
293 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
294 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
295 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
296 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
297
298 struct drm_amdgpu_gem_userptr {
299 __u64 addr;
300 __u64 size;
301 /* AMDGPU_GEM_USERPTR_* */
302 __u32 flags;
303 /* Resulting GEM handle */
304 __u32 handle;
305 };
306
307 /* SI-CI-VI: */
308 /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
309 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
310 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
311 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
312 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
313 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
314 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
315 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
316 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
317 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
318 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
319 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
320 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
321 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
322 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
323 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
324 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
325
326 /* GFX9 and later: */
327 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
328 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
329
330 /* Set/Get helpers for tiling flags. */
331 #define AMDGPU_TILING_SET(field, value) \
332 (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT)
333 #define AMDGPU_TILING_GET(value, field) \
334 (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK)
335
336 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
337 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
338
339 /** The same structure is shared for input/output */
340 struct drm_amdgpu_gem_metadata {
341 /** GEM Object handle */
342 __u32 handle;
343 /** Do we want get or set metadata */
344 __u32 op;
345 struct {
346 /** For future use, no flags defined so far */
347 __u64 flags;
348 /** family specific tiling info */
349 __u64 tiling_info;
350 __u32 data_size_bytes;
351 __u32 data[64];
352 } data;
353 };
354
355 struct drm_amdgpu_gem_mmap_in {
356 /** the GEM object handle */
357 __u32 handle;
358 __u32 _pad;
359 };
360
361 struct drm_amdgpu_gem_mmap_out {
362 /** mmap offset from the vma offset manager */
363 __u64 addr_ptr;
364 };
365
366 union drm_amdgpu_gem_mmap {
367 struct drm_amdgpu_gem_mmap_in in;
368 struct drm_amdgpu_gem_mmap_out out;
369 };
370
371 struct drm_amdgpu_gem_wait_idle_in {
372 /** GEM object handle */
373 __u32 handle;
374 /** For future use, no flags defined so far */
375 __u32 flags;
376 /** Absolute timeout to wait */
377 __u64 timeout;
378 };
379
380 struct drm_amdgpu_gem_wait_idle_out {
381 /** BO status: 0 - BO is idle, 1 - BO is busy */
382 __u32 status;
383 /** Returned current memory domain */
384 __u32 domain;
385 };
386
387 union drm_amdgpu_gem_wait_idle {
388 struct drm_amdgpu_gem_wait_idle_in in;
389 struct drm_amdgpu_gem_wait_idle_out out;
390 };
391
392 struct drm_amdgpu_wait_cs_in {
393 /* Command submission handle
394 * handle equals 0 means none to wait for
395 * handle equals ~0ull means wait for the latest sequence number
396 */
397 __u64 handle;
398 /** Absolute timeout to wait */
399 __u64 timeout;
400 __u32 ip_type;
401 __u32 ip_instance;
402 __u32 ring;
403 __u32 ctx_id;
404 };
405
406 struct drm_amdgpu_wait_cs_out {
407 /** CS status: 0 - CS completed, 1 - CS still busy */
408 __u64 status;
409 };
410
411 union drm_amdgpu_wait_cs {
412 struct drm_amdgpu_wait_cs_in in;
413 struct drm_amdgpu_wait_cs_out out;
414 };
415
416 struct drm_amdgpu_fence {
417 __u32 ctx_id;
418 __u32 ip_type;
419 __u32 ip_instance;
420 __u32 ring;
421 __u64 seq_no;
422 };
423
424 struct drm_amdgpu_wait_fences_in {
425 /** This points to uint64_t * which points to fences */
426 __u64 fences;
427 __u32 fence_count;
428 __u32 wait_all;
429 __u64 timeout_ns;
430 };
431
432 struct drm_amdgpu_wait_fences_out {
433 __u32 status;
434 __u32 first_signaled;
435 };
436
437 union drm_amdgpu_wait_fences {
438 struct drm_amdgpu_wait_fences_in in;
439 struct drm_amdgpu_wait_fences_out out;
440 };
441
442 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
443 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
444
445 /* Sets or returns a value associated with a buffer. */
446 struct drm_amdgpu_gem_op {
447 /** GEM object handle */
448 __u32 handle;
449 /** AMDGPU_GEM_OP_* */
450 __u32 op;
451 /** Input or return value */
452 __u64 value;
453 };
454
455 #define AMDGPU_VA_OP_MAP 1
456 #define AMDGPU_VA_OP_UNMAP 2
457 #define AMDGPU_VA_OP_CLEAR 3
458 #define AMDGPU_VA_OP_REPLACE 4
459
460 /* Delay the page table update till the next CS */
461 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
462
463 /* Mapping flags */
464 /* readable mapping */
465 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
466 /* writable mapping */
467 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
468 /* executable mapping, new for VI */
469 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
470 /* partially resident texture */
471 #define AMDGPU_VM_PAGE_PRT (1 << 4)
472 /* MTYPE flags use bit 5 to 8 */
473 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
474 /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
475 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
476 /* Use NC MTYPE instead of default MTYPE */
477 #define AMDGPU_VM_MTYPE_NC (1 << 5)
478 /* Use WC MTYPE instead of default MTYPE */
479 #define AMDGPU_VM_MTYPE_WC (2 << 5)
480 /* Use CC MTYPE instead of default MTYPE */
481 #define AMDGPU_VM_MTYPE_CC (3 << 5)
482 /* Use UC MTYPE instead of default MTYPE */
483 #define AMDGPU_VM_MTYPE_UC (4 << 5)
484
485 struct drm_amdgpu_gem_va {
486 /** GEM object handle */
487 __u32 handle;
488 __u32 _pad;
489 /** AMDGPU_VA_OP_* */
490 __u32 operation;
491 /** AMDGPU_VM_PAGE_* */
492 __u32 flags;
493 /** va address to assign . Must be correctly aligned.*/
494 __u64 va_address;
495 /** Specify offset inside of BO to assign. Must be correctly aligned.*/
496 __u64 offset_in_bo;
497 /** Specify mapping size. Must be correctly aligned. */
498 __u64 map_size;
499 };
500
501 #define AMDGPU_HW_IP_GFX 0
502 #define AMDGPU_HW_IP_COMPUTE 1
503 #define AMDGPU_HW_IP_DMA 2
504 #define AMDGPU_HW_IP_UVD 3
505 #define AMDGPU_HW_IP_VCE 4
506 #define AMDGPU_HW_IP_UVD_ENC 5
507 #define AMDGPU_HW_IP_VCN_DEC 6
508 #define AMDGPU_HW_IP_VCN_ENC 7
509 #define AMDGPU_HW_IP_VCN_JPEG 8
510 #define AMDGPU_HW_IP_NUM 9
511
512 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
513
514 #define AMDGPU_CHUNK_ID_IB 0x01
515 #define AMDGPU_CHUNK_ID_FENCE 0x02
516 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
517 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
518 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
519 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
520
521 struct drm_amdgpu_cs_chunk {
522 __u32 chunk_id;
523 __u32 length_dw;
524 __u64 chunk_data;
525 };
526
527 struct drm_amdgpu_cs_in {
528 /** Rendering context id */
529 __u32 ctx_id;
530 /** Handle of resource list associated with CS */
531 __u32 bo_list_handle;
532 __u32 num_chunks;
533 __u32 _pad;
534 /** this points to __u64 * which point to cs chunks */
535 __u64 chunks;
536 };
537
538 struct drm_amdgpu_cs_out {
539 __u64 handle;
540 };
541
542 union drm_amdgpu_cs {
543 struct drm_amdgpu_cs_in in;
544 struct drm_amdgpu_cs_out out;
545 };
546
547 /* Specify flags to be used for IB */
548
549 /* This IB should be submitted to CE */
550 #define AMDGPU_IB_FLAG_CE (1<<0)
551
552 /* Preamble flag, which means the IB could be dropped if no context switch */
553 #define AMDGPU_IB_FLAG_PREAMBLE (1<<1)
554
555 /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */
556 #define AMDGPU_IB_FLAG_PREEMPT (1<<2)
557
558 /* The IB fence should do the L2 writeback but not invalidate any shader
559 * caches (L2/vL1/sL1/I$). */
560 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
561
562 struct drm_amdgpu_cs_chunk_ib {
563 __u32 _pad;
564 /** AMDGPU_IB_FLAG_* */
565 __u32 flags;
566 /** Virtual address to begin IB execution */
567 __u64 va_start;
568 /** Size of submission */
569 __u32 ib_bytes;
570 /** HW IP to submit to */
571 __u32 ip_type;
572 /** HW IP index of the same type to submit to */
573 __u32 ip_instance;
574 /** Ring index to submit to */
575 __u32 ring;
576 };
577
578 struct drm_amdgpu_cs_chunk_dep {
579 __u32 ip_type;
580 __u32 ip_instance;
581 __u32 ring;
582 __u32 ctx_id;
583 __u64 handle;
584 };
585
586 struct drm_amdgpu_cs_chunk_fence {
587 __u32 handle;
588 __u32 offset;
589 };
590
591 struct drm_amdgpu_cs_chunk_sem {
592 __u32 handle;
593 };
594
595 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
596 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
597 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
598
599 union drm_amdgpu_fence_to_handle {
600 struct {
601 struct drm_amdgpu_fence fence;
602 __u32 what;
603 __u32 pad;
604 } in;
605 struct {
606 __u32 handle;
607 } out;
608 };
609
610 struct drm_amdgpu_cs_chunk_data {
611 union {
612 struct drm_amdgpu_cs_chunk_ib ib_data;
613 struct drm_amdgpu_cs_chunk_fence fence_data;
614 };
615 };
616
617 /**
618 * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
619 *
620 */
621 #define AMDGPU_IDS_FLAGS_FUSION 0x1
622 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
623
624 /* indicate if acceleration can be working */
625 #define AMDGPU_INFO_ACCEL_WORKING 0x00
626 /* get the crtc_id from the mode object id? */
627 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
628 /* query hw IP info */
629 #define AMDGPU_INFO_HW_IP_INFO 0x02
630 /* query hw IP instance count for the specified type */
631 #define AMDGPU_INFO_HW_IP_COUNT 0x03
632 /* timestamp for GL_ARB_timer_query */
633 #define AMDGPU_INFO_TIMESTAMP 0x05
634 /* Query the firmware version */
635 #define AMDGPU_INFO_FW_VERSION 0x0e
636 /* Subquery id: Query VCE firmware version */
637 #define AMDGPU_INFO_FW_VCE 0x1
638 /* Subquery id: Query UVD firmware version */
639 #define AMDGPU_INFO_FW_UVD 0x2
640 /* Subquery id: Query GMC firmware version */
641 #define AMDGPU_INFO_FW_GMC 0x03
642 /* Subquery id: Query GFX ME firmware version */
643 #define AMDGPU_INFO_FW_GFX_ME 0x04
644 /* Subquery id: Query GFX PFP firmware version */
645 #define AMDGPU_INFO_FW_GFX_PFP 0x05
646 /* Subquery id: Query GFX CE firmware version */
647 #define AMDGPU_INFO_FW_GFX_CE 0x06
648 /* Subquery id: Query GFX RLC firmware version */
649 #define AMDGPU_INFO_FW_GFX_RLC 0x07
650 /* Subquery id: Query GFX MEC firmware version */
651 #define AMDGPU_INFO_FW_GFX_MEC 0x08
652 /* Subquery id: Query SMC firmware version */
653 #define AMDGPU_INFO_FW_SMC 0x0a
654 /* Subquery id: Query SDMA firmware version */
655 #define AMDGPU_INFO_FW_SDMA 0x0b
656 /* Subquery id: Query PSP SOS firmware version */
657 #define AMDGPU_INFO_FW_SOS 0x0c
658 /* Subquery id: Query PSP ASD firmware version */
659 #define AMDGPU_INFO_FW_ASD 0x0d
660 /* Subquery id: Query VCN firmware version */
661 #define AMDGPU_INFO_FW_VCN 0x0e
662 /* Subquery id: Query GFX RLC SRLC firmware version */
663 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
664 /* Subquery id: Query GFX RLC SRLG firmware version */
665 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
666 /* Subquery id: Query GFX RLC SRLS firmware version */
667 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
668 /* number of bytes moved for TTM migration */
669 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
670 /* the used VRAM size */
671 #define AMDGPU_INFO_VRAM_USAGE 0x10
672 /* the used GTT size */
673 #define AMDGPU_INFO_GTT_USAGE 0x11
674 /* Information about GDS, etc. resource configuration */
675 #define AMDGPU_INFO_GDS_CONFIG 0x13
676 /* Query information about VRAM and GTT domains */
677 #define AMDGPU_INFO_VRAM_GTT 0x14
678 /* Query information about register in MMR address space*/
679 #define AMDGPU_INFO_READ_MMR_REG 0x15
680 /* Query information about device: rev id, family, etc. */
681 #define AMDGPU_INFO_DEV_INFO 0x16
682 /* visible vram usage */
683 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
684 /* number of TTM buffer evictions */
685 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
686 /* Query memory about VRAM and GTT domains */
687 #define AMDGPU_INFO_MEMORY 0x19
688 /* Query vce clock table */
689 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
690 /* Query vbios related information */
691 #define AMDGPU_INFO_VBIOS 0x1B
692 /* Subquery id: Query vbios size */
693 #define AMDGPU_INFO_VBIOS_SIZE 0x1
694 /* Subquery id: Query vbios image */
695 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
696 /* Query UVD handles */
697 #define AMDGPU_INFO_NUM_HANDLES 0x1C
698 /* Query sensor related information */
699 #define AMDGPU_INFO_SENSOR 0x1D
700 /* Subquery id: Query GPU shader clock */
701 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
702 /* Subquery id: Query GPU memory clock */
703 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
704 /* Subquery id: Query GPU temperature */
705 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
706 /* Subquery id: Query GPU load */
707 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
708 /* Subquery id: Query average GPU power */
709 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
710 /* Subquery id: Query northbridge voltage */
711 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
712 /* Subquery id: Query graphics voltage */
713 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
714 /* Subquery id: Query GPU stable pstate shader clock */
715 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
716 /* Subquery id: Query GPU stable pstate memory clock */
717 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
718 /* Number of VRAM page faults on CPU access. */
719 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
720 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
721
722 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
723 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
724 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
725 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
726
727 struct drm_amdgpu_query_fw {
728 /** AMDGPU_INFO_FW_* */
729 __u32 fw_type;
730 /**
731 * Index of the IP if there are more IPs of
732 * the same type.
733 */
734 __u32 ip_instance;
735 /**
736 * Index of the engine. Whether this is used depends
737 * on the firmware type. (e.g. MEC, SDMA)
738 */
739 __u32 index;
740 __u32 _pad;
741 };
742
743 /* Input structure for the INFO ioctl */
744 struct drm_amdgpu_info {
745 /* Where the return value will be stored */
746 __u64 return_pointer;
747 /* The size of the return value. Just like "size" in "snprintf",
748 * it limits how many bytes the kernel can write. */
749 __u32 return_size;
750 /* The query request id. */
751 __u32 query;
752
753 union {
754 struct {
755 __u32 id;
756 __u32 _pad;
757 } mode_crtc;
758
759 struct {
760 /** AMDGPU_HW_IP_* */
761 __u32 type;
762 /**
763 * Index of the IP if there are more IPs of the same
764 * type. Ignored by AMDGPU_INFO_HW_IP_COUNT.
765 */
766 __u32 ip_instance;
767 } query_hw_ip;
768
769 struct {
770 __u32 dword_offset;
771 /** number of registers to read */
772 __u32 count;
773 __u32 instance;
774 /** For future use, no flags defined so far */
775 __u32 flags;
776 } read_mmr_reg;
777
778 struct drm_amdgpu_query_fw query_fw;
779
780 struct {
781 __u32 type;
782 __u32 offset;
783 } vbios_info;
784
785 struct {
786 __u32 type;
787 } sensor_info;
788 };
789 };
790
791 struct drm_amdgpu_info_gds {
792 /** GDS GFX partition size */
793 __u32 gds_gfx_partition_size;
794 /** GDS compute partition size */
795 __u32 compute_partition_size;
796 /** total GDS memory size */
797 __u32 gds_total_size;
798 /** GWS size per GFX partition */
799 __u32 gws_per_gfx_partition;
800 /** GSW size per compute partition */
801 __u32 gws_per_compute_partition;
802 /** OA size per GFX partition */
803 __u32 oa_per_gfx_partition;
804 /** OA size per compute partition */
805 __u32 oa_per_compute_partition;
806 __u32 _pad;
807 };
808
809 struct drm_amdgpu_info_vram_gtt {
810 __u64 vram_size;
811 __u64 vram_cpu_accessible_size;
812 __u64 gtt_size;
813 };
814
815 struct drm_amdgpu_heap_info {
816 /** max. physical memory */
817 __u64 total_heap_size;
818
819 /** Theoretical max. available memory in the given heap */
820 __u64 usable_heap_size;
821
822 /**
823 * Number of bytes allocated in the heap. This includes all processes
824 * and private allocations in the kernel. It changes when new buffers
825 * are allocated, freed, and moved. It cannot be larger than
826 * heap_size.
827 */
828 __u64 heap_usage;
829
830 /**
831 * Theoretical possible max. size of buffer which
832 * could be allocated in the given heap
833 */
834 __u64 max_allocation;
835 };
836
837 struct drm_amdgpu_memory_info {
838 struct drm_amdgpu_heap_info vram;
839 struct drm_amdgpu_heap_info cpu_accessible_vram;
840 struct drm_amdgpu_heap_info gtt;
841 };
842
843 struct drm_amdgpu_info_firmware {
844 __u32 ver;
845 __u32 feature;
846 };
847
848 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
849 #define AMDGPU_VRAM_TYPE_GDDR1 1
850 #define AMDGPU_VRAM_TYPE_DDR2 2
851 #define AMDGPU_VRAM_TYPE_GDDR3 3
852 #define AMDGPU_VRAM_TYPE_GDDR4 4
853 #define AMDGPU_VRAM_TYPE_GDDR5 5
854 #define AMDGPU_VRAM_TYPE_HBM 6
855 #define AMDGPU_VRAM_TYPE_DDR3 7
856 #define AMDGPU_VRAM_TYPE_DDR4 8
857
858 struct drm_amdgpu_info_device {
859 /** PCI Device ID */
860 __u32 device_id;
861 /** Internal chip revision: A0, A1, etc.) */
862 __u32 chip_rev;
863 __u32 external_rev;
864 /** Revision id in PCI Config space */
865 __u32 pci_rev;
866 __u32 family;
867 __u32 num_shader_engines;
868 __u32 num_shader_arrays_per_engine;
869 /* in KHz */
870 __u32 gpu_counter_freq;
871 __u64 max_engine_clock;
872 __u64 max_memory_clock;
873 /* cu information */
874 __u32 cu_active_number;
875 /* NOTE: cu_ao_mask is INVALID, DON'T use it */
876 __u32 cu_ao_mask;
877 __u32 cu_bitmap[4][4];
878 /** Render backend pipe mask. One render backend is CB+DB. */
879 __u32 enabled_rb_pipes_mask;
880 __u32 num_rb_pipes;
881 __u32 num_hw_gfx_contexts;
882 __u32 _pad;
883 __u64 ids_flags;
884 /** Starting virtual address for UMDs. */
885 __u64 virtual_address_offset;
886 /** The maximum virtual address */
887 __u64 virtual_address_max;
888 /** Required alignment of virtual addresses. */
889 __u32 virtual_address_alignment;
890 /** Page table entry - fragment size */
891 __u32 pte_fragment_size;
892 __u32 gart_page_size;
893 /** constant engine ram size*/
894 __u32 ce_ram_size;
895 /** video memory type info*/
896 __u32 vram_type;
897 /** video memory bit width*/
898 __u32 vram_bit_width;
899 /* vce harvesting instance */
900 __u32 vce_harvest_config;
901 /* gfx double offchip LDS buffers */
902 __u32 gc_double_offchip_lds_buf;
903 /* NGG Primitive Buffer */
904 __u64 prim_buf_gpu_addr;
905 /* NGG Position Buffer */
906 __u64 pos_buf_gpu_addr;
907 /* NGG Control Sideband */
908 __u64 cntl_sb_buf_gpu_addr;
909 /* NGG Parameter Cache */
910 __u64 param_buf_gpu_addr;
911 __u32 prim_buf_size;
912 __u32 pos_buf_size;
913 __u32 cntl_sb_buf_size;
914 __u32 param_buf_size;
915 /* wavefront size*/
916 __u32 wave_front_size;
917 /* shader visible vgprs*/
918 __u32 num_shader_visible_vgprs;
919 /* CU per shader array*/
920 __u32 num_cu_per_sh;
921 /* number of tcc blocks*/
922 __u32 num_tcc_blocks;
923 /* gs vgt table depth*/
924 __u32 gs_vgt_table_depth;
925 /* gs primitive buffer depth*/
926 __u32 gs_prim_buffer_depth;
927 /* max gs wavefront per vgt*/
928 __u32 max_gs_waves_per_vgt;
929 __u32 _pad1;
930 /* always on cu bitmap */
931 __u32 cu_ao_bitmap[4][4];
932 /** Starting high virtual address for UMDs. */
933 __u64 high_va_offset;
934 /** The maximum high virtual address */
935 __u64 high_va_max;
936 };
937
938 struct drm_amdgpu_info_hw_ip {
939 /** Version of h/w IP */
940 __u32 hw_ip_version_major;
941 __u32 hw_ip_version_minor;
942 /** Capabilities */
943 __u64 capabilities_flags;
944 /** command buffer address start alignment*/
945 __u32 ib_start_alignment;
946 /** command buffer size alignment*/
947 __u32 ib_size_alignment;
948 /** Bitmask of available rings. Bit 0 means ring 0, etc. */
949 __u32 available_rings;
950 __u32 _pad;
951 };
952
953 struct drm_amdgpu_info_num_handles {
954 /** Max handles as supported by firmware for UVD */
955 __u32 uvd_max_handles;
956 /** Handles currently in use for UVD */
957 __u32 uvd_used_handles;
958 };
959
960 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
961
962 struct drm_amdgpu_info_vce_clock_table_entry {
963 /** System clock */
964 __u32 sclk;
965 /** Memory clock */
966 __u32 mclk;
967 /** VCE clock */
968 __u32 eclk;
969 __u32 pad;
970 };
971
972 struct drm_amdgpu_info_vce_clock_table {
973 struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
974 __u32 num_valid_entries;
975 __u32 pad;
976 };
977
978 /*
979 * Supported GPU families
980 */
981 #define AMDGPU_FAMILY_UNKNOWN 0
982 #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */
983 #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */
984 #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */
985 #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */
986 #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */
987 #define AMDGPU_FAMILY_AI 141 /* Vega10 */
988 #define AMDGPU_FAMILY_RV 142 /* Raven */
989
990 #if defined(__cplusplus)
991 }
992 #endif
993
994 #endif
Linux with added FPC-III support