drivers/net/ethernet/broadcom/genet/bcmmii.c

   1 /*
   2  * Broadcom GENET MDIO routines
   3  *
   4  * Copyright (c) 2014-2017 Broadcom
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11
  12 #include <linux/types.h>
  13 #include <linux/delay.h>
  14 #include <linux/wait.h>
  15 #include <linux/mii.h>
  16 #include <linux/ethtool.h>
  17 #include <linux/bitops.h>
  18 #include <linux/netdevice.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/phy.h>
  21 #include <linux/phy_fixed.h>
  22 #include <linux/brcmphy.h>
  23 #include <linux/of.h>
  24 #include <linux/of_net.h>
  25 #include <linux/of_mdio.h>
  26 #include <linux/platform_data/bcmgenet.h>
  27 #include <linux/platform_data/mdio-bcm-unimac.h>
  28
  29 #include "bcmgenet.h"
  30
  31 /* setup netdev link state when PHY link status change and
  32  * update UMAC and RGMII block when link up
  33  */
  34 void bcmgenet_mii_setup(struct net_device *dev)
  35 {
  36         struct bcmgenet_priv *priv = netdev_priv(dev);
  37         struct phy_device *phydev = dev->phydev;
  38         u32 reg, cmd_bits = 0;
  39         bool status_changed = false;
  40
  41         if (priv->old_link != phydev->link) {
  42                 status_changed = true;
  43                 priv->old_link = phydev->link;
  44         }
  45
  46         if (phydev->link) {
  47                 /* check speed/duplex/pause changes */
  48                 if (priv->old_speed != phydev->speed) {
  49                         status_changed = true;
  50                         priv->old_speed = phydev->speed;
  51                 }
  52
  53                 if (priv->old_duplex != phydev->duplex) {
  54                         status_changed = true;
  55                         priv->old_duplex = phydev->duplex;
  56                 }
  57
  58                 if (priv->old_pause != phydev->pause) {
  59                         status_changed = true;
  60                         priv->old_pause = phydev->pause;
  61                 }
  62
  63                 /* done if nothing has changed */
  64                 if (!status_changed)
  65                         return;
  66
  67                 /* speed */
  68                 if (phydev->speed == SPEED_1000)
  69                         cmd_bits = UMAC_SPEED_1000;
  70                 else if (phydev->speed == SPEED_100)
  71                         cmd_bits = UMAC_SPEED_100;
  72                 else
  73                         cmd_bits = UMAC_SPEED_10;
  74                 cmd_bits <<= CMD_SPEED_SHIFT;
  75
  76                 /* duplex */
  77                 if (phydev->duplex != DUPLEX_FULL)
  78                         cmd_bits |= CMD_HD_EN;
  79
  80                 /* pause capability */
  81                 if (!phydev->pause)
  82                         cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
  83
  84                 /*
  85                  * Program UMAC and RGMII block based on established
  86                  * link speed, duplex, and pause. The speed set in
  87                  * umac->cmd tell RGMII block which clock to use for
  88                  * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
  89                  * Receive clock is provided by the PHY.
  90                  */
  91                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
  92                 reg &= ~OOB_DISABLE;
  93                 reg |= RGMII_LINK;
  94                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
  95
  96                 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
  97                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
  98                                CMD_HD_EN |
  99                                CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE);
 100                 reg |= cmd_bits;
 101                 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
 102         } else {
 103                 /* done if nothing has changed */
 104                 if (!status_changed)
 105                         return;
 106
 107                 /* needed for MoCA fixed PHY to reflect correct link status */
 108                 netif_carrier_off(dev);
 109         }
 110
 111         phy_print_status(phydev);
 112 }
 113
 114
 115 static int bcmgenet_fixed_phy_link_update(struct net_device *dev,
 116                                           struct fixed_phy_status *status)
 117 {
 118         if (dev && dev->phydev && status)
 119                 status->link = dev->phydev->link;
 120
 121         return 0;
 122 }
 123
 124 void bcmgenet_phy_power_set(struct net_device *dev, bool enable)
 125 {
 126         struct bcmgenet_priv *priv = netdev_priv(dev);
 127         u32 reg = 0;
 128
 129         /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
 130         if (GENET_IS_V4(priv)) {
 131                 reg = bcmgenet_ext_readl(priv, EXT_GPHY_CTRL);
 132                 if (enable) {
 133                         reg &= ~EXT_CK25_DIS;
 134                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 135                         mdelay(1);
 136
 137                         reg &= ~(EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN);
 138                         reg |= EXT_GPHY_RESET;
 139                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 140                         mdelay(1);
 141
 142                         reg &= ~EXT_GPHY_RESET;
 143                 } else {
 144                         reg |= EXT_CFG_IDDQ_BIAS | EXT_CFG_PWR_DOWN |
 145                                EXT_GPHY_RESET;
 146                         bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 147                         mdelay(1);
 148                         reg |= EXT_CK25_DIS;
 149                 }
 150                 bcmgenet_ext_writel(priv, reg, EXT_GPHY_CTRL);
 151                 udelay(60);
 152         } else {
 153                 mdelay(1);
 154         }
 155 }
 156
 157 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv *priv)
 158 {
 159         u32 reg;
 160
 161         if (!GENET_IS_V5(priv)) {
 162                 /* Speed settings are set in bcmgenet_mii_setup() */
 163                 reg = bcmgenet_sys_readl(priv, SYS_PORT_CTRL);
 164                 reg |= LED_ACT_SOURCE_MAC;
 165                 bcmgenet_sys_writel(priv, reg, SYS_PORT_CTRL);
 166         }
 167
 168         if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
 169                 fixed_phy_set_link_update(priv->dev->phydev,
 170                                           bcmgenet_fixed_phy_link_update);
 171 }
 172
 173 int bcmgenet_mii_config(struct net_device *dev, bool init)
 174 {
 175         struct bcmgenet_priv *priv = netdev_priv(dev);
 176         struct phy_device *phydev = dev->phydev;
 177         struct device *kdev = &priv->pdev->dev;
 178         const char *phy_name = NULL;
 179         u32 id_mode_dis = 0;
 180         u32 port_ctrl;
 181         u32 reg;
 182
 183         priv->ext_phy = !priv->internal_phy &&
 184                         (priv->phy_interface != PHY_INTERFACE_MODE_MOCA);
 185
 186         switch (priv->phy_interface) {
 187         case PHY_INTERFACE_MODE_INTERNAL:
 188         case PHY_INTERFACE_MODE_MOCA:
 189                 /* Irrespective of the actually configured PHY speed (100 or
 190                  * 1000) GENETv4 only has an internal GPHY so we will just end
 191                  * up masking the Gigabit features from what we support, not
 192                  * switching to the EPHY
 193                  */
 194                 if (GENET_IS_V4(priv))
 195                         port_ctrl = PORT_MODE_INT_GPHY;
 196                 else
 197                         port_ctrl = PORT_MODE_INT_EPHY;
 198
 199                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 200
 201                 if (priv->internal_phy) {
 202                         phy_name = "internal PHY";
 203                 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
 204                         phy_name = "MoCA";
 205                         bcmgenet_moca_phy_setup(priv);
 206                 }
 207                 break;
 208
 209         case PHY_INTERFACE_MODE_MII:
 210                 phy_name = "external MII";
 211                 phydev->supported &= PHY_BASIC_FEATURES;
 212                 bcmgenet_sys_writel(priv,
 213                                     PORT_MODE_EXT_EPHY, SYS_PORT_CTRL);
 214                 break;
 215
 216         case PHY_INTERFACE_MODE_REVMII:
 217                 phy_name = "external RvMII";
 218                 /* of_mdiobus_register took care of reading the 'max-speed'
 219                  * PHY property for us, effectively limiting the PHY supported
 220                  * capabilities, use that knowledge to also configure the
 221                  * Reverse MII interface correctly.
 222                  */
 223                 if ((dev->phydev->supported & PHY_BASIC_FEATURES) ==
 224                                 PHY_BASIC_FEATURES)
 225                         port_ctrl = PORT_MODE_EXT_RVMII_25;
 226                 else
 227                         port_ctrl = PORT_MODE_EXT_RVMII_50;
 228                 bcmgenet_sys_writel(priv, port_ctrl, SYS_PORT_CTRL);
 229                 break;
 230
 231         case PHY_INTERFACE_MODE_RGMII:
 232                 /* RGMII_NO_ID: TXC transitions at the same time as TXD
 233                  *              (requires PCB or receiver-side delay)
 234                  * RGMII:       Add 2ns delay on TXC (90 degree shift)
 235                  *
 236                  * ID is implicitly disabled for 100Mbps (RG)MII operation.
 237                  */
 238                 id_mode_dis = BIT(16);
 239                 /* fall through */
 240         case PHY_INTERFACE_MODE_RGMII_TXID:
 241                 if (id_mode_dis)
 242                         phy_name = "external RGMII (no delay)";
 243                 else
 244                         phy_name = "external RGMII (TX delay)";
 245                 bcmgenet_sys_writel(priv,
 246                                     PORT_MODE_EXT_GPHY, SYS_PORT_CTRL);
 247                 break;
 248         default:
 249                 dev_err(kdev, "unknown phy mode: %d\n", priv->phy_interface);
 250                 return -EINVAL;
 251         }
 252
 253         /* This is an external PHY (xMII), so we need to enable the RGMII
 254          * block for the interface to work
 255          */
 256         if (priv->ext_phy) {
 257                 reg = bcmgenet_ext_readl(priv, EXT_RGMII_OOB_CTRL);
 258                 reg |= RGMII_MODE_EN | id_mode_dis;
 259                 bcmgenet_ext_writel(priv, reg, EXT_RGMII_OOB_CTRL);
 260         }
 261
 262         if (init)
 263                 dev_info(kdev, "configuring instance for %s\n", phy_name);
 264
 265         return 0;
 266 }
 267
 268 int bcmgenet_mii_probe(struct net_device *dev)
 269 {
 270         struct bcmgenet_priv *priv = netdev_priv(dev);
 271         struct device_node *dn = priv->pdev->dev.of_node;
 272         struct phy_device *phydev;
 273         u32 phy_flags;
 274         int ret;
 275
 276         /* Communicate the integrated PHY revision */
 277         phy_flags = priv->gphy_rev;
 278
 279         /* Initialize link state variables that bcmgenet_mii_setup() uses */
 280         priv->old_link = -1;
 281         priv->old_speed = -1;
 282         priv->old_duplex = -1;
 283         priv->old_pause = -1;
 284
 285         if (dn) {
 286                 phydev = of_phy_connect(dev, priv->phy_dn, bcmgenet_mii_setup,
 287                                         phy_flags, priv->phy_interface);
 288                 if (!phydev) {
 289                         pr_err("could not attach to PHY\n");
 290                         return -ENODEV;
 291                 }
 292         } else {
 293                 phydev = dev->phydev;
 294                 phydev->dev_flags = phy_flags;
 295
 296                 ret = phy_connect_direct(dev, phydev, bcmgenet_mii_setup,
 297                                          priv->phy_interface);
 298                 if (ret) {
 299                         pr_err("could not attach to PHY\n");
 300                         return -ENODEV;
 301                 }
 302         }
 303
 304         /* Configure port multiplexer based on what the probed PHY device since
 305          * reading the 'max-speed' property determines the maximum supported
 306          * PHY speed which is needed for bcmgenet_mii_config() to configure
 307          * things appropriately.
 308          */
 309         ret = bcmgenet_mii_config(dev, true);
 310         if (ret) {
 311                 phy_disconnect(dev->phydev);
 312                 return ret;
 313         }
 314
 315         phydev->advertising = phydev->supported;
 316
 317         /* The internal PHY has its link interrupts routed to the
 318          * Ethernet MAC ISRs
 319          */
 320         if (priv->internal_phy)
 321                 dev->phydev->irq = PHY_IGNORE_INTERRUPT;
 322
 323         return 0;
 324 }
 325
 326 static struct device_node *bcmgenet_mii_of_find_mdio(struct bcmgenet_priv *priv)
 327 {
 328         struct device_node *dn = priv->pdev->dev.of_node;
 329         struct device *kdev = &priv->pdev->dev;
 330         char *compat;
 331
 332         compat = kasprintf(GFP_KERNEL, "brcm,genet-mdio-v%d", priv->version);
 333         if (!compat)
 334                 return NULL;
 335
 336         priv->mdio_dn = of_find_compatible_node(dn, NULL, compat);
 337         kfree(compat);
 338         if (!priv->mdio_dn) {
 339                 dev_err(kdev, "unable to find MDIO bus node\n");
 340                 return NULL;
 341         }
 342
 343         return priv->mdio_dn;
 344 }
 345
 346 static void bcmgenet_mii_pdata_init(struct bcmgenet_priv *priv,
 347                                     struct unimac_mdio_pdata *ppd)
 348 {
 349         struct device *kdev = &priv->pdev->dev;
 350         struct bcmgenet_platform_data *pd = kdev->platform_data;
 351
 352         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 353                 /*
 354                  * Internal or external PHY with MDIO access
 355                  */
 356                 if (pd->phy_address >= 0 && pd->phy_address < PHY_MAX_ADDR)
 357                         ppd->phy_mask = 1 << pd->phy_address;
 358                 else
 359                         ppd->phy_mask = 0;
 360         }
 361 }
 362
 363 static int bcmgenet_mii_wait(void *wait_func_data)
 364 {
 365         struct bcmgenet_priv *priv = wait_func_data;
 366
 367         wait_event_timeout(priv->wq,
 368                            !(bcmgenet_umac_readl(priv, UMAC_MDIO_CMD)
 369                            & MDIO_START_BUSY),
 370                            HZ / 100);
 371         return 0;
 372 }
 373
 374 static int bcmgenet_mii_register(struct bcmgenet_priv *priv)
 375 {
 376         struct platform_device *pdev = priv->pdev;
 377         struct bcmgenet_platform_data *pdata = pdev->dev.platform_data;
 378         struct device_node *dn = pdev->dev.of_node;
 379         struct unimac_mdio_pdata ppd;
 380         struct platform_device *ppdev;
 381         struct resource *pres, res;
 382         int id, ret;
 383
 384         pres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 385         memset(&res, 0, sizeof(res));
 386         memset(&ppd, 0, sizeof(ppd));
 387
 388         ppd.wait_func = bcmgenet_mii_wait;
 389         ppd.wait_func_data = priv;
 390         ppd.bus_name = "bcmgenet MII bus";
 391
 392         /* Unimac MDIO bus controller starts at UniMAC offset + MDIO_CMD
 393          * and is 2 * 32-bits word long, 8 bytes total.
 394          */
 395         res.start = pres->start + GENET_UMAC_OFF + UMAC_MDIO_CMD;
 396         res.end = res.start + 8;
 397         res.flags = IORESOURCE_MEM;
 398
 399         if (dn)
 400                 id = of_alias_get_id(dn, "eth");
 401         else
 402                 id = pdev->id;
 403
 404         ppdev = platform_device_alloc(UNIMAC_MDIO_DRV_NAME, id);
 405         if (!ppdev)
 406                 return -ENOMEM;
 407
 408         /* Retain this platform_device pointer for later cleanup */
 409         priv->mii_pdev = ppdev;
 410         ppdev->dev.parent = &pdev->dev;
 411         ppdev->dev.of_node = bcmgenet_mii_of_find_mdio(priv);
 412         if (pdata)
 413                 bcmgenet_mii_pdata_init(priv, &ppd);
 414
 415         ret = platform_device_add_resources(ppdev, &res, 1);
 416         if (ret)
 417                 goto out;
 418
 419         ret = platform_device_add_data(ppdev, &ppd, sizeof(ppd));
 420         if (ret)
 421                 goto out;
 422
 423         ret = platform_device_add(ppdev);
 424         if (ret)
 425                 goto out;
 426
 427         return 0;
 428 out:
 429         platform_device_put(ppdev);
 430         return ret;
 431 }
 432
 433 static int bcmgenet_mii_of_init(struct bcmgenet_priv *priv)
 434 {
 435         struct device_node *dn = priv->pdev->dev.of_node;
 436         struct device *kdev = &priv->pdev->dev;
 437         struct phy_device *phydev;
 438         int phy_mode;
 439         int ret;
 440
 441         /* Fetch the PHY phandle */
 442         priv->phy_dn = of_parse_phandle(dn, "phy-handle", 0);
 443
 444         /* In the case of a fixed PHY, the DT node associated
 445          * to the PHY is the Ethernet MAC DT node.
 446          */
 447         if (!priv->phy_dn && of_phy_is_fixed_link(dn)) {
 448                 ret = of_phy_register_fixed_link(dn);
 449                 if (ret)
 450                         return ret;
 451
 452                 priv->phy_dn = of_node_get(dn);
 453         }
 454
 455         /* Get the link mode */
 456         phy_mode = of_get_phy_mode(dn);
 457         if (phy_mode < 0) {
 458                 dev_err(kdev, "invalid PHY mode property\n");
 459                 return phy_mode;
 460         }
 461
 462         priv->phy_interface = phy_mode;
 463
 464         /* We need to specifically look up whether this PHY interface is internal
 465          * or not *before* we even try to probe the PHY driver over MDIO as we
 466          * may have shut down the internal PHY for power saving purposes.
 467          */
 468         if (priv->phy_interface == PHY_INTERFACE_MODE_INTERNAL)
 469                 priv->internal_phy = true;
 470
 471         /* Make sure we initialize MoCA PHYs with a link down */
 472         if (phy_mode == PHY_INTERFACE_MODE_MOCA) {
 473                 phydev = of_phy_find_device(dn);
 474                 if (phydev) {
 475                         phydev->link = 0;
 476                         put_device(&phydev->mdio.dev);
 477                 }
 478         }
 479
 480         return 0;
 481 }
 482
 483 static int bcmgenet_mii_pd_init(struct bcmgenet_priv *priv)
 484 {
 485         struct device *kdev = &priv->pdev->dev;
 486         struct bcmgenet_platform_data *pd = kdev->platform_data;
 487         char phy_name[MII_BUS_ID_SIZE + 3];
 488         char mdio_bus_id[MII_BUS_ID_SIZE];
 489         struct phy_device *phydev;
 490
 491         snprintf(mdio_bus_id, MII_BUS_ID_SIZE, "%s-%d",
 492                  UNIMAC_MDIO_DRV_NAME, priv->pdev->id);
 493
 494         if (pd->phy_interface != PHY_INTERFACE_MODE_MOCA && pd->mdio_enabled) {
 495                 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT,
 496                          mdio_bus_id, pd->phy_address);
 497
 498                 /*
 499                  * Internal or external PHY with MDIO access
 500                  */
 501                 phydev = phy_attach(priv->dev, phy_name, pd->phy_interface);
 502                 if (!phydev) {
 503                         dev_err(kdev, "failed to register PHY device\n");
 504                         return -ENODEV;
 505                 }
 506         } else {
 507                 /*
 508                  * MoCA port or no MDIO access.
 509                  * Use fixed PHY to represent the link layer.
 510                  */
 511                 struct fixed_phy_status fphy_status = {
 512                         .link = 1,
 513                         .speed = pd->phy_speed,
 514                         .duplex = pd->phy_duplex,
 515                         .pause = 0,
 516                         .asym_pause = 0,
 517                 };
 518
 519                 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
 520                 if (!phydev || IS_ERR(phydev)) {
 521                         dev_err(kdev, "failed to register fixed PHY device\n");
 522                         return -ENODEV;
 523                 }
 524
 525                 /* Make sure we initialize MoCA PHYs with a link down */
 526                 phydev->link = 0;
 527
 528         }
 529
 530         priv->phy_interface = pd->phy_interface;
 531
 532         return 0;
 533 }
 534
 535 static int bcmgenet_mii_bus_init(struct bcmgenet_priv *priv)
 536 {
 537         struct device_node *dn = priv->pdev->dev.of_node;
 538
 539         if (dn)
 540                 return bcmgenet_mii_of_init(priv);
 541         else
 542                 return bcmgenet_mii_pd_init(priv);
 543 }
 544
 545 int bcmgenet_mii_init(struct net_device *dev)
 546 {
 547         struct bcmgenet_priv *priv = netdev_priv(dev);
 548         int ret;
 549
 550         ret = bcmgenet_mii_register(priv);
 551         if (ret)
 552                 return ret;
 553
 554         ret = bcmgenet_mii_bus_init(priv);
 555         if (ret)
 556                 goto out;
 557
 558         return 0;
 559
 560 out:
 561         bcmgenet_mii_exit(dev);
 562         return ret;
 563 }
 564
 565 void bcmgenet_mii_exit(struct net_device *dev)
 566 {
 567         struct bcmgenet_priv *priv = netdev_priv(dev);
 568         struct device_node *dn = priv->pdev->dev.of_node;
 569
 570         if (of_phy_is_fixed_link(dn))
 571                 of_phy_deregister_fixed_link(dn);
 572         of_node_put(priv->phy_dn);
 573         platform_device_unregister(priv->mii_pdev);
 574 }