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staging: rtl8188eu: Replace function name in string with __func__
[linux/fpc-iii.git] / drivers / net / ethernet / cavium / liquidio / cn23xx_pf_device.c
blobe8b290473ee25fe3c6f5b9683c86b87254d3767b
1 /**********************************************************************
2 * Author: Cavium, Inc.
3 *
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
6 *
7 * Copyright (c) 2003-2016 Cavium, Inc.
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more details.
17 ***********************************************************************/
18 #include <linux/pci.h>
19 #include <linux/vmalloc.h>
20 #include <linux/etherdevice.h>
21 #include "liquidio_common.h"
22 #include "octeon_droq.h"
23 #include "octeon_iq.h"
24 #include "response_manager.h"
25 #include "octeon_device.h"
26 #include "cn23xx_pf_device.h"
27 #include "octeon_main.h"
28 #include "octeon_mailbox.h"
29
30 #define RESET_NOTDONE 0
31 #define RESET_DONE 1
32
33 /* Change the value of SLI Packet Input Jabber Register to allow
34 * VXLAN TSO packets which can be 64424 bytes, exceeding the
35 * MAX_GSO_SIZE we supplied to the kernel
36 */
37 #define CN23XX_INPUT_JABBER 64600
38
39 void cn23xx_dump_pf_initialized_regs(struct octeon_device *oct)
40 {
41 int i = 0;
42 u32 regval = 0;
43 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
44
45 /*In cn23xx_soft_reset*/
46 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%llx\n",
47 "CN23XX_WIN_WR_MASK_REG", CVM_CAST64(CN23XX_WIN_WR_MASK_REG),
48 CVM_CAST64(octeon_read_csr64(oct, CN23XX_WIN_WR_MASK_REG)));
49 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
50 "CN23XX_SLI_SCRATCH1", CVM_CAST64(CN23XX_SLI_SCRATCH1),
51 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)));
52 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
53 "CN23XX_RST_SOFT_RST", CN23XX_RST_SOFT_RST,
54 lio_pci_readq(oct, CN23XX_RST_SOFT_RST));
55
56 /*In cn23xx_set_dpi_regs*/
57 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
58 "CN23XX_DPI_DMA_CONTROL", CN23XX_DPI_DMA_CONTROL,
59 lio_pci_readq(oct, CN23XX_DPI_DMA_CONTROL));
60
61 for (i = 0; i < 6; i++) {
62 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
63 "CN23XX_DPI_DMA_ENG_ENB", i,
64 CN23XX_DPI_DMA_ENG_ENB(i),
65 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_ENB(i)));
66 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
67 "CN23XX_DPI_DMA_ENG_BUF", i,
68 CN23XX_DPI_DMA_ENG_BUF(i),
69 lio_pci_readq(oct, CN23XX_DPI_DMA_ENG_BUF(i)));
70 }
71
72 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n", "CN23XX_DPI_CTL",
73 CN23XX_DPI_CTL, lio_pci_readq(oct, CN23XX_DPI_CTL));
74
75 /*In cn23xx_setup_pcie_mps and cn23xx_setup_pcie_mrrs */
76 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
77 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
78 "CN23XX_CONFIG_PCIE_DEVCTL",
79 CVM_CAST64(CN23XX_CONFIG_PCIE_DEVCTL), CVM_CAST64(regval));
80
81 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
82 "CN23XX_DPI_SLI_PRTX_CFG", oct->pcie_port,
83 CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port),
84 lio_pci_readq(oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port)));
85
86 /*In cn23xx_specific_regs_setup */
87 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
88 "CN23XX_SLI_S2M_PORTX_CTL", oct->pcie_port,
89 CVM_CAST64(CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port)),
90 CVM_CAST64(octeon_read_csr64(
91 oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port))));
92
93 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
94 "CN23XX_SLI_RING_RST", CVM_CAST64(CN23XX_SLI_PKT_IOQ_RING_RST),
95 (u64)octeon_read_csr64(oct, CN23XX_SLI_PKT_IOQ_RING_RST));
96
97 /*In cn23xx_setup_global_mac_regs*/
98 for (i = 0; i < CN23XX_MAX_MACS; i++) {
99 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
100 "CN23XX_SLI_PKT_MAC_RINFO64", i,
101 CVM_CAST64(CN23XX_SLI_PKT_MAC_RINFO64(i, oct->pf_num)),
102 CVM_CAST64(octeon_read_csr64
103 (oct, CN23XX_SLI_PKT_MAC_RINFO64
104 (i, oct->pf_num))));
105 }
106
107 /*In cn23xx_setup_global_input_regs*/
108 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
109 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
110 "CN23XX_SLI_IQ_PKT_CONTROL64", i,
111 CVM_CAST64(CN23XX_SLI_IQ_PKT_CONTROL64(i)),
112 CVM_CAST64(octeon_read_csr64
113 (oct, CN23XX_SLI_IQ_PKT_CONTROL64(i))));
114 }
115
116 /*In cn23xx_setup_global_output_regs*/
117 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
118 "CN23XX_SLI_OQ_WMARK", CVM_CAST64(CN23XX_SLI_OQ_WMARK),
119 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_OQ_WMARK)));
120
121 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
122 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
123 "CN23XX_SLI_OQ_PKT_CONTROL", i,
124 CVM_CAST64(CN23XX_SLI_OQ_PKT_CONTROL(i)),
125 CVM_CAST64(octeon_read_csr(
126 oct, CN23XX_SLI_OQ_PKT_CONTROL(i))));
127 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
128 "CN23XX_SLI_OQ_PKT_INT_LEVELS", i,
129 CVM_CAST64(CN23XX_SLI_OQ_PKT_INT_LEVELS(i)),
130 CVM_CAST64(octeon_read_csr64(
131 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(i))));
132 }
133
134 /*In cn23xx_enable_interrupt and cn23xx_disable_interrupt*/
135 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
136 "cn23xx->intr_enb_reg64",
137 CVM_CAST64((long)(cn23xx->intr_enb_reg64)),
138 CVM_CAST64(readq(cn23xx->intr_enb_reg64)));
139
140 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
141 "cn23xx->intr_sum_reg64",
142 CVM_CAST64((long)(cn23xx->intr_sum_reg64)),
143 CVM_CAST64(readq(cn23xx->intr_sum_reg64)));
144
145 /*In cn23xx_setup_iq_regs*/
146 for (i = 0; i < CN23XX_MAX_INPUT_QUEUES; i++) {
147 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
148 "CN23XX_SLI_IQ_BASE_ADDR64", i,
149 CVM_CAST64(CN23XX_SLI_IQ_BASE_ADDR64(i)),
150 CVM_CAST64(octeon_read_csr64(
151 oct, CN23XX_SLI_IQ_BASE_ADDR64(i))));
152 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
153 "CN23XX_SLI_IQ_SIZE", i,
154 CVM_CAST64(CN23XX_SLI_IQ_SIZE(i)),
155 CVM_CAST64(octeon_read_csr
156 (oct, CN23XX_SLI_IQ_SIZE(i))));
157 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
158 "CN23XX_SLI_IQ_DOORBELL", i,
159 CVM_CAST64(CN23XX_SLI_IQ_DOORBELL(i)),
160 CVM_CAST64(octeon_read_csr64(
161 oct, CN23XX_SLI_IQ_DOORBELL(i))));
162 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
163 "CN23XX_SLI_IQ_INSTR_COUNT64", i,
164 CVM_CAST64(CN23XX_SLI_IQ_INSTR_COUNT64(i)),
165 CVM_CAST64(octeon_read_csr64(
166 oct, CN23XX_SLI_IQ_INSTR_COUNT64(i))));
167 }
168
169 /*In cn23xx_setup_oq_regs*/
170 for (i = 0; i < CN23XX_MAX_OUTPUT_QUEUES; i++) {
171 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
172 "CN23XX_SLI_OQ_BASE_ADDR64", i,
173 CVM_CAST64(CN23XX_SLI_OQ_BASE_ADDR64(i)),
174 CVM_CAST64(octeon_read_csr64(
175 oct, CN23XX_SLI_OQ_BASE_ADDR64(i))));
176 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
177 "CN23XX_SLI_OQ_SIZE", i,
178 CVM_CAST64(CN23XX_SLI_OQ_SIZE(i)),
179 CVM_CAST64(octeon_read_csr
180 (oct, CN23XX_SLI_OQ_SIZE(i))));
181 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
182 "CN23XX_SLI_OQ_BUFF_INFO_SIZE", i,
183 CVM_CAST64(CN23XX_SLI_OQ_BUFF_INFO_SIZE(i)),
184 CVM_CAST64(octeon_read_csr(
185 oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(i))));
186 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
187 "CN23XX_SLI_OQ_PKTS_SENT", i,
188 CVM_CAST64(CN23XX_SLI_OQ_PKTS_SENT(i)),
189 CVM_CAST64(octeon_read_csr64(
190 oct, CN23XX_SLI_OQ_PKTS_SENT(i))));
191 dev_dbg(&oct->pci_dev->dev, "%s(%d)[%llx] : 0x%016llx\n",
192 "CN23XX_SLI_OQ_PKTS_CREDIT", i,
193 CVM_CAST64(CN23XX_SLI_OQ_PKTS_CREDIT(i)),
194 CVM_CAST64(octeon_read_csr64(
195 oct, CN23XX_SLI_OQ_PKTS_CREDIT(i))));
196 }
197
198 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
199 "CN23XX_SLI_PKT_TIME_INT",
200 CVM_CAST64(CN23XX_SLI_PKT_TIME_INT),
201 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_TIME_INT)));
202 dev_dbg(&oct->pci_dev->dev, "%s[%llx] : 0x%016llx\n",
203 "CN23XX_SLI_PKT_CNT_INT",
204 CVM_CAST64(CN23XX_SLI_PKT_CNT_INT),
205 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_PKT_CNT_INT)));
206 }
207
208 static int cn23xx_pf_soft_reset(struct octeon_device *oct)
209 {
210 octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);
211
212 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: BIST enabled for CN23XX soft reset\n",
213 oct->octeon_id);
214
215 octeon_write_csr64(oct, CN23XX_SLI_SCRATCH1, 0x1234ULL);
216
217 /* Initiate chip-wide soft reset */
218 lio_pci_readq(oct, CN23XX_RST_SOFT_RST);
219 lio_pci_writeq(oct, 1, CN23XX_RST_SOFT_RST);
220
221 /* Wait for 100ms as Octeon resets. */
222 mdelay(100);
223
224 if (octeon_read_csr64(oct, CN23XX_SLI_SCRATCH1)) {
225 dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Soft reset failed\n",
226 oct->octeon_id);
227 return 1;
228 }
229
230 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Reset completed\n",
231 oct->octeon_id);
232
233 /* restore the reset value*/
234 octeon_write_csr64(oct, CN23XX_WIN_WR_MASK_REG, 0xFF);
235
236 return 0;
237 }
238
239 static void cn23xx_enable_error_reporting(struct octeon_device *oct)
240 {
241 u32 regval;
242 u32 uncorrectable_err_mask, corrtable_err_status;
243
244 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
245 if (regval & CN23XX_CONFIG_PCIE_DEVCTL_MASK) {
246 uncorrectable_err_mask = 0;
247 corrtable_err_status = 0;
248 pci_read_config_dword(oct->pci_dev,
249 CN23XX_CONFIG_PCIE_UNCORRECT_ERR_MASK,
250 &uncorrectable_err_mask);
251 pci_read_config_dword(oct->pci_dev,
252 CN23XX_CONFIG_PCIE_CORRECT_ERR_STATUS,
253 &corrtable_err_status);
254 dev_err(&oct->pci_dev->dev, "PCI-E Fatal error detected;\n"
255 "\tdev_ctl_status_reg = 0x%08x\n"
256 "\tuncorrectable_error_mask_reg = 0x%08x\n"
257 "\tcorrectable_error_status_reg = 0x%08x\n",
258 regval, uncorrectable_err_mask,
259 corrtable_err_status);
260 }
261
262 regval |= 0xf; /* Enable Link error reporting */
263
264 dev_dbg(&oct->pci_dev->dev, "OCTEON[%d]: Enabling PCI-E error reporting..\n",
265 oct->octeon_id);
266 pci_write_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, regval);
267 }
268
269 static u32 cn23xx_coprocessor_clock(struct octeon_device *oct)
270 {
271 /* Bits 29:24 of RST_BOOT[PNR_MUL] holds the ref.clock MULTIPLIER
272 * for SLI.
273 */
274
275 /* TBD: get the info in Hand-shake */
276 return (((lio_pci_readq(oct, CN23XX_RST_BOOT) >> 24) & 0x3f) * 50);
277 }
278
279 u32 cn23xx_pf_get_oq_ticks(struct octeon_device *oct, u32 time_intr_in_us)
280 {
281 /* This gives the SLI clock per microsec */
282 u32 oqticks_per_us = cn23xx_coprocessor_clock(oct);
283
284 oct->pfvf_hsword.coproc_tics_per_us = oqticks_per_us;
285
286 /* This gives the clock cycles per millisecond */
287 oqticks_per_us *= 1000;
288
289 /* This gives the oq ticks (1024 core clock cycles) per millisecond */
290 oqticks_per_us /= 1024;
291
292 /* time_intr is in microseconds. The next 2 steps gives the oq ticks
293 * corressponding to time_intr.
294 */
295 oqticks_per_us *= time_intr_in_us;
296 oqticks_per_us /= 1000;
297
298 return oqticks_per_us;
299 }
300
301 static void cn23xx_setup_global_mac_regs(struct octeon_device *oct)
302 {
303 u16 mac_no = oct->pcie_port;
304 u16 pf_num = oct->pf_num;
305 u64 reg_val;
306 u64 temp;
307
308 /* programming SRN and TRS for each MAC(0..3) */
309
310 dev_dbg(&oct->pci_dev->dev, "%s:Using pcie port %d\n",
311 __func__, mac_no);
312 /* By default, mapping all 64 IOQs to a single MACs */
313
314 reg_val =
315 octeon_read_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num));
316
317 if (oct->rev_id == OCTEON_CN23XX_REV_1_1) {
318 /* setting SRN <6:0> */
319 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
320 } else {
321 /* setting SRN <6:0> */
322 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF;
323 }
324
325 /* setting TRS <23:16> */
326 reg_val = reg_val |
327 (oct->sriov_info.trs << CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS);
328 /* setting RPVF <39:32> */
329 temp = oct->sriov_info.rings_per_vf & 0xff;
330 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS);
331
332 /* setting NVFS <55:48> */
333 temp = oct->sriov_info.max_vfs & 0xff;
334 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS);
335
336 /* write these settings to MAC register */
337 octeon_write_csr64(oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num),
338 reg_val);
339
340 dev_dbg(&oct->pci_dev->dev, "SLI_PKT_MAC(%d)_PF(%d)_RINFO : 0x%016llx\n",
341 mac_no, pf_num, (u64)octeon_read_csr64
342 (oct, CN23XX_SLI_PKT_MAC_RINFO64(mac_no, pf_num)));
343 }
344
345 static int cn23xx_reset_io_queues(struct octeon_device *oct)
346 {
347 int ret_val = 0;
348 u64 d64;
349 u32 q_no, srn, ern;
350 u32 loop = 1000;
351
352 srn = oct->sriov_info.pf_srn;
353 ern = srn + oct->sriov_info.num_pf_rings;
354
355 /*As per HRM reg description, s/w cant write 0 to ENB. */
356 /*to make the queue off, need to set the RST bit. */
357
358 /* Reset the Enable bit for all the 64 IQs. */
359 for (q_no = srn; q_no < ern; q_no++) {
360 /* set RST bit to 1. This bit applies to both IQ and OQ */
361 d64 = octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
362 d64 = d64 | CN23XX_PKT_INPUT_CTL_RST;
363 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), d64);
364 }
365
366 /*wait until the RST bit is clear or the RST and quite bits are set*/
367 for (q_no = srn; q_no < ern; q_no++) {
368 u64 reg_val = octeon_read_csr64(oct,
369 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
370 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) &&
371 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) &&
372 loop--) {
373 WRITE_ONCE(reg_val, octeon_read_csr64(
374 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));
375 }
376 if (!loop) {
377 dev_err(&oct->pci_dev->dev,
378 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
379 q_no);
380 return -1;
381 }
382 WRITE_ONCE(reg_val, READ_ONCE(reg_val) &
383 ~CN23XX_PKT_INPUT_CTL_RST);
384 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
385 READ_ONCE(reg_val));
386
387 WRITE_ONCE(reg_val, octeon_read_csr64(
388 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));
389 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) {
390 dev_err(&oct->pci_dev->dev,
391 "clearing the reset failed for qno: %u\n",
392 q_no);
393 ret_val = -1;
394 }
395 }
396
397 return ret_val;
398 }
399
400 static int cn23xx_pf_setup_global_input_regs(struct octeon_device *oct)
401 {
402 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
403 struct octeon_instr_queue *iq;
404 u64 intr_threshold, reg_val;
405 u32 q_no, ern, srn;
406 u64 pf_num;
407 u64 vf_num;
408
409 pf_num = oct->pf_num;
410
411 srn = oct->sriov_info.pf_srn;
412 ern = srn + oct->sriov_info.num_pf_rings;
413
414 if (cn23xx_reset_io_queues(oct))
415 return -1;
416
417 /** Set the MAC_NUM and PVF_NUM in IQ_PKT_CONTROL reg
418 * for all queues.Only PF can set these bits.
419 * bits 29:30 indicate the MAC num.
420 * bits 32:47 indicate the PVF num.
421 */
422 for (q_no = 0; q_no < ern; q_no++) {
423 reg_val = oct->pcie_port << CN23XX_PKT_INPUT_CTL_MAC_NUM_POS;
424
425 /* for VF assigned queues. */
426 if (q_no < oct->sriov_info.pf_srn) {
427 vf_num = q_no / oct->sriov_info.rings_per_vf;
428 vf_num += 1; /* VF1, VF2,........ */
429 } else {
430 vf_num = 0;
431 }
432
433 reg_val |= vf_num << CN23XX_PKT_INPUT_CTL_VF_NUM_POS;
434 reg_val |= pf_num << CN23XX_PKT_INPUT_CTL_PF_NUM_POS;
435
436 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
437 reg_val);
438 }
439
440 /* Select ES, RO, NS, RDSIZE,DPTR Fomat#0 for
441 * pf queues
442 */
443 for (q_no = srn; q_no < ern; q_no++) {
444 void __iomem *inst_cnt_reg;
445
446 iq = oct->instr_queue[q_no];
447 if (iq)
448 inst_cnt_reg = iq->inst_cnt_reg;
449 else
450 inst_cnt_reg = (u8 *)oct->mmio[0].hw_addr +
451 CN23XX_SLI_IQ_INSTR_COUNT64(q_no);
452
453 reg_val =
454 octeon_read_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
455
456 reg_val |= CN23XX_PKT_INPUT_CTL_MASK;
457
458 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
459 reg_val);
460
461 /* Set WMARK level for triggering PI_INT */
462 /* intr_threshold = CN23XX_DEF_IQ_INTR_THRESHOLD & */
463 intr_threshold = CFG_GET_IQ_INTR_PKT(cn23xx->conf) &
464 CN23XX_PKT_IN_DONE_WMARK_MASK;
465
466 writeq((readq(inst_cnt_reg) &
467 ~(CN23XX_PKT_IN_DONE_WMARK_MASK <<
468 CN23XX_PKT_IN_DONE_WMARK_BIT_POS)) |
469 (intr_threshold << CN23XX_PKT_IN_DONE_WMARK_BIT_POS),
470 inst_cnt_reg);
471 }
472 return 0;
473 }
474
475 static void cn23xx_pf_setup_global_output_regs(struct octeon_device *oct)
476 {
477 u32 reg_val;
478 u32 q_no, ern, srn;
479 u64 time_threshold;
480
481 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
482
483 srn = oct->sriov_info.pf_srn;
484 ern = srn + oct->sriov_info.num_pf_rings;
485
486 if (CFG_GET_IS_SLI_BP_ON(cn23xx->conf)) {
487 octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 32);
488 } else {
489 /** Set Output queue watermark to 0 to disable backpressure */
490 octeon_write_csr64(oct, CN23XX_SLI_OQ_WMARK, 0);
491 }
492
493 for (q_no = srn; q_no < ern; q_no++) {
494 reg_val = octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
495
496 /* set DPTR */
497 reg_val |= CN23XX_PKT_OUTPUT_CTL_DPTR;
498
499 /* reset BMODE */
500 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_BMODE);
501
502 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
503 * for Output Queue ScatterList
504 * reset ROR_P, NSR_P
505 */
506 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR_P);
507 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR_P);
508
509 #ifdef __LITTLE_ENDIAN_BITFIELD
510 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ES_P);
511 #else
512 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES_P);
513 #endif
514 /* No Relaxed Ordering, No Snoop, 64-bit Byte swap
515 * for Output Queue Data
516 * reset ROR, NSR
517 */
518 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_ROR);
519 reg_val &= ~(CN23XX_PKT_OUTPUT_CTL_NSR);
520 /* set the ES bit */
521 reg_val |= (CN23XX_PKT_OUTPUT_CTL_ES);
522
523 /* write all the selected settings */
524 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no), reg_val);
525
526 /* Enabling these interrupt in oct->fn_list.enable_interrupt()
527 * routine which called after IOQ init.
528 * Set up interrupt packet and time thresholds
529 * for all the OQs
530 */
531 time_threshold = cn23xx_pf_get_oq_ticks(
532 oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
533
534 octeon_write_csr64(oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(q_no),
535 (CFG_GET_OQ_INTR_PKT(cn23xx->conf) |
536 (time_threshold << 32)));
537 }
538
539 /** Setting the water mark level for pko back pressure **/
540 writeq(0x40, (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_WMARK);
541
542 /** Disabling setting OQs in reset when ring has no dorebells
543 * enabling this will cause of head of line blocking
544 */
545 /* Do it only for pass1.1. and pass1.2 */
546 if ((oct->rev_id == OCTEON_CN23XX_REV_1_0) ||
547 (oct->rev_id == OCTEON_CN23XX_REV_1_1))
548 writeq(readq((u8 *)oct->mmio[0].hw_addr +
549 CN23XX_SLI_GBL_CONTROL) | 0x2,
550 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_GBL_CONTROL);
551
552 /** Enable channel-level backpressure */
553 if (oct->pf_num)
554 writeq(0xffffffffffffffffULL,
555 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN2_W1S);
556 else
557 writeq(0xffffffffffffffffULL,
558 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OUT_BP_EN_W1S);
559 }
560
561 static int cn23xx_setup_pf_device_regs(struct octeon_device *oct)
562 {
563 cn23xx_enable_error_reporting(oct);
564
565 /* program the MAC(0..3)_RINFO before setting up input/output regs */
566 cn23xx_setup_global_mac_regs(oct);
567
568 if (cn23xx_pf_setup_global_input_regs(oct))
569 return -1;
570
571 cn23xx_pf_setup_global_output_regs(oct);
572
573 /* Default error timeout value should be 0x200000 to avoid host hang
574 * when reads invalid register
575 */
576 octeon_write_csr64(oct, CN23XX_SLI_WINDOW_CTL,
577 CN23XX_SLI_WINDOW_CTL_DEFAULT);
578
579 /* set SLI_PKT_IN_JABBER to handle large VXLAN packets */
580 octeon_write_csr64(oct, CN23XX_SLI_PKT_IN_JABBER, CN23XX_INPUT_JABBER);
581 return 0;
582 }
583
584 static void cn23xx_setup_iq_regs(struct octeon_device *oct, u32 iq_no)
585 {
586 struct octeon_instr_queue *iq = oct->instr_queue[iq_no];
587 u64 pkt_in_done;
588
589 iq_no += oct->sriov_info.pf_srn;
590
591 /* Write the start of the input queue's ring and its size */
592 octeon_write_csr64(oct, CN23XX_SLI_IQ_BASE_ADDR64(iq_no),
593 iq->base_addr_dma);
594 octeon_write_csr(oct, CN23XX_SLI_IQ_SIZE(iq_no), iq->max_count);
595
596 /* Remember the doorbell & instruction count register addr
597 * for this queue
598 */
599 iq->doorbell_reg =
600 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_DOORBELL(iq_no);
601 iq->inst_cnt_reg =
602 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_IQ_INSTR_COUNT64(iq_no);
603 dev_dbg(&oct->pci_dev->dev, "InstQ[%d]:dbell reg @ 0x%p instcnt_reg @ 0x%p\n",
604 iq_no, iq->doorbell_reg, iq->inst_cnt_reg);
605
606 /* Store the current instruction counter (used in flush_iq
607 * calculation)
608 */
609 pkt_in_done = readq(iq->inst_cnt_reg);
610
611 if (oct->msix_on) {
612 /* Set CINT_ENB to enable IQ interrupt */
613 writeq((pkt_in_done | CN23XX_INTR_CINT_ENB),
614 iq->inst_cnt_reg);
615 } else {
616 /* Clear the count by writing back what we read, but don't
617 * enable interrupts
618 */
619 writeq(pkt_in_done, iq->inst_cnt_reg);
620 }
621
622 iq->reset_instr_cnt = 0;
623 }
624
625 static void cn23xx_setup_oq_regs(struct octeon_device *oct, u32 oq_no)
626 {
627 u32 reg_val;
628 struct octeon_droq *droq = oct->droq[oq_no];
629 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
630 u64 time_threshold;
631 u64 cnt_threshold;
632
633 oq_no += oct->sriov_info.pf_srn;
634
635 octeon_write_csr64(oct, CN23XX_SLI_OQ_BASE_ADDR64(oq_no),
636 droq->desc_ring_dma);
637 octeon_write_csr(oct, CN23XX_SLI_OQ_SIZE(oq_no), droq->max_count);
638
639 octeon_write_csr(oct, CN23XX_SLI_OQ_BUFF_INFO_SIZE(oq_no),
640 droq->buffer_size);
641
642 /* Get the mapped address of the pkt_sent and pkts_credit regs */
643 droq->pkts_sent_reg =
644 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_SENT(oq_no);
645 droq->pkts_credit_reg =
646 (u8 *)oct->mmio[0].hw_addr + CN23XX_SLI_OQ_PKTS_CREDIT(oq_no);
647
648 if (!oct->msix_on) {
649 /* Enable this output queue to generate Packet Timer Interrupt
650 */
651 reg_val =
652 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
653 reg_val |= CN23XX_PKT_OUTPUT_CTL_TENB;
654 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
655 reg_val);
656
657 /* Enable this output queue to generate Packet Count Interrupt
658 */
659 reg_val =
660 octeon_read_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no));
661 reg_val |= CN23XX_PKT_OUTPUT_CTL_CENB;
662 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(oq_no),
663 reg_val);
664 } else {
665 time_threshold = cn23xx_pf_get_oq_ticks(
666 oct, (u32)CFG_GET_OQ_INTR_TIME(cn23xx->conf));
667 cnt_threshold = (u32)CFG_GET_OQ_INTR_PKT(cn23xx->conf);
668
669 octeon_write_csr64(
670 oct, CN23XX_SLI_OQ_PKT_INT_LEVELS(oq_no),
671 ((time_threshold << 32 | cnt_threshold)));
672 }
673 }
674
675 static void cn23xx_pf_mbox_thread(struct work_struct *work)
676 {
677 struct cavium_wk *wk = (struct cavium_wk *)work;
678 struct octeon_mbox *mbox = (struct octeon_mbox *)wk->ctxptr;
679 struct octeon_device *oct = mbox->oct_dev;
680 u64 mbox_int_val, val64;
681 u32 q_no, i;
682
683 if (oct->rev_id < OCTEON_CN23XX_REV_1_1) {
684 /*read and clear by writing 1*/
685 mbox_int_val = readq(mbox->mbox_int_reg);
686 writeq(mbox_int_val, mbox->mbox_int_reg);
687
688 for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) {
689 q_no = i * oct->sriov_info.rings_per_vf;
690
691 val64 = readq(oct->mbox[q_no]->mbox_write_reg);
692
693 if (val64 && (val64 != OCTEON_PFVFACK)) {
694 if (octeon_mbox_read(oct->mbox[q_no]))
695 octeon_mbox_process_message(
696 oct->mbox[q_no]);
697 }
698 }
699
700 schedule_delayed_work(&wk->work, msecs_to_jiffies(10));
701 } else {
702 octeon_mbox_process_message(mbox);
703 }
704 }
705
706 static int cn23xx_setup_pf_mbox(struct octeon_device *oct)
707 {
708 struct octeon_mbox *mbox = NULL;
709 u16 mac_no = oct->pcie_port;
710 u16 pf_num = oct->pf_num;
711 u32 q_no, i;
712
713 if (!oct->sriov_info.max_vfs)
714 return 0;
715
716 for (i = 0; i < oct->sriov_info.max_vfs; i++) {
717 q_no = i * oct->sriov_info.rings_per_vf;
718
719 mbox = vmalloc(sizeof(*mbox));
720 if (!mbox)
721 goto free_mbox;
722
723 memset(mbox, 0, sizeof(struct octeon_mbox));
724
725 spin_lock_init(&mbox->lock);
726
727 mbox->oct_dev = oct;
728
729 mbox->q_no = q_no;
730
731 mbox->state = OCTEON_MBOX_STATE_IDLE;
732
733 /* PF mbox interrupt reg */
734 mbox->mbox_int_reg = (u8 *)oct->mmio[0].hw_addr +
735 CN23XX_SLI_MAC_PF_MBOX_INT(mac_no, pf_num);
736
737 /* PF writes into SIG0 reg */
738 mbox->mbox_write_reg = (u8 *)oct->mmio[0].hw_addr +
739 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q_no, 0);
740
741 /* PF reads from SIG1 reg */
742 mbox->mbox_read_reg = (u8 *)oct->mmio[0].hw_addr +
743 CN23XX_SLI_PKT_PF_VF_MBOX_SIG(q_no, 1);
744
745 /*Mail Box Thread creation*/
746 INIT_DELAYED_WORK(&mbox->mbox_poll_wk.work,
747 cn23xx_pf_mbox_thread);
748 mbox->mbox_poll_wk.ctxptr = (void *)mbox;
749
750 oct->mbox[q_no] = mbox;
751
752 writeq(OCTEON_PFVFSIG, mbox->mbox_read_reg);
753 }
754
755 if (oct->rev_id < OCTEON_CN23XX_REV_1_1)
756 schedule_delayed_work(&oct->mbox[0]->mbox_poll_wk.work,
757 msecs_to_jiffies(0));
758
759 return 0;
760
761 free_mbox:
762 while (i) {
763 i--;
764 vfree(oct->mbox[i]);
765 }
766
767 return 1;
768 }
769
770 static int cn23xx_free_pf_mbox(struct octeon_device *oct)
771 {
772 u32 q_no, i;
773
774 if (!oct->sriov_info.max_vfs)
775 return 0;
776
777 for (i = 0; i < oct->sriov_info.max_vfs; i++) {
778 q_no = i * oct->sriov_info.rings_per_vf;
779 cancel_delayed_work_sync(
780 &oct->mbox[q_no]->mbox_poll_wk.work);
781 vfree(oct->mbox[q_no]);
782 }
783
784 return 0;
785 }
786
787 static int cn23xx_enable_io_queues(struct octeon_device *oct)
788 {
789 u64 reg_val;
790 u32 srn, ern, q_no;
791 u32 loop = 1000;
792
793 srn = oct->sriov_info.pf_srn;
794 ern = srn + oct->num_iqs;
795
796 for (q_no = srn; q_no < ern; q_no++) {
797 /* set the corresponding IQ IS_64B bit */
798 if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {
799 reg_val = octeon_read_csr64(
800 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
801 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_IS_64B;
802 octeon_write_csr64(
803 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
804 }
805
806 /* set the corresponding IQ ENB bit */
807 if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {
808 /* IOQs are in reset by default in PEM2 mode,
809 * clearing reset bit
810 */
811 reg_val = octeon_read_csr64(
812 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
813
814 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
815 while ((reg_val & CN23XX_PKT_INPUT_CTL_RST) &&
816 !(reg_val &
817 CN23XX_PKT_INPUT_CTL_QUIET) &&
818 --loop) {
819 reg_val = octeon_read_csr64(
820 oct,
821 CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
822 }
823 if (!loop) {
824 dev_err(&oct->pci_dev->dev,
825 "clearing the reset reg failed or setting the quiet reg failed for qno: %u\n",
826 q_no);
827 return -1;
828 }
829 reg_val = reg_val & ~CN23XX_PKT_INPUT_CTL_RST;
830 octeon_write_csr64(
831 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
832 reg_val);
833
834 reg_val = octeon_read_csr64(
835 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
836 if (reg_val & CN23XX_PKT_INPUT_CTL_RST) {
837 dev_err(&oct->pci_dev->dev,
838 "clearing the reset failed for qno: %u\n",
839 q_no);
840 return -1;
841 }
842 }
843 reg_val = octeon_read_csr64(
844 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no));
845 reg_val = reg_val | CN23XX_PKT_INPUT_CTL_RING_ENB;
846 octeon_write_csr64(
847 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no), reg_val);
848 }
849 }
850 for (q_no = srn; q_no < ern; q_no++) {
851 u32 reg_val;
852 /* set the corresponding OQ ENB bit */
853 if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {
854 reg_val = octeon_read_csr(
855 oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no));
856 reg_val = reg_val | CN23XX_PKT_OUTPUT_CTL_RING_ENB;
857 octeon_write_csr(oct, CN23XX_SLI_OQ_PKT_CONTROL(q_no),
858 reg_val);
859 }
860 }
861 return 0;
862 }
863
864 static void cn23xx_disable_io_queues(struct octeon_device *oct)
865 {
866 int q_no, loop;
867 u64 d64;
868 u32 d32;
869 u32 srn, ern;
870
871 srn = oct->sriov_info.pf_srn;
872 ern = srn + oct->num_iqs;
873
874 /*** Disable Input Queues. ***/
875 for (q_no = srn; q_no < ern; q_no++) {
876 loop = HZ;
877
878 /* start the Reset for a particular ring */
879 WRITE_ONCE(d64, octeon_read_csr64(
880 oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no)));
881 WRITE_ONCE(d64, READ_ONCE(d64) &
882 (~(CN23XX_PKT_INPUT_CTL_RING_ENB)));
883 WRITE_ONCE(d64, READ_ONCE(d64) | CN23XX_PKT_INPUT_CTL_RST);
884 octeon_write_csr64(oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
885 READ_ONCE(d64));
886
887 /* Wait until hardware indicates that the particular IQ
888 * is out of reset.
889 */
890 WRITE_ONCE(d64, octeon_read_csr64(
891 oct, CN23XX_SLI_PKT_IOQ_RING_RST));
892 while (!(READ_ONCE(d64) & BIT_ULL(q_no)) && loop--) {
893 WRITE_ONCE(d64, octeon_read_csr64(
894 oct, CN23XX_SLI_PKT_IOQ_RING_RST));
895 schedule_timeout_uninterruptible(1);
896 }
897
898 /* Reset the doorbell register for this Input Queue. */
899 octeon_write_csr(oct, CN23XX_SLI_IQ_DOORBELL(q_no), 0xFFFFFFFF);
900 while (octeon_read_csr64(oct, CN23XX_SLI_IQ_DOORBELL(q_no)) &&
901 loop--) {
902 schedule_timeout_uninterruptible(1);
903 }
904 }
905
906 /*** Disable Output Queues. ***/
907 for (q_no = srn; q_no < ern; q_no++) {
908 loop = HZ;
909
910 /* Wait until hardware indicates that the particular IQ
911 * is out of reset.It given that SLI_PKT_RING_RST is
912 * common for both IQs and OQs
913 */
914 WRITE_ONCE(d64, octeon_read_csr64(
915 oct, CN23XX_SLI_PKT_IOQ_RING_RST));
916 while (!(READ_ONCE(d64) & BIT_ULL(q_no)) && loop--) {
917 WRITE_ONCE(d64, octeon_read_csr64(
918 oct, CN23XX_SLI_PKT_IOQ_RING_RST));
919 schedule_timeout_uninterruptible(1);
920 }
921
922 /* Reset the doorbell register for this Output Queue. */
923 octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_CREDIT(q_no),
924 0xFFFFFFFF);
925 while (octeon_read_csr64(oct,
926 CN23XX_SLI_OQ_PKTS_CREDIT(q_no)) &&
927 loop--) {
928 schedule_timeout_uninterruptible(1);
929 }
930
931 /* clear the SLI_PKT(0..63)_CNTS[CNT] reg value */
932 WRITE_ONCE(d32, octeon_read_csr(
933 oct, CN23XX_SLI_OQ_PKTS_SENT(q_no)));
934 octeon_write_csr(oct, CN23XX_SLI_OQ_PKTS_SENT(q_no),
935 READ_ONCE(d32));
936 }
937 }
938
939 static u64 cn23xx_pf_msix_interrupt_handler(void *dev)
940 {
941 struct octeon_ioq_vector *ioq_vector = (struct octeon_ioq_vector *)dev;
942 struct octeon_device *oct = ioq_vector->oct_dev;
943 u64 pkts_sent;
944 u64 ret = 0;
945 struct octeon_droq *droq = oct->droq[ioq_vector->droq_index];
946
947 dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);
948
949 if (!droq) {
950 dev_err(&oct->pci_dev->dev, "23XX bringup FIXME: oct pfnum:%d ioq_vector->ioq_num :%d droq is NULL\n",
951 oct->pf_num, ioq_vector->ioq_num);
952 return 0;
953 }
954
955 pkts_sent = readq(droq->pkts_sent_reg);
956
957 /* If our device has interrupted, then proceed. Also check
958 * for all f's if interrupt was triggered on an error
959 * and the PCI read fails.
960 */
961 if (!pkts_sent || (pkts_sent == 0xFFFFFFFFFFFFFFFFULL))
962 return ret;
963
964 /* Write count reg in sli_pkt_cnts to clear these int.*/
965 if ((pkts_sent & CN23XX_INTR_PO_INT) ||
966 (pkts_sent & CN23XX_INTR_PI_INT)) {
967 if (pkts_sent & CN23XX_INTR_PO_INT)
968 ret |= MSIX_PO_INT;
969 }
970
971 if (pkts_sent & CN23XX_INTR_PI_INT)
972 /* We will clear the count when we update the read_index. */
973 ret |= MSIX_PI_INT;
974
975 /* Never need to handle msix mbox intr for pf. They arrive on the last
976 * msix
977 */
978 return ret;
979 }
980
981 static void cn23xx_handle_pf_mbox_intr(struct octeon_device *oct)
982 {
983 struct delayed_work *work;
984 u64 mbox_int_val;
985 u32 i, q_no;
986
987 mbox_int_val = readq(oct->mbox[0]->mbox_int_reg);
988
989 for (i = 0; i < oct->sriov_info.num_vfs_alloced; i++) {
990 q_no = i * oct->sriov_info.rings_per_vf;
991
992 if (mbox_int_val & BIT_ULL(q_no)) {
993 writeq(BIT_ULL(q_no),
994 oct->mbox[0]->mbox_int_reg);
995 if (octeon_mbox_read(oct->mbox[q_no])) {
996 work = &oct->mbox[q_no]->mbox_poll_wk.work;
997 schedule_delayed_work(work,
998 msecs_to_jiffies(0));
999 }
1000 }
1001 }
1002 }
1003
1004 static irqreturn_t cn23xx_interrupt_handler(void *dev)
1005 {
1006 struct octeon_device *oct = (struct octeon_device *)dev;
1007 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1008 u64 intr64;
1009
1010 dev_dbg(&oct->pci_dev->dev, "In %s octeon_dev @ %p\n", __func__, oct);
1011 intr64 = readq(cn23xx->intr_sum_reg64);
1012
1013 oct->int_status = 0;
1014
1015 if (intr64 & CN23XX_INTR_ERR)
1016 dev_err(&oct->pci_dev->dev, "OCTEON[%d]: Error Intr: 0x%016llx\n",
1017 oct->octeon_id, CVM_CAST64(intr64));
1018
1019 /* When VFs write into MBOX_SIG2 reg,these intr is set in PF */
1020 if (intr64 & CN23XX_INTR_VF_MBOX)
1021 cn23xx_handle_pf_mbox_intr(oct);
1022
1023 if (oct->msix_on != LIO_FLAG_MSIX_ENABLED) {
1024 if (intr64 & CN23XX_INTR_PKT_DATA)
1025 oct->int_status |= OCT_DEV_INTR_PKT_DATA;
1026 }
1027
1028 if (intr64 & (CN23XX_INTR_DMA0_FORCE))
1029 oct->int_status |= OCT_DEV_INTR_DMA0_FORCE;
1030 if (intr64 & (CN23XX_INTR_DMA1_FORCE))
1031 oct->int_status |= OCT_DEV_INTR_DMA1_FORCE;
1032
1033 /* Clear the current interrupts */
1034 writeq(intr64, cn23xx->intr_sum_reg64);
1035
1036 return IRQ_HANDLED;
1037 }
1038
1039 static void cn23xx_bar1_idx_setup(struct octeon_device *oct, u64 core_addr,
1040 u32 idx, int valid)
1041 {
1042 u64 bar1;
1043 u64 reg_adr;
1044
1045 if (!valid) {
1046 reg_adr = lio_pci_readq(
1047 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1048 WRITE_ONCE(bar1, reg_adr);
1049 lio_pci_writeq(oct, (READ_ONCE(bar1) & 0xFFFFFFFEULL),
1050 CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1051 reg_adr = lio_pci_readq(
1052 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1053 WRITE_ONCE(bar1, reg_adr);
1054 return;
1055 }
1056
1057 /* The PEM(0..3)_BAR1_INDEX(0..15)[ADDR_IDX]<23:4> stores
1058 * bits <41:22> of the Core Addr
1059 */
1060 lio_pci_writeq(oct, (((core_addr >> 22) << 4) | PCI_BAR1_MASK),
1061 CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1062
1063 WRITE_ONCE(bar1, lio_pci_readq(
1064 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx)));
1065 }
1066
1067 static void cn23xx_bar1_idx_write(struct octeon_device *oct, u32 idx, u32 mask)
1068 {
1069 lio_pci_writeq(oct, mask,
1070 CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1071 }
1072
1073 static u32 cn23xx_bar1_idx_read(struct octeon_device *oct, u32 idx)
1074 {
1075 return (u32)lio_pci_readq(
1076 oct, CN23XX_PEM_BAR1_INDEX_REG(oct->pcie_port, idx));
1077 }
1078
1079 /* always call with lock held */
1080 static u32 cn23xx_update_read_index(struct octeon_instr_queue *iq)
1081 {
1082 u32 new_idx;
1083 u32 last_done;
1084 u32 pkt_in_done = readl(iq->inst_cnt_reg);
1085
1086 last_done = pkt_in_done - iq->pkt_in_done;
1087 iq->pkt_in_done = pkt_in_done;
1088
1089 /* Modulo of the new index with the IQ size will give us
1090 * the new index. The iq->reset_instr_cnt is always zero for
1091 * cn23xx, so no extra adjustments are needed.
1092 */
1093 new_idx = (iq->octeon_read_index +
1094 (u32)(last_done & CN23XX_PKT_IN_DONE_CNT_MASK)) %
1095 iq->max_count;
1096
1097 return new_idx;
1098 }
1099
1100 static void cn23xx_enable_pf_interrupt(struct octeon_device *oct, u8 intr_flag)
1101 {
1102 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1103 u64 intr_val = 0;
1104
1105 /* Divide the single write to multiple writes based on the flag. */
1106 /* Enable Interrupt */
1107 if (intr_flag == OCTEON_ALL_INTR) {
1108 writeq(cn23xx->intr_mask64, cn23xx->intr_enb_reg64);
1109 } else if (intr_flag & OCTEON_OUTPUT_INTR) {
1110 intr_val = readq(cn23xx->intr_enb_reg64);
1111 intr_val |= CN23XX_INTR_PKT_DATA;
1112 writeq(intr_val, cn23xx->intr_enb_reg64);
1113 } else if ((intr_flag & OCTEON_MBOX_INTR) &&
1114 (oct->sriov_info.max_vfs > 0)) {
1115 if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) {
1116 intr_val = readq(cn23xx->intr_enb_reg64);
1117 intr_val |= CN23XX_INTR_VF_MBOX;
1118 writeq(intr_val, cn23xx->intr_enb_reg64);
1119 }
1120 }
1121 }
1122
1123 static void cn23xx_disable_pf_interrupt(struct octeon_device *oct, u8 intr_flag)
1124 {
1125 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1126 u64 intr_val = 0;
1127
1128 /* Disable Interrupts */
1129 if (intr_flag == OCTEON_ALL_INTR) {
1130 writeq(0, cn23xx->intr_enb_reg64);
1131 } else if (intr_flag & OCTEON_OUTPUT_INTR) {
1132 intr_val = readq(cn23xx->intr_enb_reg64);
1133 intr_val &= ~CN23XX_INTR_PKT_DATA;
1134 writeq(intr_val, cn23xx->intr_enb_reg64);
1135 } else if ((intr_flag & OCTEON_MBOX_INTR) &&
1136 (oct->sriov_info.max_vfs > 0)) {
1137 if (oct->rev_id >= OCTEON_CN23XX_REV_1_1) {
1138 intr_val = readq(cn23xx->intr_enb_reg64);
1139 intr_val &= ~CN23XX_INTR_VF_MBOX;
1140 writeq(intr_val, cn23xx->intr_enb_reg64);
1141 }
1142 }
1143 }
1144
1145 static void cn23xx_get_pcie_qlmport(struct octeon_device *oct)
1146 {
1147 oct->pcie_port = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;
1148
1149 dev_dbg(&oct->pci_dev->dev, "OCTEON: CN23xx uses PCIE Port %d\n",
1150 oct->pcie_port);
1151 }
1152
1153 static int cn23xx_get_pf_num(struct octeon_device *oct)
1154 {
1155 u32 fdl_bit = 0;
1156 u64 pkt0_in_ctl, d64;
1157 int pfnum, mac, trs, ret;
1158
1159 ret = 0;
1160
1161 /** Read Function Dependency Link reg to get the function number */
1162 if (pci_read_config_dword(oct->pci_dev, CN23XX_PCIE_SRIOV_FDL,
1163 &fdl_bit) == 0) {
1164 oct->pf_num = ((fdl_bit >> CN23XX_PCIE_SRIOV_FDL_BIT_POS) &
1165 CN23XX_PCIE_SRIOV_FDL_MASK);
1166 } else {
1167 ret = EINVAL;
1168
1169 /* Under some virtual environments, extended PCI regs are
1170 * inaccessible, in which case the above read will have failed.
1171 * In this case, read the PF number from the
1172 * SLI_PKT0_INPUT_CONTROL reg (written by f/w)
1173 */
1174 pkt0_in_ctl = octeon_read_csr64(oct,
1175 CN23XX_SLI_IQ_PKT_CONTROL64(0));
1176 pfnum = (pkt0_in_ctl >> CN23XX_PKT_INPUT_CTL_PF_NUM_POS) &
1177 CN23XX_PKT_INPUT_CTL_PF_NUM_MASK;
1178 mac = (octeon_read_csr(oct, CN23XX_SLI_MAC_NUMBER)) & 0xff;
1179
1180 /* validate PF num by reading RINFO; f/w writes RINFO.trs == 1*/
1181 d64 = octeon_read_csr64(oct,
1182 CN23XX_SLI_PKT_MAC_RINFO64(mac, pfnum));
1183 trs = (int)(d64 >> CN23XX_PKT_MAC_CTL_RINFO_TRS_BIT_POS) & 0xff;
1184 if (trs == 1) {
1185 dev_err(&oct->pci_dev->dev,
1186 "OCTEON: error reading PCI cfg space pfnum, re-read %u\n",
1187 pfnum);
1188 oct->pf_num = pfnum;
1189 ret = 0;
1190 } else {
1191 dev_err(&oct->pci_dev->dev,
1192 "OCTEON: error reading PCI cfg space pfnum; could not ascertain PF number\n");
1193 }
1194 }
1195
1196 return ret;
1197 }
1198
1199 static void cn23xx_setup_reg_address(struct octeon_device *oct)
1200 {
1201 u8 __iomem *bar0_pciaddr = oct->mmio[0].hw_addr;
1202 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1203
1204 oct->reg_list.pci_win_wr_addr_hi =
1205 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_ADDR_HI);
1206 oct->reg_list.pci_win_wr_addr_lo =
1207 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_ADDR_LO);
1208 oct->reg_list.pci_win_wr_addr =
1209 (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_ADDR64);
1210
1211 oct->reg_list.pci_win_rd_addr_hi =
1212 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_ADDR_HI);
1213 oct->reg_list.pci_win_rd_addr_lo =
1214 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_ADDR_LO);
1215 oct->reg_list.pci_win_rd_addr =
1216 (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_ADDR64);
1217
1218 oct->reg_list.pci_win_wr_data_hi =
1219 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_DATA_HI);
1220 oct->reg_list.pci_win_wr_data_lo =
1221 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_DATA_LO);
1222 oct->reg_list.pci_win_wr_data =
1223 (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_WR_DATA64);
1224
1225 oct->reg_list.pci_win_rd_data_hi =
1226 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_DATA_HI);
1227 oct->reg_list.pci_win_rd_data_lo =
1228 (u32 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_DATA_LO);
1229 oct->reg_list.pci_win_rd_data =
1230 (u64 __iomem *)(bar0_pciaddr + CN23XX_WIN_RD_DATA64);
1231
1232 cn23xx_get_pcie_qlmport(oct);
1233
1234 cn23xx->intr_mask64 = CN23XX_INTR_MASK;
1235 if (!oct->msix_on)
1236 cn23xx->intr_mask64 |= CN23XX_INTR_PKT_TIME;
1237 if (oct->rev_id >= OCTEON_CN23XX_REV_1_1)
1238 cn23xx->intr_mask64 |= CN23XX_INTR_VF_MBOX;
1239
1240 cn23xx->intr_sum_reg64 =
1241 bar0_pciaddr +
1242 CN23XX_SLI_MAC_PF_INT_SUM64(oct->pcie_port, oct->pf_num);
1243 cn23xx->intr_enb_reg64 =
1244 bar0_pciaddr +
1245 CN23XX_SLI_MAC_PF_INT_ENB64(oct->pcie_port, oct->pf_num);
1246 }
1247
1248 static int cn23xx_sriov_config(struct octeon_device *oct)
1249 {
1250 struct octeon_cn23xx_pf *cn23xx = (struct octeon_cn23xx_pf *)oct->chip;
1251 u32 max_rings, total_rings, max_vfs, rings_per_vf;
1252 u32 pf_srn, num_pf_rings;
1253 u32 max_possible_vfs;
1254
1255 cn23xx->conf =
1256 (struct octeon_config *)oct_get_config_info(oct, LIO_23XX);
1257 switch (oct->rev_id) {
1258 case OCTEON_CN23XX_REV_1_0:
1259 max_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_0;
1260 max_possible_vfs = CN23XX_MAX_VFS_PER_PF_PASS_1_0;
1261 break;
1262 case OCTEON_CN23XX_REV_1_1:
1263 max_rings = CN23XX_MAX_RINGS_PER_PF_PASS_1_1;
1264 max_possible_vfs = CN23XX_MAX_VFS_PER_PF_PASS_1_1;
1265 break;
1266 default:
1267 max_rings = CN23XX_MAX_RINGS_PER_PF;
1268 max_possible_vfs = CN23XX_MAX_VFS_PER_PF;
1269 break;
1270 }
1271
1272 if (max_rings <= num_present_cpus())
1273 num_pf_rings = 1;
1274 else
1275 num_pf_rings = num_present_cpus();
1276
1277 #ifdef CONFIG_PCI_IOV
1278 max_vfs = min_t(u32,
1279 (max_rings - num_pf_rings), max_possible_vfs);
1280 rings_per_vf = 1;
1281 #else
1282 max_vfs = 0;
1283 rings_per_vf = 0;
1284 #endif
1285
1286 total_rings = num_pf_rings + max_vfs;
1287
1288 /* the first ring of the pf */
1289 pf_srn = total_rings - num_pf_rings;
1290
1291 oct->sriov_info.trs = total_rings;
1292 oct->sriov_info.max_vfs = max_vfs;
1293 oct->sriov_info.rings_per_vf = rings_per_vf;
1294 oct->sriov_info.pf_srn = pf_srn;
1295 oct->sriov_info.num_pf_rings = num_pf_rings;
1296 dev_notice(&oct->pci_dev->dev, "trs:%d max_vfs:%d rings_per_vf:%d pf_srn:%d num_pf_rings:%d\n",
1297 oct->sriov_info.trs, oct->sriov_info.max_vfs,
1298 oct->sriov_info.rings_per_vf, oct->sriov_info.pf_srn,
1299 oct->sriov_info.num_pf_rings);
1300
1301 oct->sriov_info.sriov_enabled = 0;
1302
1303 return 0;
1304 }
1305
1306 int setup_cn23xx_octeon_pf_device(struct octeon_device *oct)
1307 {
1308 u32 data32;
1309 u64 BAR0, BAR1;
1310
1311 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_0, &data32);
1312 BAR0 = (u64)(data32 & ~0xf);
1313 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_1, &data32);
1314 BAR0 |= ((u64)data32 << 32);
1315 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_2, &data32);
1316 BAR1 = (u64)(data32 & ~0xf);
1317 pci_read_config_dword(oct->pci_dev, PCI_BASE_ADDRESS_3, &data32);
1318 BAR1 |= ((u64)data32 << 32);
1319
1320 if (!BAR0 || !BAR1) {
1321 if (!BAR0)
1322 dev_err(&oct->pci_dev->dev, "device BAR0 unassigned\n");
1323 if (!BAR1)
1324 dev_err(&oct->pci_dev->dev, "device BAR1 unassigned\n");
1325 return 1;
1326 }
1327
1328 if (octeon_map_pci_barx(oct, 0, 0))
1329 return 1;
1330
1331 if (octeon_map_pci_barx(oct, 1, MAX_BAR1_IOREMAP_SIZE)) {
1332 dev_err(&oct->pci_dev->dev, "%s CN23XX BAR1 map failed\n",
1333 __func__);
1334 octeon_unmap_pci_barx(oct, 0);
1335 return 1;
1336 }
1337
1338 if (cn23xx_get_pf_num(oct) != 0)
1339 return 1;
1340
1341 if (cn23xx_sriov_config(oct)) {
1342 octeon_unmap_pci_barx(oct, 0);
1343 octeon_unmap_pci_barx(oct, 1);
1344 return 1;
1345 }
1346
1347 octeon_write_csr64(oct, CN23XX_SLI_MAC_CREDIT_CNT, 0x3F802080802080ULL);
1348
1349 oct->fn_list.setup_iq_regs = cn23xx_setup_iq_regs;
1350 oct->fn_list.setup_oq_regs = cn23xx_setup_oq_regs;
1351 oct->fn_list.setup_mbox = cn23xx_setup_pf_mbox;
1352 oct->fn_list.free_mbox = cn23xx_free_pf_mbox;
1353
1354 oct->fn_list.process_interrupt_regs = cn23xx_interrupt_handler;
1355 oct->fn_list.msix_interrupt_handler = cn23xx_pf_msix_interrupt_handler;
1356
1357 oct->fn_list.soft_reset = cn23xx_pf_soft_reset;
1358 oct->fn_list.setup_device_regs = cn23xx_setup_pf_device_regs;
1359 oct->fn_list.update_iq_read_idx = cn23xx_update_read_index;
1360
1361 oct->fn_list.bar1_idx_setup = cn23xx_bar1_idx_setup;
1362 oct->fn_list.bar1_idx_write = cn23xx_bar1_idx_write;
1363 oct->fn_list.bar1_idx_read = cn23xx_bar1_idx_read;
1364
1365 oct->fn_list.enable_interrupt = cn23xx_enable_pf_interrupt;
1366 oct->fn_list.disable_interrupt = cn23xx_disable_pf_interrupt;
1367
1368 oct->fn_list.enable_io_queues = cn23xx_enable_io_queues;
1369 oct->fn_list.disable_io_queues = cn23xx_disable_io_queues;
1370
1371 cn23xx_setup_reg_address(oct);
1372
1373 oct->coproc_clock_rate = 1000000ULL * cn23xx_coprocessor_clock(oct);
1374
1375 return 0;
1376 }
1377
1378 int validate_cn23xx_pf_config_info(struct octeon_device *oct,
1379 struct octeon_config *conf23xx)
1380 {
1381 if (CFG_GET_IQ_MAX_Q(conf23xx) > CN23XX_MAX_INPUT_QUEUES) {
1382 dev_err(&oct->pci_dev->dev, "%s: Num IQ (%d) exceeds Max (%d)\n",
1383 __func__, CFG_GET_IQ_MAX_Q(conf23xx),
1384 CN23XX_MAX_INPUT_QUEUES);
1385 return 1;
1386 }
1387
1388 if (CFG_GET_OQ_MAX_Q(conf23xx) > CN23XX_MAX_OUTPUT_QUEUES) {
1389 dev_err(&oct->pci_dev->dev, "%s: Num OQ (%d) exceeds Max (%d)\n",
1390 __func__, CFG_GET_OQ_MAX_Q(conf23xx),
1391 CN23XX_MAX_OUTPUT_QUEUES);
1392 return 1;
1393 }
1394
1395 if (CFG_GET_IQ_INSTR_TYPE(conf23xx) != OCTEON_32BYTE_INSTR &&
1396 CFG_GET_IQ_INSTR_TYPE(conf23xx) != OCTEON_64BYTE_INSTR) {
1397 dev_err(&oct->pci_dev->dev, "%s: Invalid instr type for IQ\n",
1398 __func__);
1399 return 1;
1400 }
1401
1402 if (!CFG_GET_OQ_REFILL_THRESHOLD(conf23xx)) {
1403 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n",
1404 __func__);
1405 return 1;
1406 }
1407
1408 if (!(CFG_GET_OQ_INTR_TIME(conf23xx))) {
1409 dev_err(&oct->pci_dev->dev, "%s: Invalid parameter for OQ\n",
1410 __func__);
1411 return 1;
1412 }
1413
1414 return 0;
1415 }
1416
1417 void cn23xx_dump_iq_regs(struct octeon_device *oct)
1418 {
1419 u32 regval, q_no;
1420
1421 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_DOORBELL_0 [0x%x]: 0x%016llx\n",
1422 CN23XX_SLI_IQ_DOORBELL(0),
1423 CVM_CAST64(octeon_read_csr64
1424 (oct, CN23XX_SLI_IQ_DOORBELL(0))));
1425
1426 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_BASEADDR_0 [0x%x]: 0x%016llx\n",
1427 CN23XX_SLI_IQ_BASE_ADDR64(0),
1428 CVM_CAST64(octeon_read_csr64
1429 (oct, CN23XX_SLI_IQ_BASE_ADDR64(0))));
1430
1431 dev_dbg(&oct->pci_dev->dev, "SLI_IQ_FIFO_RSIZE_0 [0x%x]: 0x%016llx\n",
1432 CN23XX_SLI_IQ_SIZE(0),
1433 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_IQ_SIZE(0))));
1434
1435 dev_dbg(&oct->pci_dev->dev, "SLI_CTL_STATUS [0x%x]: 0x%016llx\n",
1436 CN23XX_SLI_CTL_STATUS,
1437 CVM_CAST64(octeon_read_csr64(oct, CN23XX_SLI_CTL_STATUS)));
1438
1439 for (q_no = 0; q_no < CN23XX_MAX_INPUT_QUEUES; q_no++) {
1440 dev_dbg(&oct->pci_dev->dev, "SLI_PKT[%d]_INPUT_CTL [0x%x]: 0x%016llx\n",
1441 q_no, CN23XX_SLI_IQ_PKT_CONTROL64(q_no),
1442 CVM_CAST64(octeon_read_csr64
1443 (oct, CN23XX_SLI_IQ_PKT_CONTROL64(q_no))));
1444 }
1445
1446 pci_read_config_dword(oct->pci_dev, CN23XX_CONFIG_PCIE_DEVCTL, &regval);
1447 dev_dbg(&oct->pci_dev->dev, "Config DevCtl [0x%x]: 0x%08x\n",
1448 CN23XX_CONFIG_PCIE_DEVCTL, regval);
1449
1450 dev_dbg(&oct->pci_dev->dev, "SLI_PRT[%d]_CFG [0x%llx]: 0x%016llx\n",
1451 oct->pcie_port, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port),
1452 CVM_CAST64(lio_pci_readq(
1453 oct, CN23XX_DPI_SLI_PRTX_CFG(oct->pcie_port))));
1454
1455 dev_dbg(&oct->pci_dev->dev, "SLI_S2M_PORT[%d]_CTL [0x%x]: 0x%016llx\n",
1456 oct->pcie_port, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port),
1457 CVM_CAST64(octeon_read_csr64(
1458 oct, CN23XX_SLI_S2M_PORTX_CTL(oct->pcie_port))));
1459 }
1460
1461 int cn23xx_fw_loaded(struct octeon_device *oct)
1462 {
1463 u64 val;
1464
1465 /* If there's more than one active PF on this NIC, then that
1466 * implies that the NIC firmware is loaded and running. This check
1467 * prevents a rare false negative that might occur if we only relied
1468 * on checking the SCR2_BIT_FW_LOADED flag. The false negative would
1469 * happen if the PF driver sees SCR2_BIT_FW_LOADED as cleared even
1470 * though the firmware was already loaded but still booting and has yet
1471 * to set SCR2_BIT_FW_LOADED.
1472 */
1473 if (atomic_read(oct->adapter_refcount) > 1)
1474 return 1;
1475
1476 val = octeon_read_csr64(oct, CN23XX_SLI_SCRATCH2);
1477 return (val >> SCR2_BIT_FW_LOADED) & 1ULL;
1478 }
1479
1480 void cn23xx_tell_vf_its_macaddr_changed(struct octeon_device *oct, int vfidx,
1481 u8 *mac)
1482 {
1483 if (oct->sriov_info.vf_drv_loaded_mask & BIT_ULL(vfidx)) {
1484 struct octeon_mbox_cmd mbox_cmd;
1485
1486 mbox_cmd.msg.u64 = 0;
1487 mbox_cmd.msg.s.type = OCTEON_MBOX_REQUEST;
1488 mbox_cmd.msg.s.resp_needed = 0;
1489 mbox_cmd.msg.s.cmd = OCTEON_PF_CHANGED_VF_MACADDR;
1490 mbox_cmd.msg.s.len = 1;
1491 mbox_cmd.recv_len = 0;
1492 mbox_cmd.recv_status = 0;
1493 mbox_cmd.fn = NULL;
1494 mbox_cmd.fn_arg = 0;
1495 ether_addr_copy(mbox_cmd.msg.s.params, mac);
1496 mbox_cmd.q_no = vfidx * oct->sriov_info.rings_per_vf;
1497 octeon_mbox_write(oct, &mbox_cmd);
1498 }
1499 }
Linux with added FPC-III support