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staging: rtl8188eu: Replace function name in string with __func__
[linux/fpc-iii.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
blobe0b72bf428f70f7f8252ed5653475da4b949a657
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/if_vlan.h>
23 #include <linux/reset.h>
24 #include <linux/tcp.h>
25 #include <linux/interrupt.h>
26 #include <linux/pinctrl/devinfo.h>
27
28 #include "mtk_eth_soc.h"
29
30 static int mtk_msg_level = -1;
31 module_param_named(msg_level, mtk_msg_level, int, 0);
32 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
33
34 #define MTK_ETHTOOL_STAT(x) { #x, \
35 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
36
37 /* strings used by ethtool */
38 static const struct mtk_ethtool_stats {
39 char str[ETH_GSTRING_LEN];
40 u32 offset;
41 } mtk_ethtool_stats[] = {
42 MTK_ETHTOOL_STAT(tx_bytes),
43 MTK_ETHTOOL_STAT(tx_packets),
44 MTK_ETHTOOL_STAT(tx_skip),
45 MTK_ETHTOOL_STAT(tx_collisions),
46 MTK_ETHTOOL_STAT(rx_bytes),
47 MTK_ETHTOOL_STAT(rx_packets),
48 MTK_ETHTOOL_STAT(rx_overflow),
49 MTK_ETHTOOL_STAT(rx_fcs_errors),
50 MTK_ETHTOOL_STAT(rx_short_errors),
51 MTK_ETHTOOL_STAT(rx_long_errors),
52 MTK_ETHTOOL_STAT(rx_checksum_errors),
53 MTK_ETHTOOL_STAT(rx_flow_control_packets),
54 };
55
56 static const char * const mtk_clks_source_name[] = {
57 "ethif", "esw", "gp0", "gp1", "gp2", "trgpll", "sgmii_tx250m",
58 "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll"
59 };
60
61 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
62 {
63 __raw_writel(val, eth->base + reg);
64 }
65
66 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
67 {
68 return __raw_readl(eth->base + reg);
69 }
70
71 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
72 {
73 unsigned long t_start = jiffies;
74
75 while (1) {
76 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
77 return 0;
78 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
79 break;
80 usleep_range(10, 20);
81 }
82
83 dev_err(eth->dev, "mdio: MDIO timeout\n");
84 return -1;
85 }
86
87 static u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
88 u32 phy_register, u32 write_data)
89 {
90 if (mtk_mdio_busy_wait(eth))
91 return -1;
92
93 write_data &= 0xffff;
94
95 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
96 (phy_register << PHY_IAC_REG_SHIFT) |
97 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
98 MTK_PHY_IAC);
99
100 if (mtk_mdio_busy_wait(eth))
101 return -1;
102
103 return 0;
104 }
105
106 static u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
107 {
108 u32 d;
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
114 (phy_reg << PHY_IAC_REG_SHIFT) |
115 (phy_addr << PHY_IAC_ADDR_SHIFT),
116 MTK_PHY_IAC);
117
118 if (mtk_mdio_busy_wait(eth))
119 return 0xffff;
120
121 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
122
123 return d;
124 }
125
126 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
127 int phy_reg, u16 val)
128 {
129 struct mtk_eth *eth = bus->priv;
130
131 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
132 }
133
134 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
135 {
136 struct mtk_eth *eth = bus->priv;
137
138 return _mtk_mdio_read(eth, phy_addr, phy_reg);
139 }
140
141 static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth, int speed)
142 {
143 u32 val;
144 int ret;
145
146 val = (speed == SPEED_1000) ?
147 INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
148 mtk_w32(eth, val, INTF_MODE);
149
150 regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
151 ETHSYS_TRGMII_CLK_SEL362_5,
152 ETHSYS_TRGMII_CLK_SEL362_5);
153
154 val = (speed == SPEED_1000) ? 250000000 : 500000000;
155 ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
156 if (ret)
157 dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
158
159 val = (speed == SPEED_1000) ?
160 RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
161 mtk_w32(eth, val, TRGMII_RCK_CTRL);
162
163 val = (speed == SPEED_1000) ?
164 TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
165 mtk_w32(eth, val, TRGMII_TCK_CTRL);
166 }
167
168 static void mtk_gmac_sgmii_hw_setup(struct mtk_eth *eth, int mac_id)
169 {
170 u32 val;
171
172 /* Setup the link timer and QPHY power up inside SGMIISYS */
173 regmap_write(eth->sgmiisys, SGMSYS_PCS_LINK_TIMER,
174 SGMII_LINK_TIMER_DEFAULT);
175
176 regmap_read(eth->sgmiisys, SGMSYS_SGMII_MODE, &val);
177 val |= SGMII_REMOTE_FAULT_DIS;
178 regmap_write(eth->sgmiisys, SGMSYS_SGMII_MODE, val);
179
180 regmap_read(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, &val);
181 val |= SGMII_AN_RESTART;
182 regmap_write(eth->sgmiisys, SGMSYS_PCS_CONTROL_1, val);
183
184 regmap_read(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
185 val &= ~SGMII_PHYA_PWD;
186 regmap_write(eth->sgmiisys, SGMSYS_QPHY_PWR_STATE_CTRL, val);
187
188 /* Determine MUX for which GMAC uses the SGMII interface */
189 if (MTK_HAS_CAPS(eth->soc->caps, MTK_DUAL_GMAC_SHARED_SGMII)) {
190 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
191 val &= ~SYSCFG0_SGMII_MASK;
192 val |= !mac_id ? SYSCFG0_SGMII_GMAC1 : SYSCFG0_SGMII_GMAC2;
193 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
194
195 dev_info(eth->dev, "setup shared sgmii for gmac=%d\n",
196 mac_id);
197 }
198
199 /* Setup the GMAC1 going through SGMII path when SoC also support
200 * ESW on GMAC1
201 */
202 if (MTK_HAS_CAPS(eth->soc->caps, MTK_GMAC1_ESW | MTK_GMAC1_SGMII) &&
203 !mac_id) {
204 mtk_w32(eth, 0, MTK_MAC_MISC);
205 dev_info(eth->dev, "setup gmac1 going through sgmii");
206 }
207 }
208
209 static void mtk_phy_link_adjust(struct net_device *dev)
210 {
211 struct mtk_mac *mac = netdev_priv(dev);
212 u16 lcl_adv = 0, rmt_adv = 0;
213 u8 flowctrl;
214 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
215 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
216 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
217 MAC_MCR_BACKPR_EN;
218
219 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
220 return;
221
222 switch (dev->phydev->speed) {
223 case SPEED_1000:
224 mcr |= MAC_MCR_SPEED_1000;
225 break;
226 case SPEED_100:
227 mcr |= MAC_MCR_SPEED_100;
228 break;
229 };
230
231 if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_GMAC1_TRGMII) &&
232 !mac->id && !mac->trgmii)
233 mtk_gmac0_rgmii_adjust(mac->hw, dev->phydev->speed);
234
235 if (dev->phydev->link)
236 mcr |= MAC_MCR_FORCE_LINK;
237
238 if (dev->phydev->duplex) {
239 mcr |= MAC_MCR_FORCE_DPX;
240
241 if (dev->phydev->pause)
242 rmt_adv = LPA_PAUSE_CAP;
243 if (dev->phydev->asym_pause)
244 rmt_adv |= LPA_PAUSE_ASYM;
245
246 if (dev->phydev->advertising & ADVERTISED_Pause)
247 lcl_adv |= ADVERTISE_PAUSE_CAP;
248 if (dev->phydev->advertising & ADVERTISED_Asym_Pause)
249 lcl_adv |= ADVERTISE_PAUSE_ASYM;
250
251 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
252
253 if (flowctrl & FLOW_CTRL_TX)
254 mcr |= MAC_MCR_FORCE_TX_FC;
255 if (flowctrl & FLOW_CTRL_RX)
256 mcr |= MAC_MCR_FORCE_RX_FC;
257
258 netif_dbg(mac->hw, link, dev, "rx pause %s, tx pause %s\n",
259 flowctrl & FLOW_CTRL_RX ? "enabled" : "disabled",
260 flowctrl & FLOW_CTRL_TX ? "enabled" : "disabled");
261 }
262
263 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
264
265 if (dev->phydev->link)
266 netif_carrier_on(dev);
267 else
268 netif_carrier_off(dev);
269
270 if (!of_phy_is_fixed_link(mac->of_node))
271 phy_print_status(dev->phydev);
272 }
273
274 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
275 struct device_node *phy_node)
276 {
277 struct phy_device *phydev;
278 int phy_mode;
279
280 phy_mode = of_get_phy_mode(phy_node);
281 if (phy_mode < 0) {
282 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
283 return -EINVAL;
284 }
285
286 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
287 mtk_phy_link_adjust, 0, phy_mode);
288 if (!phydev) {
289 dev_err(eth->dev, "could not connect to PHY\n");
290 return -ENODEV;
291 }
292
293 dev_info(eth->dev,
294 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
295 mac->id, phydev_name(phydev), phydev->phy_id,
296 phydev->drv->name);
297
298 return 0;
299 }
300
301 static int mtk_phy_connect(struct net_device *dev)
302 {
303 struct mtk_mac *mac = netdev_priv(dev);
304 struct mtk_eth *eth;
305 struct device_node *np;
306 u32 val;
307
308 eth = mac->hw;
309 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
310 if (!np && of_phy_is_fixed_link(mac->of_node))
311 if (!of_phy_register_fixed_link(mac->of_node))
312 np = of_node_get(mac->of_node);
313 if (!np)
314 return -ENODEV;
315
316 mac->ge_mode = 0;
317 switch (of_get_phy_mode(np)) {
318 case PHY_INTERFACE_MODE_TRGMII:
319 mac->trgmii = true;
320 case PHY_INTERFACE_MODE_RGMII_TXID:
321 case PHY_INTERFACE_MODE_RGMII_RXID:
322 case PHY_INTERFACE_MODE_RGMII_ID:
323 case PHY_INTERFACE_MODE_RGMII:
324 break;
325 case PHY_INTERFACE_MODE_SGMII:
326 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII))
327 mtk_gmac_sgmii_hw_setup(eth, mac->id);
328 break;
329 case PHY_INTERFACE_MODE_MII:
330 mac->ge_mode = 1;
331 break;
332 case PHY_INTERFACE_MODE_REVMII:
333 mac->ge_mode = 2;
334 break;
335 case PHY_INTERFACE_MODE_RMII:
336 if (!mac->id)
337 goto err_phy;
338 mac->ge_mode = 3;
339 break;
340 default:
341 goto err_phy;
342 }
343
344 /* put the gmac into the right mode */
345 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
346 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
347 val |= SYSCFG0_GE_MODE(mac->ge_mode, mac->id);
348 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
349
350 /* couple phydev to net_device */
351 if (mtk_phy_connect_node(eth, mac, np))
352 goto err_phy;
353
354 dev->phydev->autoneg = AUTONEG_ENABLE;
355 dev->phydev->speed = 0;
356 dev->phydev->duplex = 0;
357
358 if (of_phy_is_fixed_link(mac->of_node))
359 dev->phydev->supported |=
360 SUPPORTED_Pause | SUPPORTED_Asym_Pause;
361
362 dev->phydev->supported &= PHY_GBIT_FEATURES | SUPPORTED_Pause |
363 SUPPORTED_Asym_Pause;
364 dev->phydev->advertising = dev->phydev->supported |
365 ADVERTISED_Autoneg;
366 phy_start_aneg(dev->phydev);
367
368 of_node_put(np);
369
370 return 0;
371
372 err_phy:
373 if (of_phy_is_fixed_link(mac->of_node))
374 of_phy_deregister_fixed_link(mac->of_node);
375 of_node_put(np);
376 dev_err(eth->dev, "%s: invalid phy\n", __func__);
377 return -EINVAL;
378 }
379
380 static int mtk_mdio_init(struct mtk_eth *eth)
381 {
382 struct device_node *mii_np;
383 int ret;
384
385 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
386 if (!mii_np) {
387 dev_err(eth->dev, "no %s child node found", "mdio-bus");
388 return -ENODEV;
389 }
390
391 if (!of_device_is_available(mii_np)) {
392 ret = -ENODEV;
393 goto err_put_node;
394 }
395
396 eth->mii_bus = devm_mdiobus_alloc(eth->dev);
397 if (!eth->mii_bus) {
398 ret = -ENOMEM;
399 goto err_put_node;
400 }
401
402 eth->mii_bus->name = "mdio";
403 eth->mii_bus->read = mtk_mdio_read;
404 eth->mii_bus->write = mtk_mdio_write;
405 eth->mii_bus->priv = eth;
406 eth->mii_bus->parent = eth->dev;
407
408 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
409 ret = of_mdiobus_register(eth->mii_bus, mii_np);
410
411 err_put_node:
412 of_node_put(mii_np);
413 return ret;
414 }
415
416 static void mtk_mdio_cleanup(struct mtk_eth *eth)
417 {
418 if (!eth->mii_bus)
419 return;
420
421 mdiobus_unregister(eth->mii_bus);
422 }
423
424 static inline void mtk_tx_irq_disable(struct mtk_eth *eth, u32 mask)
425 {
426 unsigned long flags;
427 u32 val;
428
429 spin_lock_irqsave(&eth->tx_irq_lock, flags);
430 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
431 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
432 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
433 }
434
435 static inline void mtk_tx_irq_enable(struct mtk_eth *eth, u32 mask)
436 {
437 unsigned long flags;
438 u32 val;
439
440 spin_lock_irqsave(&eth->tx_irq_lock, flags);
441 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
442 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
443 spin_unlock_irqrestore(&eth->tx_irq_lock, flags);
444 }
445
446 static inline void mtk_rx_irq_disable(struct mtk_eth *eth, u32 mask)
447 {
448 unsigned long flags;
449 u32 val;
450
451 spin_lock_irqsave(&eth->rx_irq_lock, flags);
452 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
453 mtk_w32(eth, val & ~mask, MTK_PDMA_INT_MASK);
454 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
455 }
456
457 static inline void mtk_rx_irq_enable(struct mtk_eth *eth, u32 mask)
458 {
459 unsigned long flags;
460 u32 val;
461
462 spin_lock_irqsave(&eth->rx_irq_lock, flags);
463 val = mtk_r32(eth, MTK_PDMA_INT_MASK);
464 mtk_w32(eth, val | mask, MTK_PDMA_INT_MASK);
465 spin_unlock_irqrestore(&eth->rx_irq_lock, flags);
466 }
467
468 static int mtk_set_mac_address(struct net_device *dev, void *p)
469 {
470 int ret = eth_mac_addr(dev, p);
471 struct mtk_mac *mac = netdev_priv(dev);
472 const char *macaddr = dev->dev_addr;
473
474 if (ret)
475 return ret;
476
477 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
478 return -EBUSY;
479
480 spin_lock_bh(&mac->hw->page_lock);
481 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
482 MTK_GDMA_MAC_ADRH(mac->id));
483 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
484 (macaddr[4] << 8) | macaddr[5],
485 MTK_GDMA_MAC_ADRL(mac->id));
486 spin_unlock_bh(&mac->hw->page_lock);
487
488 return 0;
489 }
490
491 void mtk_stats_update_mac(struct mtk_mac *mac)
492 {
493 struct mtk_hw_stats *hw_stats = mac->hw_stats;
494 unsigned int base = MTK_GDM1_TX_GBCNT;
495 u64 stats;
496
497 base += hw_stats->reg_offset;
498
499 u64_stats_update_begin(&hw_stats->syncp);
500
501 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
502 stats = mtk_r32(mac->hw, base + 0x04);
503 if (stats)
504 hw_stats->rx_bytes += (stats << 32);
505 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
506 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
507 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
508 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
509 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
510 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
511 hw_stats->rx_flow_control_packets +=
512 mtk_r32(mac->hw, base + 0x24);
513 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
514 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
515 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
516 stats = mtk_r32(mac->hw, base + 0x34);
517 if (stats)
518 hw_stats->tx_bytes += (stats << 32);
519 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
520 u64_stats_update_end(&hw_stats->syncp);
521 }
522
523 static void mtk_stats_update(struct mtk_eth *eth)
524 {
525 int i;
526
527 for (i = 0; i < MTK_MAC_COUNT; i++) {
528 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
529 continue;
530 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
531 mtk_stats_update_mac(eth->mac[i]);
532 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
533 }
534 }
535 }
536
537 static void mtk_get_stats64(struct net_device *dev,
538 struct rtnl_link_stats64 *storage)
539 {
540 struct mtk_mac *mac = netdev_priv(dev);
541 struct mtk_hw_stats *hw_stats = mac->hw_stats;
542 unsigned int start;
543
544 if (netif_running(dev) && netif_device_present(dev)) {
545 if (spin_trylock_bh(&hw_stats->stats_lock)) {
546 mtk_stats_update_mac(mac);
547 spin_unlock_bh(&hw_stats->stats_lock);
548 }
549 }
550
551 do {
552 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
553 storage->rx_packets = hw_stats->rx_packets;
554 storage->tx_packets = hw_stats->tx_packets;
555 storage->rx_bytes = hw_stats->rx_bytes;
556 storage->tx_bytes = hw_stats->tx_bytes;
557 storage->collisions = hw_stats->tx_collisions;
558 storage->rx_length_errors = hw_stats->rx_short_errors +
559 hw_stats->rx_long_errors;
560 storage->rx_over_errors = hw_stats->rx_overflow;
561 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
562 storage->rx_errors = hw_stats->rx_checksum_errors;
563 storage->tx_aborted_errors = hw_stats->tx_skip;
564 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
565
566 storage->tx_errors = dev->stats.tx_errors;
567 storage->rx_dropped = dev->stats.rx_dropped;
568 storage->tx_dropped = dev->stats.tx_dropped;
569 }
570
571 static inline int mtk_max_frag_size(int mtu)
572 {
573 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
574 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
575 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
576
577 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
578 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
579 }
580
581 static inline int mtk_max_buf_size(int frag_size)
582 {
583 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
584 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
585
586 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
587
588 return buf_size;
589 }
590
591 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
592 struct mtk_rx_dma *dma_rxd)
593 {
594 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
595 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
596 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
597 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
598 }
599
600 /* the qdma core needs scratch memory to be setup */
601 static int mtk_init_fq_dma(struct mtk_eth *eth)
602 {
603 dma_addr_t phy_ring_tail;
604 int cnt = MTK_DMA_SIZE;
605 dma_addr_t dma_addr;
606 int i;
607
608 eth->scratch_ring = dma_alloc_coherent(eth->dev,
609 cnt * sizeof(struct mtk_tx_dma),
610 &eth->phy_scratch_ring,
611 GFP_ATOMIC | __GFP_ZERO);
612 if (unlikely(!eth->scratch_ring))
613 return -ENOMEM;
614
615 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
616 GFP_KERNEL);
617 if (unlikely(!eth->scratch_head))
618 return -ENOMEM;
619
620 dma_addr = dma_map_single(eth->dev,
621 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
622 DMA_FROM_DEVICE);
623 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
624 return -ENOMEM;
625
626 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
627 phy_ring_tail = eth->phy_scratch_ring +
628 (sizeof(struct mtk_tx_dma) * (cnt - 1));
629
630 for (i = 0; i < cnt; i++) {
631 eth->scratch_ring[i].txd1 =
632 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
633 if (i < cnt - 1)
634 eth->scratch_ring[i].txd2 = (eth->phy_scratch_ring +
635 ((i + 1) * sizeof(struct mtk_tx_dma)));
636 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
637 }
638
639 mtk_w32(eth, eth->phy_scratch_ring, MTK_QDMA_FQ_HEAD);
640 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
641 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
642 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
643
644 return 0;
645 }
646
647 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
648 {
649 void *ret = ring->dma;
650
651 return ret + (desc - ring->phys);
652 }
653
654 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
655 struct mtk_tx_dma *txd)
656 {
657 int idx = txd - ring->dma;
658
659 return &ring->buf[idx];
660 }
661
662 static void mtk_tx_unmap(struct mtk_eth *eth, struct mtk_tx_buf *tx_buf)
663 {
664 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
665 dma_unmap_single(eth->dev,
666 dma_unmap_addr(tx_buf, dma_addr0),
667 dma_unmap_len(tx_buf, dma_len0),
668 DMA_TO_DEVICE);
669 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
670 dma_unmap_page(eth->dev,
671 dma_unmap_addr(tx_buf, dma_addr0),
672 dma_unmap_len(tx_buf, dma_len0),
673 DMA_TO_DEVICE);
674 }
675 tx_buf->flags = 0;
676 if (tx_buf->skb &&
677 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
678 dev_kfree_skb_any(tx_buf->skb);
679 tx_buf->skb = NULL;
680 }
681
682 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
683 int tx_num, struct mtk_tx_ring *ring, bool gso)
684 {
685 struct mtk_mac *mac = netdev_priv(dev);
686 struct mtk_eth *eth = mac->hw;
687 struct mtk_tx_dma *itxd, *txd;
688 struct mtk_tx_buf *itx_buf, *tx_buf;
689 dma_addr_t mapped_addr;
690 unsigned int nr_frags;
691 int i, n_desc = 1;
692 u32 txd4 = 0, fport;
693
694 itxd = ring->next_free;
695 if (itxd == ring->last_free)
696 return -ENOMEM;
697
698 /* set the forward port */
699 fport = (mac->id + 1) << TX_DMA_FPORT_SHIFT;
700 txd4 |= fport;
701
702 itx_buf = mtk_desc_to_tx_buf(ring, itxd);
703 memset(itx_buf, 0, sizeof(*itx_buf));
704
705 if (gso)
706 txd4 |= TX_DMA_TSO;
707
708 /* TX Checksum offload */
709 if (skb->ip_summed == CHECKSUM_PARTIAL)
710 txd4 |= TX_DMA_CHKSUM;
711
712 /* VLAN header offload */
713 if (skb_vlan_tag_present(skb))
714 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
715
716 mapped_addr = dma_map_single(eth->dev, skb->data,
717 skb_headlen(skb), DMA_TO_DEVICE);
718 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
719 return -ENOMEM;
720
721 WRITE_ONCE(itxd->txd1, mapped_addr);
722 itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
723 itx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
724 MTK_TX_FLAGS_FPORT1;
725 dma_unmap_addr_set(itx_buf, dma_addr0, mapped_addr);
726 dma_unmap_len_set(itx_buf, dma_len0, skb_headlen(skb));
727
728 /* TX SG offload */
729 txd = itxd;
730 nr_frags = skb_shinfo(skb)->nr_frags;
731 for (i = 0; i < nr_frags; i++) {
732 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
733 unsigned int offset = 0;
734 int frag_size = skb_frag_size(frag);
735
736 while (frag_size) {
737 bool last_frag = false;
738 unsigned int frag_map_size;
739
740 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
741 if (txd == ring->last_free)
742 goto err_dma;
743
744 n_desc++;
745 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
746 mapped_addr = skb_frag_dma_map(eth->dev, frag, offset,
747 frag_map_size,
748 DMA_TO_DEVICE);
749 if (unlikely(dma_mapping_error(eth->dev, mapped_addr)))
750 goto err_dma;
751
752 if (i == nr_frags - 1 &&
753 (frag_size - frag_map_size) == 0)
754 last_frag = true;
755
756 WRITE_ONCE(txd->txd1, mapped_addr);
757 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
758 TX_DMA_PLEN0(frag_map_size) |
759 last_frag * TX_DMA_LS0));
760 WRITE_ONCE(txd->txd4, fport);
761
762 tx_buf = mtk_desc_to_tx_buf(ring, txd);
763 memset(tx_buf, 0, sizeof(*tx_buf));
764 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
765 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
766 tx_buf->flags |= (!mac->id) ? MTK_TX_FLAGS_FPORT0 :
767 MTK_TX_FLAGS_FPORT1;
768
769 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
770 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
771 frag_size -= frag_map_size;
772 offset += frag_map_size;
773 }
774 }
775
776 /* store skb to cleanup */
777 itx_buf->skb = skb;
778
779 WRITE_ONCE(itxd->txd4, txd4);
780 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
781 (!nr_frags * TX_DMA_LS0)));
782
783 netdev_sent_queue(dev, skb->len);
784 skb_tx_timestamp(skb);
785
786 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
787 atomic_sub(n_desc, &ring->free_count);
788
789 /* make sure that all changes to the dma ring are flushed before we
790 * continue
791 */
792 wmb();
793
794 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
795 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
796
797 return 0;
798
799 err_dma:
800 do {
801 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
802
803 /* unmap dma */
804 mtk_tx_unmap(eth, tx_buf);
805
806 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
807 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
808 } while (itxd != txd);
809
810 return -ENOMEM;
811 }
812
813 static inline int mtk_cal_txd_req(struct sk_buff *skb)
814 {
815 int i, nfrags;
816 struct skb_frag_struct *frag;
817
818 nfrags = 1;
819 if (skb_is_gso(skb)) {
820 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
821 frag = &skb_shinfo(skb)->frags[i];
822 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
823 }
824 } else {
825 nfrags += skb_shinfo(skb)->nr_frags;
826 }
827
828 return nfrags;
829 }
830
831 static int mtk_queue_stopped(struct mtk_eth *eth)
832 {
833 int i;
834
835 for (i = 0; i < MTK_MAC_COUNT; i++) {
836 if (!eth->netdev[i])
837 continue;
838 if (netif_queue_stopped(eth->netdev[i]))
839 return 1;
840 }
841
842 return 0;
843 }
844
845 static void mtk_wake_queue(struct mtk_eth *eth)
846 {
847 int i;
848
849 for (i = 0; i < MTK_MAC_COUNT; i++) {
850 if (!eth->netdev[i])
851 continue;
852 netif_wake_queue(eth->netdev[i]);
853 }
854 }
855
856 static void mtk_stop_queue(struct mtk_eth *eth)
857 {
858 int i;
859
860 for (i = 0; i < MTK_MAC_COUNT; i++) {
861 if (!eth->netdev[i])
862 continue;
863 netif_stop_queue(eth->netdev[i]);
864 }
865 }
866
867 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
868 {
869 struct mtk_mac *mac = netdev_priv(dev);
870 struct mtk_eth *eth = mac->hw;
871 struct mtk_tx_ring *ring = &eth->tx_ring;
872 struct net_device_stats *stats = &dev->stats;
873 bool gso = false;
874 int tx_num;
875
876 /* normally we can rely on the stack not calling this more than once,
877 * however we have 2 queues running on the same ring so we need to lock
878 * the ring access
879 */
880 spin_lock(&eth->page_lock);
881
882 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
883 goto drop;
884
885 tx_num = mtk_cal_txd_req(skb);
886 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
887 mtk_stop_queue(eth);
888 netif_err(eth, tx_queued, dev,
889 "Tx Ring full when queue awake!\n");
890 spin_unlock(&eth->page_lock);
891 return NETDEV_TX_BUSY;
892 }
893
894 /* TSO: fill MSS info in tcp checksum field */
895 if (skb_is_gso(skb)) {
896 if (skb_cow_head(skb, 0)) {
897 netif_warn(eth, tx_err, dev,
898 "GSO expand head fail.\n");
899 goto drop;
900 }
901
902 if (skb_shinfo(skb)->gso_type &
903 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
904 gso = true;
905 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
906 }
907 }
908
909 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
910 goto drop;
911
912 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
913 mtk_stop_queue(eth);
914
915 spin_unlock(&eth->page_lock);
916
917 return NETDEV_TX_OK;
918
919 drop:
920 spin_unlock(&eth->page_lock);
921 stats->tx_dropped++;
922 dev_kfree_skb_any(skb);
923 return NETDEV_TX_OK;
924 }
925
926 static struct mtk_rx_ring *mtk_get_rx_ring(struct mtk_eth *eth)
927 {
928 int i;
929 struct mtk_rx_ring *ring;
930 int idx;
931
932 if (!eth->hwlro)
933 return &eth->rx_ring[0];
934
935 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
936 ring = &eth->rx_ring[i];
937 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
938 if (ring->dma[idx].rxd2 & RX_DMA_DONE) {
939 ring->calc_idx_update = true;
940 return ring;
941 }
942 }
943
944 return NULL;
945 }
946
947 static void mtk_update_rx_cpu_idx(struct mtk_eth *eth)
948 {
949 struct mtk_rx_ring *ring;
950 int i;
951
952 if (!eth->hwlro) {
953 ring = &eth->rx_ring[0];
954 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
955 } else {
956 for (i = 0; i < MTK_MAX_RX_RING_NUM; i++) {
957 ring = &eth->rx_ring[i];
958 if (ring->calc_idx_update) {
959 ring->calc_idx_update = false;
960 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg);
961 }
962 }
963 }
964 }
965
966 static int mtk_poll_rx(struct napi_struct *napi, int budget,
967 struct mtk_eth *eth)
968 {
969 struct mtk_rx_ring *ring;
970 int idx;
971 struct sk_buff *skb;
972 u8 *data, *new_data;
973 struct mtk_rx_dma *rxd, trxd;
974 int done = 0;
975
976 while (done < budget) {
977 struct net_device *netdev;
978 unsigned int pktlen;
979 dma_addr_t dma_addr;
980 int mac = 0;
981
982 ring = mtk_get_rx_ring(eth);
983 if (unlikely(!ring))
984 goto rx_done;
985
986 idx = NEXT_RX_DESP_IDX(ring->calc_idx, ring->dma_size);
987 rxd = &ring->dma[idx];
988 data = ring->data[idx];
989
990 mtk_rx_get_desc(&trxd, rxd);
991 if (!(trxd.rxd2 & RX_DMA_DONE))
992 break;
993
994 /* find out which mac the packet come from. values start at 1 */
995 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
996 RX_DMA_FPORT_MASK;
997 mac--;
998
999 if (unlikely(mac < 0 || mac >= MTK_MAC_COUNT ||
1000 !eth->netdev[mac]))
1001 goto release_desc;
1002
1003 netdev = eth->netdev[mac];
1004
1005 if (unlikely(test_bit(MTK_RESETTING, &eth->state)))
1006 goto release_desc;
1007
1008 /* alloc new buffer */
1009 new_data = napi_alloc_frag(ring->frag_size);
1010 if (unlikely(!new_data)) {
1011 netdev->stats.rx_dropped++;
1012 goto release_desc;
1013 }
1014 dma_addr = dma_map_single(eth->dev,
1015 new_data + NET_SKB_PAD,
1016 ring->buf_size,
1017 DMA_FROM_DEVICE);
1018 if (unlikely(dma_mapping_error(eth->dev, dma_addr))) {
1019 skb_free_frag(new_data);
1020 netdev->stats.rx_dropped++;
1021 goto release_desc;
1022 }
1023
1024 /* receive data */
1025 skb = build_skb(data, ring->frag_size);
1026 if (unlikely(!skb)) {
1027 skb_free_frag(new_data);
1028 netdev->stats.rx_dropped++;
1029 goto release_desc;
1030 }
1031 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
1032
1033 dma_unmap_single(eth->dev, trxd.rxd1,
1034 ring->buf_size, DMA_FROM_DEVICE);
1035 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
1036 skb->dev = netdev;
1037 skb_put(skb, pktlen);
1038 if (trxd.rxd4 & RX_DMA_L4_VALID)
1039 skb->ip_summed = CHECKSUM_UNNECESSARY;
1040 else
1041 skb_checksum_none_assert(skb);
1042 skb->protocol = eth_type_trans(skb, netdev);
1043
1044 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
1045 RX_DMA_VID(trxd.rxd3))
1046 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1047 RX_DMA_VID(trxd.rxd3));
1048 skb_record_rx_queue(skb, 0);
1049 napi_gro_receive(napi, skb);
1050
1051 ring->data[idx] = new_data;
1052 rxd->rxd1 = (unsigned int)dma_addr;
1053
1054 release_desc:
1055 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
1056
1057 ring->calc_idx = idx;
1058
1059 done++;
1060 }
1061
1062 rx_done:
1063 if (done) {
1064 /* make sure that all changes to the dma ring are flushed before
1065 * we continue
1066 */
1067 wmb();
1068 mtk_update_rx_cpu_idx(eth);
1069 }
1070
1071 return done;
1072 }
1073
1074 static int mtk_poll_tx(struct mtk_eth *eth, int budget)
1075 {
1076 struct mtk_tx_ring *ring = &eth->tx_ring;
1077 struct mtk_tx_dma *desc;
1078 struct sk_buff *skb;
1079 struct mtk_tx_buf *tx_buf;
1080 unsigned int done[MTK_MAX_DEVS];
1081 unsigned int bytes[MTK_MAX_DEVS];
1082 u32 cpu, dma;
1083 int total = 0, i;
1084
1085 memset(done, 0, sizeof(done));
1086 memset(bytes, 0, sizeof(bytes));
1087
1088 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
1089 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
1090
1091 desc = mtk_qdma_phys_to_virt(ring, cpu);
1092
1093 while ((cpu != dma) && budget) {
1094 u32 next_cpu = desc->txd2;
1095 int mac = 0;
1096
1097 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
1098 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
1099 break;
1100
1101 tx_buf = mtk_desc_to_tx_buf(ring, desc);
1102 if (tx_buf->flags & MTK_TX_FLAGS_FPORT1)
1103 mac = 1;
1104
1105 skb = tx_buf->skb;
1106 if (!skb)
1107 break;
1108
1109 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
1110 bytes[mac] += skb->len;
1111 done[mac]++;
1112 budget--;
1113 }
1114 mtk_tx_unmap(eth, tx_buf);
1115
1116 ring->last_free = desc;
1117 atomic_inc(&ring->free_count);
1118
1119 cpu = next_cpu;
1120 }
1121
1122 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
1123
1124 for (i = 0; i < MTK_MAC_COUNT; i++) {
1125 if (!eth->netdev[i] || !done[i])
1126 continue;
1127 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
1128 total += done[i];
1129 }
1130
1131 if (mtk_queue_stopped(eth) &&
1132 (atomic_read(&ring->free_count) > ring->thresh))
1133 mtk_wake_queue(eth);
1134
1135 return total;
1136 }
1137
1138 static void mtk_handle_status_irq(struct mtk_eth *eth)
1139 {
1140 u32 status2 = mtk_r32(eth, MTK_INT_STATUS2);
1141
1142 if (unlikely(status2 & (MTK_GDM1_AF | MTK_GDM2_AF))) {
1143 mtk_stats_update(eth);
1144 mtk_w32(eth, (MTK_GDM1_AF | MTK_GDM2_AF),
1145 MTK_INT_STATUS2);
1146 }
1147 }
1148
1149 static int mtk_napi_tx(struct napi_struct *napi, int budget)
1150 {
1151 struct mtk_eth *eth = container_of(napi, struct mtk_eth, tx_napi);
1152 u32 status, mask;
1153 int tx_done = 0;
1154
1155 mtk_handle_status_irq(eth);
1156 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
1157 tx_done = mtk_poll_tx(eth, budget);
1158
1159 if (unlikely(netif_msg_intr(eth))) {
1160 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1161 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
1162 dev_info(eth->dev,
1163 "done tx %d, intr 0x%08x/0x%x\n",
1164 tx_done, status, mask);
1165 }
1166
1167 if (tx_done == budget)
1168 return budget;
1169
1170 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1171 if (status & MTK_TX_DONE_INT)
1172 return budget;
1173
1174 napi_complete(napi);
1175 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1176
1177 return tx_done;
1178 }
1179
1180 static int mtk_napi_rx(struct napi_struct *napi, int budget)
1181 {
1182 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
1183 u32 status, mask;
1184 int rx_done = 0;
1185 int remain_budget = budget;
1186
1187 mtk_handle_status_irq(eth);
1188
1189 poll_again:
1190 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_STATUS);
1191 rx_done = mtk_poll_rx(napi, remain_budget, eth);
1192
1193 if (unlikely(netif_msg_intr(eth))) {
1194 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1195 mask = mtk_r32(eth, MTK_PDMA_INT_MASK);
1196 dev_info(eth->dev,
1197 "done rx %d, intr 0x%08x/0x%x\n",
1198 rx_done, status, mask);
1199 }
1200 if (rx_done == remain_budget)
1201 return budget;
1202
1203 status = mtk_r32(eth, MTK_PDMA_INT_STATUS);
1204 if (status & MTK_RX_DONE_INT) {
1205 remain_budget -= rx_done;
1206 goto poll_again;
1207 }
1208 napi_complete(napi);
1209 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1210
1211 return rx_done + budget - remain_budget;
1212 }
1213
1214 static int mtk_tx_alloc(struct mtk_eth *eth)
1215 {
1216 struct mtk_tx_ring *ring = &eth->tx_ring;
1217 int i, sz = sizeof(*ring->dma);
1218
1219 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
1220 GFP_KERNEL);
1221 if (!ring->buf)
1222 goto no_tx_mem;
1223
1224 ring->dma = dma_alloc_coherent(eth->dev,
1225 MTK_DMA_SIZE * sz,
1226 &ring->phys,
1227 GFP_ATOMIC | __GFP_ZERO);
1228 if (!ring->dma)
1229 goto no_tx_mem;
1230
1231 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
1232 for (i = 0; i < MTK_DMA_SIZE; i++) {
1233 int next = (i + 1) % MTK_DMA_SIZE;
1234 u32 next_ptr = ring->phys + next * sz;
1235
1236 ring->dma[i].txd2 = next_ptr;
1237 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
1238 }
1239
1240 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
1241 ring->next_free = &ring->dma[0];
1242 ring->last_free = &ring->dma[MTK_DMA_SIZE - 1];
1243 ring->thresh = MAX_SKB_FRAGS;
1244
1245 /* make sure that all changes to the dma ring are flushed before we
1246 * continue
1247 */
1248 wmb();
1249
1250 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
1251 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
1252 mtk_w32(eth,
1253 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1254 MTK_QTX_CRX_PTR);
1255 mtk_w32(eth,
1256 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1257 MTK_QTX_DRX_PTR);
1258 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1259
1260 return 0;
1261
1262 no_tx_mem:
1263 return -ENOMEM;
1264 }
1265
1266 static void mtk_tx_clean(struct mtk_eth *eth)
1267 {
1268 struct mtk_tx_ring *ring = &eth->tx_ring;
1269 int i;
1270
1271 if (ring->buf) {
1272 for (i = 0; i < MTK_DMA_SIZE; i++)
1273 mtk_tx_unmap(eth, &ring->buf[i]);
1274 kfree(ring->buf);
1275 ring->buf = NULL;
1276 }
1277
1278 if (ring->dma) {
1279 dma_free_coherent(eth->dev,
1280 MTK_DMA_SIZE * sizeof(*ring->dma),
1281 ring->dma,
1282 ring->phys);
1283 ring->dma = NULL;
1284 }
1285 }
1286
1287 static int mtk_rx_alloc(struct mtk_eth *eth, int ring_no, int rx_flag)
1288 {
1289 struct mtk_rx_ring *ring;
1290 int rx_data_len, rx_dma_size;
1291 int i;
1292 u32 offset = 0;
1293
1294 if (rx_flag == MTK_RX_FLAGS_QDMA) {
1295 if (ring_no)
1296 return -EINVAL;
1297 ring = &eth->rx_ring_qdma;
1298 offset = 0x1000;
1299 } else {
1300 ring = &eth->rx_ring[ring_no];
1301 }
1302
1303 if (rx_flag == MTK_RX_FLAGS_HWLRO) {
1304 rx_data_len = MTK_MAX_LRO_RX_LENGTH;
1305 rx_dma_size = MTK_HW_LRO_DMA_SIZE;
1306 } else {
1307 rx_data_len = ETH_DATA_LEN;
1308 rx_dma_size = MTK_DMA_SIZE;
1309 }
1310
1311 ring->frag_size = mtk_max_frag_size(rx_data_len);
1312 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1313 ring->data = kcalloc(rx_dma_size, sizeof(*ring->data),
1314 GFP_KERNEL);
1315 if (!ring->data)
1316 return -ENOMEM;
1317
1318 for (i = 0; i < rx_dma_size; i++) {
1319 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1320 if (!ring->data[i])
1321 return -ENOMEM;
1322 }
1323
1324 ring->dma = dma_alloc_coherent(eth->dev,
1325 rx_dma_size * sizeof(*ring->dma),
1326 &ring->phys,
1327 GFP_ATOMIC | __GFP_ZERO);
1328 if (!ring->dma)
1329 return -ENOMEM;
1330
1331 for (i = 0; i < rx_dma_size; i++) {
1332 dma_addr_t dma_addr = dma_map_single(eth->dev,
1333 ring->data[i] + NET_SKB_PAD,
1334 ring->buf_size,
1335 DMA_FROM_DEVICE);
1336 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1337 return -ENOMEM;
1338 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1339
1340 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1341 }
1342 ring->dma_size = rx_dma_size;
1343 ring->calc_idx_update = false;
1344 ring->calc_idx = rx_dma_size - 1;
1345 ring->crx_idx_reg = MTK_PRX_CRX_IDX_CFG(ring_no);
1346 /* make sure that all changes to the dma ring are flushed before we
1347 * continue
1348 */
1349 wmb();
1350
1351 mtk_w32(eth, ring->phys, MTK_PRX_BASE_PTR_CFG(ring_no) + offset);
1352 mtk_w32(eth, rx_dma_size, MTK_PRX_MAX_CNT_CFG(ring_no) + offset);
1353 mtk_w32(eth, ring->calc_idx, ring->crx_idx_reg + offset);
1354 mtk_w32(eth, MTK_PST_DRX_IDX_CFG(ring_no), MTK_PDMA_RST_IDX + offset);
1355
1356 return 0;
1357 }
1358
1359 static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring)
1360 {
1361 int i;
1362
1363 if (ring->data && ring->dma) {
1364 for (i = 0; i < ring->dma_size; i++) {
1365 if (!ring->data[i])
1366 continue;
1367 if (!ring->dma[i].rxd1)
1368 continue;
1369 dma_unmap_single(eth->dev,
1370 ring->dma[i].rxd1,
1371 ring->buf_size,
1372 DMA_FROM_DEVICE);
1373 skb_free_frag(ring->data[i]);
1374 }
1375 kfree(ring->data);
1376 ring->data = NULL;
1377 }
1378
1379 if (ring->dma) {
1380 dma_free_coherent(eth->dev,
1381 ring->dma_size * sizeof(*ring->dma),
1382 ring->dma,
1383 ring->phys);
1384 ring->dma = NULL;
1385 }
1386 }
1387
1388 static int mtk_hwlro_rx_init(struct mtk_eth *eth)
1389 {
1390 int i;
1391 u32 ring_ctrl_dw1 = 0, ring_ctrl_dw2 = 0, ring_ctrl_dw3 = 0;
1392 u32 lro_ctrl_dw0 = 0, lro_ctrl_dw3 = 0;
1393
1394 /* set LRO rings to auto-learn modes */
1395 ring_ctrl_dw2 |= MTK_RING_AUTO_LERAN_MODE;
1396
1397 /* validate LRO ring */
1398 ring_ctrl_dw2 |= MTK_RING_VLD;
1399
1400 /* set AGE timer (unit: 20us) */
1401 ring_ctrl_dw2 |= MTK_RING_AGE_TIME_H;
1402 ring_ctrl_dw1 |= MTK_RING_AGE_TIME_L;
1403
1404 /* set max AGG timer (unit: 20us) */
1405 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_TIME;
1406
1407 /* set max LRO AGG count */
1408 ring_ctrl_dw2 |= MTK_RING_MAX_AGG_CNT_L;
1409 ring_ctrl_dw3 |= MTK_RING_MAX_AGG_CNT_H;
1410
1411 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1412 mtk_w32(eth, ring_ctrl_dw1, MTK_LRO_CTRL_DW1_CFG(i));
1413 mtk_w32(eth, ring_ctrl_dw2, MTK_LRO_CTRL_DW2_CFG(i));
1414 mtk_w32(eth, ring_ctrl_dw3, MTK_LRO_CTRL_DW3_CFG(i));
1415 }
1416
1417 /* IPv4 checksum update enable */
1418 lro_ctrl_dw0 |= MTK_L3_CKS_UPD_EN;
1419
1420 /* switch priority comparison to packet count mode */
1421 lro_ctrl_dw0 |= MTK_LRO_ALT_PKT_CNT_MODE;
1422
1423 /* bandwidth threshold setting */
1424 mtk_w32(eth, MTK_HW_LRO_BW_THRE, MTK_PDMA_LRO_CTRL_DW2);
1425
1426 /* auto-learn score delta setting */
1427 mtk_w32(eth, MTK_HW_LRO_REPLACE_DELTA, MTK_PDMA_LRO_ALT_SCORE_DELTA);
1428
1429 /* set refresh timer for altering flows to 1 sec. (unit: 20us) */
1430 mtk_w32(eth, (MTK_HW_LRO_TIMER_UNIT << 16) | MTK_HW_LRO_REFRESH_TIME,
1431 MTK_PDMA_LRO_ALT_REFRESH_TIMER);
1432
1433 /* set HW LRO mode & the max aggregation count for rx packets */
1434 lro_ctrl_dw3 |= MTK_ADMA_MODE | (MTK_HW_LRO_MAX_AGG_CNT & 0xff);
1435
1436 /* the minimal remaining room of SDL0 in RXD for lro aggregation */
1437 lro_ctrl_dw3 |= MTK_LRO_MIN_RXD_SDL;
1438
1439 /* enable HW LRO */
1440 lro_ctrl_dw0 |= MTK_LRO_EN;
1441
1442 mtk_w32(eth, lro_ctrl_dw3, MTK_PDMA_LRO_CTRL_DW3);
1443 mtk_w32(eth, lro_ctrl_dw0, MTK_PDMA_LRO_CTRL_DW0);
1444
1445 return 0;
1446 }
1447
1448 static void mtk_hwlro_rx_uninit(struct mtk_eth *eth)
1449 {
1450 int i;
1451 u32 val;
1452
1453 /* relinquish lro rings, flush aggregated packets */
1454 mtk_w32(eth, MTK_LRO_RING_RELINQUISH_REQ, MTK_PDMA_LRO_CTRL_DW0);
1455
1456 /* wait for relinquishments done */
1457 for (i = 0; i < 10; i++) {
1458 val = mtk_r32(eth, MTK_PDMA_LRO_CTRL_DW0);
1459 if (val & MTK_LRO_RING_RELINQUISH_DONE) {
1460 msleep(20);
1461 continue;
1462 }
1463 break;
1464 }
1465
1466 /* invalidate lro rings */
1467 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1468 mtk_w32(eth, 0, MTK_LRO_CTRL_DW2_CFG(i));
1469
1470 /* disable HW LRO */
1471 mtk_w32(eth, 0, MTK_PDMA_LRO_CTRL_DW0);
1472 }
1473
1474 static void mtk_hwlro_val_ipaddr(struct mtk_eth *eth, int idx, __be32 ip)
1475 {
1476 u32 reg_val;
1477
1478 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1479
1480 /* invalidate the IP setting */
1481 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1482
1483 mtk_w32(eth, ip, MTK_LRO_DIP_DW0_CFG(idx));
1484
1485 /* validate the IP setting */
1486 mtk_w32(eth, (reg_val | MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1487 }
1488
1489 static void mtk_hwlro_inval_ipaddr(struct mtk_eth *eth, int idx)
1490 {
1491 u32 reg_val;
1492
1493 reg_val = mtk_r32(eth, MTK_LRO_CTRL_DW2_CFG(idx));
1494
1495 /* invalidate the IP setting */
1496 mtk_w32(eth, (reg_val & ~MTK_RING_MYIP_VLD), MTK_LRO_CTRL_DW2_CFG(idx));
1497
1498 mtk_w32(eth, 0, MTK_LRO_DIP_DW0_CFG(idx));
1499 }
1500
1501 static int mtk_hwlro_get_ip_cnt(struct mtk_mac *mac)
1502 {
1503 int cnt = 0;
1504 int i;
1505
1506 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1507 if (mac->hwlro_ip[i])
1508 cnt++;
1509 }
1510
1511 return cnt;
1512 }
1513
1514 static int mtk_hwlro_add_ipaddr(struct net_device *dev,
1515 struct ethtool_rxnfc *cmd)
1516 {
1517 struct ethtool_rx_flow_spec *fsp =
1518 (struct ethtool_rx_flow_spec *)&cmd->fs;
1519 struct mtk_mac *mac = netdev_priv(dev);
1520 struct mtk_eth *eth = mac->hw;
1521 int hwlro_idx;
1522
1523 if ((fsp->flow_type != TCP_V4_FLOW) ||
1524 (!fsp->h_u.tcp_ip4_spec.ip4dst) ||
1525 (fsp->location > 1))
1526 return -EINVAL;
1527
1528 mac->hwlro_ip[fsp->location] = htonl(fsp->h_u.tcp_ip4_spec.ip4dst);
1529 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1530
1531 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1532
1533 mtk_hwlro_val_ipaddr(eth, hwlro_idx, mac->hwlro_ip[fsp->location]);
1534
1535 return 0;
1536 }
1537
1538 static int mtk_hwlro_del_ipaddr(struct net_device *dev,
1539 struct ethtool_rxnfc *cmd)
1540 {
1541 struct ethtool_rx_flow_spec *fsp =
1542 (struct ethtool_rx_flow_spec *)&cmd->fs;
1543 struct mtk_mac *mac = netdev_priv(dev);
1544 struct mtk_eth *eth = mac->hw;
1545 int hwlro_idx;
1546
1547 if (fsp->location > 1)
1548 return -EINVAL;
1549
1550 mac->hwlro_ip[fsp->location] = 0;
1551 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + fsp->location;
1552
1553 mac->hwlro_ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1554
1555 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1556
1557 return 0;
1558 }
1559
1560 static void mtk_hwlro_netdev_disable(struct net_device *dev)
1561 {
1562 struct mtk_mac *mac = netdev_priv(dev);
1563 struct mtk_eth *eth = mac->hw;
1564 int i, hwlro_idx;
1565
1566 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1567 mac->hwlro_ip[i] = 0;
1568 hwlro_idx = (mac->id * MTK_MAX_LRO_IP_CNT) + i;
1569
1570 mtk_hwlro_inval_ipaddr(eth, hwlro_idx);
1571 }
1572
1573 mac->hwlro_ip_cnt = 0;
1574 }
1575
1576 static int mtk_hwlro_get_fdir_entry(struct net_device *dev,
1577 struct ethtool_rxnfc *cmd)
1578 {
1579 struct mtk_mac *mac = netdev_priv(dev);
1580 struct ethtool_rx_flow_spec *fsp =
1581 (struct ethtool_rx_flow_spec *)&cmd->fs;
1582
1583 /* only tcp dst ipv4 is meaningful, others are meaningless */
1584 fsp->flow_type = TCP_V4_FLOW;
1585 fsp->h_u.tcp_ip4_spec.ip4dst = ntohl(mac->hwlro_ip[fsp->location]);
1586 fsp->m_u.tcp_ip4_spec.ip4dst = 0;
1587
1588 fsp->h_u.tcp_ip4_spec.ip4src = 0;
1589 fsp->m_u.tcp_ip4_spec.ip4src = 0xffffffff;
1590 fsp->h_u.tcp_ip4_spec.psrc = 0;
1591 fsp->m_u.tcp_ip4_spec.psrc = 0xffff;
1592 fsp->h_u.tcp_ip4_spec.pdst = 0;
1593 fsp->m_u.tcp_ip4_spec.pdst = 0xffff;
1594 fsp->h_u.tcp_ip4_spec.tos = 0;
1595 fsp->m_u.tcp_ip4_spec.tos = 0xff;
1596
1597 return 0;
1598 }
1599
1600 static int mtk_hwlro_get_fdir_all(struct net_device *dev,
1601 struct ethtool_rxnfc *cmd,
1602 u32 *rule_locs)
1603 {
1604 struct mtk_mac *mac = netdev_priv(dev);
1605 int cnt = 0;
1606 int i;
1607
1608 for (i = 0; i < MTK_MAX_LRO_IP_CNT; i++) {
1609 if (mac->hwlro_ip[i]) {
1610 rule_locs[cnt] = i;
1611 cnt++;
1612 }
1613 }
1614
1615 cmd->rule_cnt = cnt;
1616
1617 return 0;
1618 }
1619
1620 static netdev_features_t mtk_fix_features(struct net_device *dev,
1621 netdev_features_t features)
1622 {
1623 if (!(features & NETIF_F_LRO)) {
1624 struct mtk_mac *mac = netdev_priv(dev);
1625 int ip_cnt = mtk_hwlro_get_ip_cnt(mac);
1626
1627 if (ip_cnt) {
1628 netdev_info(dev, "RX flow is programmed, LRO should keep on\n");
1629
1630 features |= NETIF_F_LRO;
1631 }
1632 }
1633
1634 return features;
1635 }
1636
1637 static int mtk_set_features(struct net_device *dev, netdev_features_t features)
1638 {
1639 int err = 0;
1640
1641 if (!((dev->features ^ features) & NETIF_F_LRO))
1642 return 0;
1643
1644 if (!(features & NETIF_F_LRO))
1645 mtk_hwlro_netdev_disable(dev);
1646
1647 return err;
1648 }
1649
1650 /* wait for DMA to finish whatever it is doing before we start using it again */
1651 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1652 {
1653 unsigned long t_start = jiffies;
1654
1655 while (1) {
1656 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1657 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1658 return 0;
1659 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1660 break;
1661 }
1662
1663 dev_err(eth->dev, "DMA init timeout\n");
1664 return -1;
1665 }
1666
1667 static int mtk_dma_init(struct mtk_eth *eth)
1668 {
1669 int err;
1670 u32 i;
1671
1672 if (mtk_dma_busy_wait(eth))
1673 return -EBUSY;
1674
1675 /* QDMA needs scratch memory for internal reordering of the
1676 * descriptors
1677 */
1678 err = mtk_init_fq_dma(eth);
1679 if (err)
1680 return err;
1681
1682 err = mtk_tx_alloc(eth);
1683 if (err)
1684 return err;
1685
1686 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_QDMA);
1687 if (err)
1688 return err;
1689
1690 err = mtk_rx_alloc(eth, 0, MTK_RX_FLAGS_NORMAL);
1691 if (err)
1692 return err;
1693
1694 if (eth->hwlro) {
1695 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++) {
1696 err = mtk_rx_alloc(eth, i, MTK_RX_FLAGS_HWLRO);
1697 if (err)
1698 return err;
1699 }
1700 err = mtk_hwlro_rx_init(eth);
1701 if (err)
1702 return err;
1703 }
1704
1705 /* Enable random early drop and set drop threshold automatically */
1706 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1707 MTK_QDMA_FC_THRES);
1708 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1709
1710 return 0;
1711 }
1712
1713 static void mtk_dma_free(struct mtk_eth *eth)
1714 {
1715 int i;
1716
1717 for (i = 0; i < MTK_MAC_COUNT; i++)
1718 if (eth->netdev[i])
1719 netdev_reset_queue(eth->netdev[i]);
1720 if (eth->scratch_ring) {
1721 dma_free_coherent(eth->dev,
1722 MTK_DMA_SIZE * sizeof(struct mtk_tx_dma),
1723 eth->scratch_ring,
1724 eth->phy_scratch_ring);
1725 eth->scratch_ring = NULL;
1726 eth->phy_scratch_ring = 0;
1727 }
1728 mtk_tx_clean(eth);
1729 mtk_rx_clean(eth, &eth->rx_ring[0]);
1730 mtk_rx_clean(eth, &eth->rx_ring_qdma);
1731
1732 if (eth->hwlro) {
1733 mtk_hwlro_rx_uninit(eth);
1734 for (i = 1; i < MTK_MAX_RX_RING_NUM; i++)
1735 mtk_rx_clean(eth, &eth->rx_ring[i]);
1736 }
1737
1738 kfree(eth->scratch_head);
1739 }
1740
1741 static void mtk_tx_timeout(struct net_device *dev)
1742 {
1743 struct mtk_mac *mac = netdev_priv(dev);
1744 struct mtk_eth *eth = mac->hw;
1745
1746 eth->netdev[mac->id]->stats.tx_errors++;
1747 netif_err(eth, tx_err, dev,
1748 "transmit timed out\n");
1749 schedule_work(&eth->pending_work);
1750 }
1751
1752 static irqreturn_t mtk_handle_irq_rx(int irq, void *_eth)
1753 {
1754 struct mtk_eth *eth = _eth;
1755
1756 if (likely(napi_schedule_prep(&eth->rx_napi))) {
1757 __napi_schedule(&eth->rx_napi);
1758 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1759 }
1760
1761 return IRQ_HANDLED;
1762 }
1763
1764 static irqreturn_t mtk_handle_irq_tx(int irq, void *_eth)
1765 {
1766 struct mtk_eth *eth = _eth;
1767
1768 if (likely(napi_schedule_prep(&eth->tx_napi))) {
1769 __napi_schedule(&eth->tx_napi);
1770 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1771 }
1772
1773 return IRQ_HANDLED;
1774 }
1775
1776 #ifdef CONFIG_NET_POLL_CONTROLLER
1777 static void mtk_poll_controller(struct net_device *dev)
1778 {
1779 struct mtk_mac *mac = netdev_priv(dev);
1780 struct mtk_eth *eth = mac->hw;
1781
1782 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1783 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1784 mtk_handle_irq_rx(eth->irq[2], dev);
1785 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1786 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1787 }
1788 #endif
1789
1790 static int mtk_start_dma(struct mtk_eth *eth)
1791 {
1792 int err;
1793
1794 err = mtk_dma_init(eth);
1795 if (err) {
1796 mtk_dma_free(eth);
1797 return err;
1798 }
1799
1800 mtk_w32(eth,
1801 MTK_TX_WB_DDONE | MTK_TX_DMA_EN |
1802 MTK_DMA_SIZE_16DWORDS | MTK_NDP_CO_PRO |
1803 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1804 MTK_RX_BT_32DWORDS,
1805 MTK_QDMA_GLO_CFG);
1806
1807 mtk_w32(eth,
1808 MTK_RX_DMA_EN | MTK_RX_2B_OFFSET |
1809 MTK_RX_BT_32DWORDS | MTK_MULTI_EN,
1810 MTK_PDMA_GLO_CFG);
1811
1812 return 0;
1813 }
1814
1815 static int mtk_open(struct net_device *dev)
1816 {
1817 struct mtk_mac *mac = netdev_priv(dev);
1818 struct mtk_eth *eth = mac->hw;
1819
1820 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1821 if (!refcount_read(&eth->dma_refcnt)) {
1822 int err = mtk_start_dma(eth);
1823
1824 if (err)
1825 return err;
1826
1827 napi_enable(&eth->tx_napi);
1828 napi_enable(&eth->rx_napi);
1829 mtk_tx_irq_enable(eth, MTK_TX_DONE_INT);
1830 mtk_rx_irq_enable(eth, MTK_RX_DONE_INT);
1831 refcount_set(&eth->dma_refcnt, 1);
1832 }
1833 else
1834 refcount_inc(&eth->dma_refcnt);
1835
1836 phy_start(dev->phydev);
1837 netif_start_queue(dev);
1838
1839 return 0;
1840 }
1841
1842 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1843 {
1844 u32 val;
1845 int i;
1846
1847 /* stop the dma engine */
1848 spin_lock_bh(&eth->page_lock);
1849 val = mtk_r32(eth, glo_cfg);
1850 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1851 glo_cfg);
1852 spin_unlock_bh(&eth->page_lock);
1853
1854 /* wait for dma stop */
1855 for (i = 0; i < 10; i++) {
1856 val = mtk_r32(eth, glo_cfg);
1857 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1858 msleep(20);
1859 continue;
1860 }
1861 break;
1862 }
1863 }
1864
1865 static int mtk_stop(struct net_device *dev)
1866 {
1867 struct mtk_mac *mac = netdev_priv(dev);
1868 struct mtk_eth *eth = mac->hw;
1869
1870 netif_tx_disable(dev);
1871 phy_stop(dev->phydev);
1872
1873 /* only shutdown DMA if this is the last user */
1874 if (!refcount_dec_and_test(&eth->dma_refcnt))
1875 return 0;
1876
1877 mtk_tx_irq_disable(eth, MTK_TX_DONE_INT);
1878 mtk_rx_irq_disable(eth, MTK_RX_DONE_INT);
1879 napi_disable(&eth->tx_napi);
1880 napi_disable(&eth->rx_napi);
1881
1882 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1883 mtk_stop_dma(eth, MTK_PDMA_GLO_CFG);
1884
1885 mtk_dma_free(eth);
1886
1887 return 0;
1888 }
1889
1890 static void ethsys_reset(struct mtk_eth *eth, u32 reset_bits)
1891 {
1892 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1893 reset_bits,
1894 reset_bits);
1895
1896 usleep_range(1000, 1100);
1897 regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL,
1898 reset_bits,
1899 ~reset_bits);
1900 mdelay(10);
1901 }
1902
1903 static void mtk_clk_disable(struct mtk_eth *eth)
1904 {
1905 int clk;
1906
1907 for (clk = MTK_CLK_MAX - 1; clk >= 0; clk--)
1908 clk_disable_unprepare(eth->clks[clk]);
1909 }
1910
1911 static int mtk_clk_enable(struct mtk_eth *eth)
1912 {
1913 int clk, ret;
1914
1915 for (clk = 0; clk < MTK_CLK_MAX ; clk++) {
1916 ret = clk_prepare_enable(eth->clks[clk]);
1917 if (ret)
1918 goto err_disable_clks;
1919 }
1920
1921 return 0;
1922
1923 err_disable_clks:
1924 while (--clk >= 0)
1925 clk_disable_unprepare(eth->clks[clk]);
1926
1927 return ret;
1928 }
1929
1930 static int mtk_hw_init(struct mtk_eth *eth)
1931 {
1932 int i, val, ret;
1933
1934 if (test_and_set_bit(MTK_HW_INIT, &eth->state))
1935 return 0;
1936
1937 pm_runtime_enable(eth->dev);
1938 pm_runtime_get_sync(eth->dev);
1939
1940 ret = mtk_clk_enable(eth);
1941 if (ret)
1942 goto err_disable_pm;
1943
1944 ethsys_reset(eth, RSTCTRL_FE);
1945 ethsys_reset(eth, RSTCTRL_PPE);
1946
1947 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
1948 for (i = 0; i < MTK_MAC_COUNT; i++) {
1949 if (!eth->mac[i])
1950 continue;
1951 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, eth->mac[i]->id);
1952 val |= SYSCFG0_GE_MODE(eth->mac[i]->ge_mode, eth->mac[i]->id);
1953 }
1954 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
1955
1956 if (eth->pctl) {
1957 /* Set GE2 driving and slew rate */
1958 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1959
1960 /* set GE2 TDSEL */
1961 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1962
1963 /* set GE2 TUNE */
1964 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1965 }
1966
1967 /* Set linkdown as the default for each GMAC. Its own MCR would be set
1968 * up with the more appropriate value when mtk_phy_link_adjust call is
1969 * being invoked.
1970 */
1971 for (i = 0; i < MTK_MAC_COUNT; i++)
1972 mtk_w32(eth, 0, MTK_MAC_MCR(i));
1973
1974 /* Indicates CDM to parse the MTK special tag from CPU
1975 * which also is working out for untag packets.
1976 */
1977 val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
1978 mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
1979
1980 /* Enable RX VLan Offloading */
1981 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1982
1983 /* enable interrupt delay for RX */
1984 mtk_w32(eth, MTK_PDMA_DELAY_RX_DELAY, MTK_PDMA_DELAY_INT);
1985
1986 /* disable delay and normal interrupt */
1987 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1988 mtk_tx_irq_disable(eth, ~0);
1989 mtk_rx_irq_disable(eth, ~0);
1990 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1991 mtk_w32(eth, 0, MTK_RST_GL);
1992
1993 /* FE int grouping */
1994 mtk_w32(eth, MTK_TX_DONE_INT, MTK_PDMA_INT_GRP1);
1995 mtk_w32(eth, MTK_RX_DONE_INT, MTK_PDMA_INT_GRP2);
1996 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QDMA_INT_GRP1);
1997 mtk_w32(eth, MTK_RX_DONE_INT, MTK_QDMA_INT_GRP2);
1998 mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
1999
2000 for (i = 0; i < 2; i++) {
2001 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
2002
2003 /* setup the forward port to send frame to PDMA */
2004 val &= ~0xffff;
2005
2006 /* Enable RX checksum */
2007 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
2008
2009 /* setup the mac dma */
2010 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
2011 }
2012
2013 return 0;
2014
2015 err_disable_pm:
2016 pm_runtime_put_sync(eth->dev);
2017 pm_runtime_disable(eth->dev);
2018
2019 return ret;
2020 }
2021
2022 static int mtk_hw_deinit(struct mtk_eth *eth)
2023 {
2024 if (!test_and_clear_bit(MTK_HW_INIT, &eth->state))
2025 return 0;
2026
2027 mtk_clk_disable(eth);
2028
2029 pm_runtime_put_sync(eth->dev);
2030 pm_runtime_disable(eth->dev);
2031
2032 return 0;
2033 }
2034
2035 static int __init mtk_init(struct net_device *dev)
2036 {
2037 struct mtk_mac *mac = netdev_priv(dev);
2038 struct mtk_eth *eth = mac->hw;
2039 const char *mac_addr;
2040
2041 mac_addr = of_get_mac_address(mac->of_node);
2042 if (mac_addr)
2043 ether_addr_copy(dev->dev_addr, mac_addr);
2044
2045 /* If the mac address is invalid, use random mac address */
2046 if (!is_valid_ether_addr(dev->dev_addr)) {
2047 eth_hw_addr_random(dev);
2048 dev_err(eth->dev, "generated random MAC address %pM\n",
2049 dev->dev_addr);
2050 }
2051
2052 return mtk_phy_connect(dev);
2053 }
2054
2055 static void mtk_uninit(struct net_device *dev)
2056 {
2057 struct mtk_mac *mac = netdev_priv(dev);
2058 struct mtk_eth *eth = mac->hw;
2059
2060 phy_disconnect(dev->phydev);
2061 if (of_phy_is_fixed_link(mac->of_node))
2062 of_phy_deregister_fixed_link(mac->of_node);
2063 mtk_tx_irq_disable(eth, ~0);
2064 mtk_rx_irq_disable(eth, ~0);
2065 }
2066
2067 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2068 {
2069 switch (cmd) {
2070 case SIOCGMIIPHY:
2071 case SIOCGMIIREG:
2072 case SIOCSMIIREG:
2073 return phy_mii_ioctl(dev->phydev, ifr, cmd);
2074 default:
2075 break;
2076 }
2077
2078 return -EOPNOTSUPP;
2079 }
2080
2081 static void mtk_pending_work(struct work_struct *work)
2082 {
2083 struct mtk_eth *eth = container_of(work, struct mtk_eth, pending_work);
2084 int err, i;
2085 unsigned long restart = 0;
2086
2087 rtnl_lock();
2088
2089 dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
2090
2091 while (test_and_set_bit_lock(MTK_RESETTING, &eth->state))
2092 cpu_relax();
2093
2094 dev_dbg(eth->dev, "[%s][%d] mtk_stop starts\n", __func__, __LINE__);
2095 /* stop all devices to make sure that dma is properly shut down */
2096 for (i = 0; i < MTK_MAC_COUNT; i++) {
2097 if (!eth->netdev[i])
2098 continue;
2099 mtk_stop(eth->netdev[i]);
2100 __set_bit(i, &restart);
2101 }
2102 dev_dbg(eth->dev, "[%s][%d] mtk_stop ends\n", __func__, __LINE__);
2103
2104 /* restart underlying hardware such as power, clock, pin mux
2105 * and the connected phy
2106 */
2107 mtk_hw_deinit(eth);
2108
2109 if (eth->dev->pins)
2110 pinctrl_select_state(eth->dev->pins->p,
2111 eth->dev->pins->default_state);
2112 mtk_hw_init(eth);
2113
2114 for (i = 0; i < MTK_MAC_COUNT; i++) {
2115 if (!eth->mac[i] ||
2116 of_phy_is_fixed_link(eth->mac[i]->of_node))
2117 continue;
2118 err = phy_init_hw(eth->netdev[i]->phydev);
2119 if (err)
2120 dev_err(eth->dev, "%s: PHY init failed.\n",
2121 eth->netdev[i]->name);
2122 }
2123
2124 /* restart DMA and enable IRQs */
2125 for (i = 0; i < MTK_MAC_COUNT; i++) {
2126 if (!test_bit(i, &restart))
2127 continue;
2128 err = mtk_open(eth->netdev[i]);
2129 if (err) {
2130 netif_alert(eth, ifup, eth->netdev[i],
2131 "Driver up/down cycle failed, closing device.\n");
2132 dev_close(eth->netdev[i]);
2133 }
2134 }
2135
2136 dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
2137
2138 clear_bit_unlock(MTK_RESETTING, &eth->state);
2139
2140 rtnl_unlock();
2141 }
2142
2143 static int mtk_free_dev(struct mtk_eth *eth)
2144 {
2145 int i;
2146
2147 for (i = 0; i < MTK_MAC_COUNT; i++) {
2148 if (!eth->netdev[i])
2149 continue;
2150 free_netdev(eth->netdev[i]);
2151 }
2152
2153 return 0;
2154 }
2155
2156 static int mtk_unreg_dev(struct mtk_eth *eth)
2157 {
2158 int i;
2159
2160 for (i = 0; i < MTK_MAC_COUNT; i++) {
2161 if (!eth->netdev[i])
2162 continue;
2163 unregister_netdev(eth->netdev[i]);
2164 }
2165
2166 return 0;
2167 }
2168
2169 static int mtk_cleanup(struct mtk_eth *eth)
2170 {
2171 mtk_unreg_dev(eth);
2172 mtk_free_dev(eth);
2173 cancel_work_sync(&eth->pending_work);
2174
2175 return 0;
2176 }
2177
2178 static int mtk_get_link_ksettings(struct net_device *ndev,
2179 struct ethtool_link_ksettings *cmd)
2180 {
2181 struct mtk_mac *mac = netdev_priv(ndev);
2182
2183 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2184 return -EBUSY;
2185
2186 phy_ethtool_ksettings_get(ndev->phydev, cmd);
2187
2188 return 0;
2189 }
2190
2191 static int mtk_set_link_ksettings(struct net_device *ndev,
2192 const struct ethtool_link_ksettings *cmd)
2193 {
2194 struct mtk_mac *mac = netdev_priv(ndev);
2195
2196 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2197 return -EBUSY;
2198
2199 return phy_ethtool_ksettings_set(ndev->phydev, cmd);
2200 }
2201
2202 static void mtk_get_drvinfo(struct net_device *dev,
2203 struct ethtool_drvinfo *info)
2204 {
2205 struct mtk_mac *mac = netdev_priv(dev);
2206
2207 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
2208 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
2209 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
2210 }
2211
2212 static u32 mtk_get_msglevel(struct net_device *dev)
2213 {
2214 struct mtk_mac *mac = netdev_priv(dev);
2215
2216 return mac->hw->msg_enable;
2217 }
2218
2219 static void mtk_set_msglevel(struct net_device *dev, u32 value)
2220 {
2221 struct mtk_mac *mac = netdev_priv(dev);
2222
2223 mac->hw->msg_enable = value;
2224 }
2225
2226 static int mtk_nway_reset(struct net_device *dev)
2227 {
2228 struct mtk_mac *mac = netdev_priv(dev);
2229
2230 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2231 return -EBUSY;
2232
2233 return genphy_restart_aneg(dev->phydev);
2234 }
2235
2236 static u32 mtk_get_link(struct net_device *dev)
2237 {
2238 struct mtk_mac *mac = netdev_priv(dev);
2239 int err;
2240
2241 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2242 return -EBUSY;
2243
2244 err = genphy_update_link(dev->phydev);
2245 if (err)
2246 return ethtool_op_get_link(dev);
2247
2248 return dev->phydev->link;
2249 }
2250
2251 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2252 {
2253 int i;
2254
2255 switch (stringset) {
2256 case ETH_SS_STATS:
2257 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
2258 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
2259 data += ETH_GSTRING_LEN;
2260 }
2261 break;
2262 }
2263 }
2264
2265 static int mtk_get_sset_count(struct net_device *dev, int sset)
2266 {
2267 switch (sset) {
2268 case ETH_SS_STATS:
2269 return ARRAY_SIZE(mtk_ethtool_stats);
2270 default:
2271 return -EOPNOTSUPP;
2272 }
2273 }
2274
2275 static void mtk_get_ethtool_stats(struct net_device *dev,
2276 struct ethtool_stats *stats, u64 *data)
2277 {
2278 struct mtk_mac *mac = netdev_priv(dev);
2279 struct mtk_hw_stats *hwstats = mac->hw_stats;
2280 u64 *data_src, *data_dst;
2281 unsigned int start;
2282 int i;
2283
2284 if (unlikely(test_bit(MTK_RESETTING, &mac->hw->state)))
2285 return;
2286
2287 if (netif_running(dev) && netif_device_present(dev)) {
2288 if (spin_trylock_bh(&hwstats->stats_lock)) {
2289 mtk_stats_update_mac(mac);
2290 spin_unlock_bh(&hwstats->stats_lock);
2291 }
2292 }
2293
2294 data_src = (u64 *)hwstats;
2295
2296 do {
2297 data_dst = data;
2298 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
2299
2300 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
2301 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
2302 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
2303 }
2304
2305 static int mtk_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
2306 u32 *rule_locs)
2307 {
2308 int ret = -EOPNOTSUPP;
2309
2310 switch (cmd->cmd) {
2311 case ETHTOOL_GRXRINGS:
2312 if (dev->features & NETIF_F_LRO) {
2313 cmd->data = MTK_MAX_RX_RING_NUM;
2314 ret = 0;
2315 }
2316 break;
2317 case ETHTOOL_GRXCLSRLCNT:
2318 if (dev->features & NETIF_F_LRO) {
2319 struct mtk_mac *mac = netdev_priv(dev);
2320
2321 cmd->rule_cnt = mac->hwlro_ip_cnt;
2322 ret = 0;
2323 }
2324 break;
2325 case ETHTOOL_GRXCLSRULE:
2326 if (dev->features & NETIF_F_LRO)
2327 ret = mtk_hwlro_get_fdir_entry(dev, cmd);
2328 break;
2329 case ETHTOOL_GRXCLSRLALL:
2330 if (dev->features & NETIF_F_LRO)
2331 ret = mtk_hwlro_get_fdir_all(dev, cmd,
2332 rule_locs);
2333 break;
2334 default:
2335 break;
2336 }
2337
2338 return ret;
2339 }
2340
2341 static int mtk_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd)
2342 {
2343 int ret = -EOPNOTSUPP;
2344
2345 switch (cmd->cmd) {
2346 case ETHTOOL_SRXCLSRLINS:
2347 if (dev->features & NETIF_F_LRO)
2348 ret = mtk_hwlro_add_ipaddr(dev, cmd);
2349 break;
2350 case ETHTOOL_SRXCLSRLDEL:
2351 if (dev->features & NETIF_F_LRO)
2352 ret = mtk_hwlro_del_ipaddr(dev, cmd);
2353 break;
2354 default:
2355 break;
2356 }
2357
2358 return ret;
2359 }
2360
2361 static const struct ethtool_ops mtk_ethtool_ops = {
2362 .get_link_ksettings = mtk_get_link_ksettings,
2363 .set_link_ksettings = mtk_set_link_ksettings,
2364 .get_drvinfo = mtk_get_drvinfo,
2365 .get_msglevel = mtk_get_msglevel,
2366 .set_msglevel = mtk_set_msglevel,
2367 .nway_reset = mtk_nway_reset,
2368 .get_link = mtk_get_link,
2369 .get_strings = mtk_get_strings,
2370 .get_sset_count = mtk_get_sset_count,
2371 .get_ethtool_stats = mtk_get_ethtool_stats,
2372 .get_rxnfc = mtk_get_rxnfc,
2373 .set_rxnfc = mtk_set_rxnfc,
2374 };
2375
2376 static const struct net_device_ops mtk_netdev_ops = {
2377 .ndo_init = mtk_init,
2378 .ndo_uninit = mtk_uninit,
2379 .ndo_open = mtk_open,
2380 .ndo_stop = mtk_stop,
2381 .ndo_start_xmit = mtk_start_xmit,
2382 .ndo_set_mac_address = mtk_set_mac_address,
2383 .ndo_validate_addr = eth_validate_addr,
2384 .ndo_do_ioctl = mtk_do_ioctl,
2385 .ndo_tx_timeout = mtk_tx_timeout,
2386 .ndo_get_stats64 = mtk_get_stats64,
2387 .ndo_fix_features = mtk_fix_features,
2388 .ndo_set_features = mtk_set_features,
2389 #ifdef CONFIG_NET_POLL_CONTROLLER
2390 .ndo_poll_controller = mtk_poll_controller,
2391 #endif
2392 };
2393
2394 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
2395 {
2396 struct mtk_mac *mac;
2397 const __be32 *_id = of_get_property(np, "reg", NULL);
2398 int id, err;
2399
2400 if (!_id) {
2401 dev_err(eth->dev, "missing mac id\n");
2402 return -EINVAL;
2403 }
2404
2405 id = be32_to_cpup(_id);
2406 if (id >= MTK_MAC_COUNT) {
2407 dev_err(eth->dev, "%d is not a valid mac id\n", id);
2408 return -EINVAL;
2409 }
2410
2411 if (eth->netdev[id]) {
2412 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
2413 return -EINVAL;
2414 }
2415
2416 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
2417 if (!eth->netdev[id]) {
2418 dev_err(eth->dev, "alloc_etherdev failed\n");
2419 return -ENOMEM;
2420 }
2421 mac = netdev_priv(eth->netdev[id]);
2422 eth->mac[id] = mac;
2423 mac->id = id;
2424 mac->hw = eth;
2425 mac->of_node = np;
2426
2427 memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
2428 mac->hwlro_ip_cnt = 0;
2429
2430 mac->hw_stats = devm_kzalloc(eth->dev,
2431 sizeof(*mac->hw_stats),
2432 GFP_KERNEL);
2433 if (!mac->hw_stats) {
2434 dev_err(eth->dev, "failed to allocate counter memory\n");
2435 err = -ENOMEM;
2436 goto free_netdev;
2437 }
2438 spin_lock_init(&mac->hw_stats->stats_lock);
2439 u64_stats_init(&mac->hw_stats->syncp);
2440 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
2441
2442 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
2443 eth->netdev[id]->watchdog_timeo = 5 * HZ;
2444 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
2445 eth->netdev[id]->base_addr = (unsigned long)eth->base;
2446
2447 eth->netdev[id]->hw_features = MTK_HW_FEATURES;
2448 if (eth->hwlro)
2449 eth->netdev[id]->hw_features |= NETIF_F_LRO;
2450
2451 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
2452 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
2453 eth->netdev[id]->features |= MTK_HW_FEATURES;
2454 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
2455
2456 eth->netdev[id]->irq = eth->irq[0];
2457 eth->netdev[id]->dev.of_node = np;
2458
2459 return 0;
2460
2461 free_netdev:
2462 free_netdev(eth->netdev[id]);
2463 return err;
2464 }
2465
2466 static int mtk_get_chip_id(struct mtk_eth *eth, u32 *chip_id)
2467 {
2468 u32 val[2], id[4];
2469
2470 regmap_read(eth->ethsys, ETHSYS_CHIPID0_3, &val[0]);
2471 regmap_read(eth->ethsys, ETHSYS_CHIPID4_7, &val[1]);
2472
2473 id[3] = ((val[0] >> 16) & 0xff) - '0';
2474 id[2] = ((val[0] >> 24) & 0xff) - '0';
2475 id[1] = (val[1] & 0xff) - '0';
2476 id[0] = ((val[1] >> 8) & 0xff) - '0';
2477
2478 *chip_id = (id[3] * 1000) + (id[2] * 100) +
2479 (id[1] * 10) + id[0];
2480
2481 if (!(*chip_id)) {
2482 dev_err(eth->dev, "failed to get chip id\n");
2483 return -ENODEV;
2484 }
2485
2486 dev_info(eth->dev, "chip id = %d\n", *chip_id);
2487
2488 return 0;
2489 }
2490
2491 static bool mtk_is_hwlro_supported(struct mtk_eth *eth)
2492 {
2493 switch (eth->chip_id) {
2494 case MT7622_ETH:
2495 case MT7623_ETH:
2496 return true;
2497 }
2498
2499 return false;
2500 }
2501
2502 static int mtk_probe(struct platform_device *pdev)
2503 {
2504 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2505 struct device_node *mac_np;
2506 const struct of_device_id *match;
2507 struct mtk_eth *eth;
2508 int err;
2509 int i;
2510
2511 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
2512 if (!eth)
2513 return -ENOMEM;
2514
2515 match = of_match_device(of_mtk_match, &pdev->dev);
2516 eth->soc = (struct mtk_soc_data *)match->data;
2517
2518 eth->dev = &pdev->dev;
2519 eth->base = devm_ioremap_resource(&pdev->dev, res);
2520 if (IS_ERR(eth->base))
2521 return PTR_ERR(eth->base);
2522
2523 spin_lock_init(&eth->page_lock);
2524 spin_lock_init(&eth->tx_irq_lock);
2525 spin_lock_init(&eth->rx_irq_lock);
2526
2527 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2528 "mediatek,ethsys");
2529 if (IS_ERR(eth->ethsys)) {
2530 dev_err(&pdev->dev, "no ethsys regmap found\n");
2531 return PTR_ERR(eth->ethsys);
2532 }
2533
2534 if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
2535 eth->sgmiisys =
2536 syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2537 "mediatek,sgmiisys");
2538 if (IS_ERR(eth->sgmiisys)) {
2539 dev_err(&pdev->dev, "no sgmiisys regmap found\n");
2540 return PTR_ERR(eth->sgmiisys);
2541 }
2542 }
2543
2544 if (eth->soc->required_pctl) {
2545 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
2546 "mediatek,pctl");
2547 if (IS_ERR(eth->pctl)) {
2548 dev_err(&pdev->dev, "no pctl regmap found\n");
2549 return PTR_ERR(eth->pctl);
2550 }
2551 }
2552
2553 for (i = 0; i < 3; i++) {
2554 eth->irq[i] = platform_get_irq(pdev, i);
2555 if (eth->irq[i] < 0) {
2556 dev_err(&pdev->dev, "no IRQ%d resource found\n", i);
2557 return -ENXIO;
2558 }
2559 }
2560 for (i = 0; i < ARRAY_SIZE(eth->clks); i++) {
2561 eth->clks[i] = devm_clk_get(eth->dev,
2562 mtk_clks_source_name[i]);
2563 if (IS_ERR(eth->clks[i])) {
2564 if (PTR_ERR(eth->clks[i]) == -EPROBE_DEFER)
2565 return -EPROBE_DEFER;
2566 if (eth->soc->required_clks & BIT(i)) {
2567 dev_err(&pdev->dev, "clock %s not found\n",
2568 mtk_clks_source_name[i]);
2569 return -EINVAL;
2570 }
2571 eth->clks[i] = NULL;
2572 }
2573 }
2574
2575 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
2576 INIT_WORK(&eth->pending_work, mtk_pending_work);
2577
2578 err = mtk_hw_init(eth);
2579 if (err)
2580 return err;
2581
2582 err = mtk_get_chip_id(eth, &eth->chip_id);
2583 if (err)
2584 return err;
2585
2586 eth->hwlro = mtk_is_hwlro_supported(eth);
2587
2588 for_each_child_of_node(pdev->dev.of_node, mac_np) {
2589 if (!of_device_is_compatible(mac_np,
2590 "mediatek,eth-mac"))
2591 continue;
2592
2593 if (!of_device_is_available(mac_np))
2594 continue;
2595
2596 err = mtk_add_mac(eth, mac_np);
2597 if (err)
2598 goto err_deinit_hw;
2599 }
2600
2601 err = devm_request_irq(eth->dev, eth->irq[1], mtk_handle_irq_tx, 0,
2602 dev_name(eth->dev), eth);
2603 if (err)
2604 goto err_free_dev;
2605
2606 err = devm_request_irq(eth->dev, eth->irq[2], mtk_handle_irq_rx, 0,
2607 dev_name(eth->dev), eth);
2608 if (err)
2609 goto err_free_dev;
2610
2611 err = mtk_mdio_init(eth);
2612 if (err)
2613 goto err_free_dev;
2614
2615 for (i = 0; i < MTK_MAX_DEVS; i++) {
2616 if (!eth->netdev[i])
2617 continue;
2618
2619 err = register_netdev(eth->netdev[i]);
2620 if (err) {
2621 dev_err(eth->dev, "error bringing up device\n");
2622 goto err_deinit_mdio;
2623 } else
2624 netif_info(eth, probe, eth->netdev[i],
2625 "mediatek frame engine at 0x%08lx, irq %d\n",
2626 eth->netdev[i]->base_addr, eth->irq[0]);
2627 }
2628
2629 /* we run 2 devices on the same DMA ring so we need a dummy device
2630 * for NAPI to work
2631 */
2632 init_dummy_netdev(&eth->dummy_dev);
2633 netif_napi_add(&eth->dummy_dev, &eth->tx_napi, mtk_napi_tx,
2634 MTK_NAPI_WEIGHT);
2635 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx,
2636 MTK_NAPI_WEIGHT);
2637
2638 platform_set_drvdata(pdev, eth);
2639
2640 return 0;
2641
2642 err_deinit_mdio:
2643 mtk_mdio_cleanup(eth);
2644 err_free_dev:
2645 mtk_free_dev(eth);
2646 err_deinit_hw:
2647 mtk_hw_deinit(eth);
2648
2649 return err;
2650 }
2651
2652 static int mtk_remove(struct platform_device *pdev)
2653 {
2654 struct mtk_eth *eth = platform_get_drvdata(pdev);
2655 int i;
2656
2657 /* stop all devices to make sure that dma is properly shut down */
2658 for (i = 0; i < MTK_MAC_COUNT; i++) {
2659 if (!eth->netdev[i])
2660 continue;
2661 mtk_stop(eth->netdev[i]);
2662 }
2663
2664 mtk_hw_deinit(eth);
2665
2666 netif_napi_del(&eth->tx_napi);
2667 netif_napi_del(&eth->rx_napi);
2668 mtk_cleanup(eth);
2669 mtk_mdio_cleanup(eth);
2670
2671 return 0;
2672 }
2673
2674 static const struct mtk_soc_data mt2701_data = {
2675 .caps = MTK_GMAC1_TRGMII,
2676 .required_clks = MT7623_CLKS_BITMAP,
2677 .required_pctl = true,
2678 };
2679
2680 static const struct mtk_soc_data mt7622_data = {
2681 .caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
2682 .required_clks = MT7622_CLKS_BITMAP,
2683 .required_pctl = false,
2684 };
2685
2686 static const struct mtk_soc_data mt7623_data = {
2687 .caps = MTK_GMAC1_TRGMII,
2688 .required_clks = MT7623_CLKS_BITMAP,
2689 .required_pctl = true,
2690 };
2691
2692 const struct of_device_id of_mtk_match[] = {
2693 { .compatible = "mediatek,mt2701-eth", .data = &mt2701_data},
2694 { .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
2695 { .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
2696 {},
2697 };
2698 MODULE_DEVICE_TABLE(of, of_mtk_match);
2699
2700 static struct platform_driver mtk_driver = {
2701 .probe = mtk_probe,
2702 .remove = mtk_remove,
2703 .driver = {
2704 .name = "mtk_soc_eth",
2705 .of_match_table = of_mtk_match,
2706 },
2707 };
2708
2709 module_platform_driver(mtk_driver);
2710
2711 MODULE_LICENSE("GPL");
2712 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
2713 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux with added FPC-III support