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staging: rtl8188eu: Replace function name in string with __func__
[linux/fpc-iii.git] / drivers / net / ethernet / qlogic / qed / qed_mcp.c
blob6f46cb11f3494c5055c75685eacadd29698dc297
1 /* QLogic qed NIC Driver
2 * Copyright (c) 2015-2017 QLogic Corporation
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and /or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/types.h>
34 #include <asm/byteorder.h>
35 #include <linux/delay.h>
36 #include <linux/errno.h>
37 #include <linux/kernel.h>
38 #include <linux/slab.h>
39 #include <linux/spinlock.h>
40 #include <linux/string.h>
41 #include <linux/etherdevice.h>
42 #include "qed.h"
43 #include "qed_dcbx.h"
44 #include "qed_hsi.h"
45 #include "qed_hw.h"
46 #include "qed_mcp.h"
47 #include "qed_reg_addr.h"
48 #include "qed_sriov.h"
49
50 #define CHIP_MCP_RESP_ITER_US 10
51
52 #define QED_DRV_MB_MAX_RETRIES (500 * 1000) /* Account for 5 sec */
53 #define QED_MCP_RESET_RETRIES (50 * 1000) /* Account for 500 msec */
54
55 #define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
56 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
57 _val)
58
59 #define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
60 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
61
62 #define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
63 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
64 offsetof(struct public_drv_mb, _field), _val)
65
66 #define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
67 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
68 offsetof(struct public_drv_mb, _field))
69
70 #define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
71 DRV_ID_PDA_COMP_VER_SHIFT)
72
73 #define MCP_BYTES_PER_MBIT_SHIFT 17
74
75 bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
76 {
77 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
78 return false;
79 return true;
80 }
81
82 void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
83 {
84 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
85 PUBLIC_PORT);
86 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
87
88 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
89 MFW_PORT(p_hwfn));
90 DP_VERBOSE(p_hwfn, QED_MSG_SP,
91 "port_addr = 0x%x, port_id 0x%02x\n",
92 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
93 }
94
95 void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
96 {
97 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
98 u32 tmp, i;
99
100 if (!p_hwfn->mcp_info->public_base)
101 return;
102
103 for (i = 0; i < length; i++) {
104 tmp = qed_rd(p_hwfn, p_ptt,
105 p_hwfn->mcp_info->mfw_mb_addr +
106 (i << 2) + sizeof(u32));
107
108 /* The MB data is actually BE; Need to force it to cpu */
109 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
110 be32_to_cpu((__force __be32)tmp);
111 }
112 }
113
114 struct qed_mcp_cmd_elem {
115 struct list_head list;
116 struct qed_mcp_mb_params *p_mb_params;
117 u16 expected_seq_num;
118 bool b_is_completed;
119 };
120
121 /* Must be called while cmd_lock is acquired */
122 static struct qed_mcp_cmd_elem *
123 qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
124 struct qed_mcp_mb_params *p_mb_params,
125 u16 expected_seq_num)
126 {
127 struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
128
129 p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
130 if (!p_cmd_elem)
131 goto out;
132
133 p_cmd_elem->p_mb_params = p_mb_params;
134 p_cmd_elem->expected_seq_num = expected_seq_num;
135 list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
136 out:
137 return p_cmd_elem;
138 }
139
140 /* Must be called while cmd_lock is acquired */
141 static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
142 struct qed_mcp_cmd_elem *p_cmd_elem)
143 {
144 list_del(&p_cmd_elem->list);
145 kfree(p_cmd_elem);
146 }
147
148 /* Must be called while cmd_lock is acquired */
149 static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
150 u16 seq_num)
151 {
152 struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
153
154 list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
155 if (p_cmd_elem->expected_seq_num == seq_num)
156 return p_cmd_elem;
157 }
158
159 return NULL;
160 }
161
162 int qed_mcp_free(struct qed_hwfn *p_hwfn)
163 {
164 if (p_hwfn->mcp_info) {
165 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
166
167 kfree(p_hwfn->mcp_info->mfw_mb_cur);
168 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
169
170 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
171 list_for_each_entry_safe(p_cmd_elem,
172 p_tmp,
173 &p_hwfn->mcp_info->cmd_list, list) {
174 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
175 }
176 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
177 }
178
179 kfree(p_hwfn->mcp_info);
180 p_hwfn->mcp_info = NULL;
181
182 return 0;
183 }
184
185 static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
186 {
187 struct qed_mcp_info *p_info = p_hwfn->mcp_info;
188 u32 drv_mb_offsize, mfw_mb_offsize;
189 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
190
191 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
192 if (!p_info->public_base)
193 return 0;
194
195 p_info->public_base |= GRCBASE_MCP;
196
197 /* Calculate the driver and MFW mailbox address */
198 drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
199 SECTION_OFFSIZE_ADDR(p_info->public_base,
200 PUBLIC_DRV_MB));
201 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
202 DP_VERBOSE(p_hwfn, QED_MSG_SP,
203 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
204 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
205
206 /* Set the MFW MB address */
207 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
208 SECTION_OFFSIZE_ADDR(p_info->public_base,
209 PUBLIC_MFW_MB));
210 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
211 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
212
213 /* Get the current driver mailbox sequence before sending
214 * the first command
215 */
216 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
217 DRV_MSG_SEQ_NUMBER_MASK;
218
219 /* Get current FW pulse sequence */
220 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
221 DRV_PULSE_SEQ_MASK;
222
223 p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
224
225 return 0;
226 }
227
228 int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
229 {
230 struct qed_mcp_info *p_info;
231 u32 size;
232
233 /* Allocate mcp_info structure */
234 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
235 if (!p_hwfn->mcp_info)
236 goto err;
237 p_info = p_hwfn->mcp_info;
238
239 /* Initialize the MFW spinlock */
240 spin_lock_init(&p_info->cmd_lock);
241 spin_lock_init(&p_info->link_lock);
242
243 INIT_LIST_HEAD(&p_info->cmd_list);
244
245 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
246 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
247 /* Do not free mcp_info here, since public_base indicate that
248 * the MCP is not initialized
249 */
250 return 0;
251 }
252
253 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
254 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
255 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
256 if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
257 goto err;
258
259 return 0;
260
261 err:
262 qed_mcp_free(p_hwfn);
263 return -ENOMEM;
264 }
265
266 static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
267 struct qed_ptt *p_ptt)
268 {
269 u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
270
271 /* Use MCP history register to check if MCP reset occurred between init
272 * time and now.
273 */
274 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
275 DP_VERBOSE(p_hwfn,
276 QED_MSG_SP,
277 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
278 p_hwfn->mcp_info->mcp_hist, generic_por_0);
279
280 qed_load_mcp_offsets(p_hwfn, p_ptt);
281 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
282 }
283 }
284
285 int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
286 {
287 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
288 int rc = 0;
289
290 /* Ensure that only a single thread is accessing the mailbox */
291 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
292
293 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
294
295 /* Set drv command along with the updated sequence */
296 qed_mcp_reread_offsets(p_hwfn, p_ptt);
297 seq = ++p_hwfn->mcp_info->drv_mb_seq;
298 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
299
300 do {
301 /* Wait for MFW response */
302 udelay(delay);
303 /* Give the FW up to 500 second (50*1000*10usec) */
304 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
305 MISCS_REG_GENERIC_POR_0)) &&
306 (cnt++ < QED_MCP_RESET_RETRIES));
307
308 if (org_mcp_reset_seq !=
309 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
310 DP_VERBOSE(p_hwfn, QED_MSG_SP,
311 "MCP was reset after %d usec\n", cnt * delay);
312 } else {
313 DP_ERR(p_hwfn, "Failed to reset MCP\n");
314 rc = -EAGAIN;
315 }
316
317 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
318
319 return rc;
320 }
321
322 /* Must be called while cmd_lock is acquired */
323 static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
324 {
325 struct qed_mcp_cmd_elem *p_cmd_elem;
326
327 /* There is at most one pending command at a certain time, and if it
328 * exists - it is placed at the HEAD of the list.
329 */
330 if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
331 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
332 struct qed_mcp_cmd_elem, list);
333 return !p_cmd_elem->b_is_completed;
334 }
335
336 return false;
337 }
338
339 /* Must be called while cmd_lock is acquired */
340 static int
341 qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
342 {
343 struct qed_mcp_mb_params *p_mb_params;
344 struct qed_mcp_cmd_elem *p_cmd_elem;
345 u32 mcp_resp;
346 u16 seq_num;
347
348 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
349 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
350
351 /* Return if no new non-handled response has been received */
352 if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
353 return -EAGAIN;
354
355 p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
356 if (!p_cmd_elem) {
357 DP_ERR(p_hwfn,
358 "Failed to find a pending mailbox cmd that expects sequence number %d\n",
359 seq_num);
360 return -EINVAL;
361 }
362
363 p_mb_params = p_cmd_elem->p_mb_params;
364
365 /* Get the MFW response along with the sequence number */
366 p_mb_params->mcp_resp = mcp_resp;
367
368 /* Get the MFW param */
369 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
370
371 /* Get the union data */
372 if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
373 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
374 offsetof(struct public_drv_mb,
375 union_data);
376 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
377 union_data_addr, p_mb_params->data_dst_size);
378 }
379
380 p_cmd_elem->b_is_completed = true;
381
382 return 0;
383 }
384
385 /* Must be called while cmd_lock is acquired */
386 static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
387 struct qed_ptt *p_ptt,
388 struct qed_mcp_mb_params *p_mb_params,
389 u16 seq_num)
390 {
391 union drv_union_data union_data;
392 u32 union_data_addr;
393
394 /* Set the union data */
395 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
396 offsetof(struct public_drv_mb, union_data);
397 memset(&union_data, 0, sizeof(union_data));
398 if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
399 memcpy(&union_data, p_mb_params->p_data_src,
400 p_mb_params->data_src_size);
401 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
402 sizeof(union_data));
403
404 /* Set the drv param */
405 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
406
407 /* Set the drv command along with the sequence number */
408 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
409
410 DP_VERBOSE(p_hwfn, QED_MSG_SP,
411 "MFW mailbox: command 0x%08x param 0x%08x\n",
412 (p_mb_params->cmd | seq_num), p_mb_params->param);
413 }
414
415 static int
416 _qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
417 struct qed_ptt *p_ptt,
418 struct qed_mcp_mb_params *p_mb_params,
419 u32 max_retries, u32 delay)
420 {
421 struct qed_mcp_cmd_elem *p_cmd_elem;
422 u32 cnt = 0;
423 u16 seq_num;
424 int rc = 0;
425
426 /* Wait until the mailbox is non-occupied */
427 do {
428 /* Exit the loop if there is no pending command, or if the
429 * pending command is completed during this iteration.
430 * The spinlock stays locked until the command is sent.
431 */
432
433 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
434
435 if (!qed_mcp_has_pending_cmd(p_hwfn))
436 break;
437
438 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
439 if (!rc)
440 break;
441 else if (rc != -EAGAIN)
442 goto err;
443
444 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
445 udelay(delay);
446 } while (++cnt < max_retries);
447
448 if (cnt >= max_retries) {
449 DP_NOTICE(p_hwfn,
450 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
451 p_mb_params->cmd, p_mb_params->param);
452 return -EAGAIN;
453 }
454
455 /* Send the mailbox command */
456 qed_mcp_reread_offsets(p_hwfn, p_ptt);
457 seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
458 p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
459 if (!p_cmd_elem) {
460 rc = -ENOMEM;
461 goto err;
462 }
463
464 __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
465 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
466
467 /* Wait for the MFW response */
468 do {
469 /* Exit the loop if the command is already completed, or if the
470 * command is completed during this iteration.
471 * The spinlock stays locked until the list element is removed.
472 */
473
474 udelay(delay);
475 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
476
477 if (p_cmd_elem->b_is_completed)
478 break;
479
480 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
481 if (!rc)
482 break;
483 else if (rc != -EAGAIN)
484 goto err;
485
486 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
487 } while (++cnt < max_retries);
488
489 if (cnt >= max_retries) {
490 DP_NOTICE(p_hwfn,
491 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
492 p_mb_params->cmd, p_mb_params->param);
493
494 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
495 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
496 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
497
498 return -EAGAIN;
499 }
500
501 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
502 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
503
504 DP_VERBOSE(p_hwfn,
505 QED_MSG_SP,
506 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
507 p_mb_params->mcp_resp,
508 p_mb_params->mcp_param,
509 (cnt * delay) / 1000, (cnt * delay) % 1000);
510
511 /* Clear the sequence number from the MFW response */
512 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
513
514 return 0;
515
516 err:
517 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
518 return rc;
519 }
520
521 static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
522 struct qed_ptt *p_ptt,
523 struct qed_mcp_mb_params *p_mb_params)
524 {
525 size_t union_data_size = sizeof(union drv_union_data);
526 u32 max_retries = QED_DRV_MB_MAX_RETRIES;
527 u32 delay = CHIP_MCP_RESP_ITER_US;
528
529 /* MCP not initialized */
530 if (!qed_mcp_is_init(p_hwfn)) {
531 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
532 return -EBUSY;
533 }
534
535 if (p_mb_params->data_src_size > union_data_size ||
536 p_mb_params->data_dst_size > union_data_size) {
537 DP_ERR(p_hwfn,
538 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
539 p_mb_params->data_src_size,
540 p_mb_params->data_dst_size, union_data_size);
541 return -EINVAL;
542 }
543
544 return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
545 delay);
546 }
547
548 int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
549 struct qed_ptt *p_ptt,
550 u32 cmd,
551 u32 param,
552 u32 *o_mcp_resp,
553 u32 *o_mcp_param)
554 {
555 struct qed_mcp_mb_params mb_params;
556 int rc;
557
558 memset(&mb_params, 0, sizeof(mb_params));
559 mb_params.cmd = cmd;
560 mb_params.param = param;
561
562 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
563 if (rc)
564 return rc;
565
566 *o_mcp_resp = mb_params.mcp_resp;
567 *o_mcp_param = mb_params.mcp_param;
568
569 return 0;
570 }
571
572 int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
573 struct qed_ptt *p_ptt,
574 u32 cmd,
575 u32 param,
576 u32 *o_mcp_resp,
577 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
578 {
579 struct qed_mcp_mb_params mb_params;
580 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
581 int rc;
582
583 memset(&mb_params, 0, sizeof(mb_params));
584 mb_params.cmd = cmd;
585 mb_params.param = param;
586 mb_params.p_data_dst = raw_data;
587
588 /* Use the maximal value since the actual one is part of the response */
589 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
590
591 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
592 if (rc)
593 return rc;
594
595 *o_mcp_resp = mb_params.mcp_resp;
596 *o_mcp_param = mb_params.mcp_param;
597
598 *o_txn_size = *o_mcp_param;
599 memcpy(o_buf, raw_data, *o_txn_size);
600
601 return 0;
602 }
603
604 static bool
605 qed_mcp_can_force_load(u8 drv_role,
606 u8 exist_drv_role,
607 enum qed_override_force_load override_force_load)
608 {
609 bool can_force_load = false;
610
611 switch (override_force_load) {
612 case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
613 can_force_load = true;
614 break;
615 case QED_OVERRIDE_FORCE_LOAD_NEVER:
616 can_force_load = false;
617 break;
618 default:
619 can_force_load = (drv_role == DRV_ROLE_OS &&
620 exist_drv_role == DRV_ROLE_PREBOOT) ||
621 (drv_role == DRV_ROLE_KDUMP &&
622 exist_drv_role == DRV_ROLE_OS);
623 break;
624 }
625
626 return can_force_load;
627 }
628
629 static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
630 struct qed_ptt *p_ptt)
631 {
632 u32 resp = 0, param = 0;
633 int rc;
634
635 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
636 &resp, &param);
637 if (rc)
638 DP_NOTICE(p_hwfn,
639 "Failed to send cancel load request, rc = %d\n", rc);
640
641 return rc;
642 }
643
644 #define CONFIG_QEDE_BITMAP_IDX BIT(0)
645 #define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1)
646 #define CONFIG_QEDR_BITMAP_IDX BIT(2)
647 #define CONFIG_QEDF_BITMAP_IDX BIT(4)
648 #define CONFIG_QEDI_BITMAP_IDX BIT(5)
649 #define CONFIG_QED_LL2_BITMAP_IDX BIT(6)
650
651 static u32 qed_get_config_bitmap(void)
652 {
653 u32 config_bitmap = 0x0;
654
655 if (IS_ENABLED(CONFIG_QEDE))
656 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
657
658 if (IS_ENABLED(CONFIG_QED_SRIOV))
659 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
660
661 if (IS_ENABLED(CONFIG_QED_RDMA))
662 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
663
664 if (IS_ENABLED(CONFIG_QED_FCOE))
665 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
666
667 if (IS_ENABLED(CONFIG_QED_ISCSI))
668 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
669
670 if (IS_ENABLED(CONFIG_QED_LL2))
671 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
672
673 return config_bitmap;
674 }
675
676 struct qed_load_req_in_params {
677 u8 hsi_ver;
678 #define QED_LOAD_REQ_HSI_VER_DEFAULT 0
679 #define QED_LOAD_REQ_HSI_VER_1 1
680 u32 drv_ver_0;
681 u32 drv_ver_1;
682 u32 fw_ver;
683 u8 drv_role;
684 u8 timeout_val;
685 u8 force_cmd;
686 bool avoid_eng_reset;
687 };
688
689 struct qed_load_req_out_params {
690 u32 load_code;
691 u32 exist_drv_ver_0;
692 u32 exist_drv_ver_1;
693 u32 exist_fw_ver;
694 u8 exist_drv_role;
695 u8 mfw_hsi_ver;
696 bool drv_exists;
697 };
698
699 static int
700 __qed_mcp_load_req(struct qed_hwfn *p_hwfn,
701 struct qed_ptt *p_ptt,
702 struct qed_load_req_in_params *p_in_params,
703 struct qed_load_req_out_params *p_out_params)
704 {
705 struct qed_mcp_mb_params mb_params;
706 struct load_req_stc load_req;
707 struct load_rsp_stc load_rsp;
708 u32 hsi_ver;
709 int rc;
710
711 memset(&load_req, 0, sizeof(load_req));
712 load_req.drv_ver_0 = p_in_params->drv_ver_0;
713 load_req.drv_ver_1 = p_in_params->drv_ver_1;
714 load_req.fw_ver = p_in_params->fw_ver;
715 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
716 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
717 p_in_params->timeout_val);
718 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
719 p_in_params->force_cmd);
720 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
721 p_in_params->avoid_eng_reset);
722
723 hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
724 DRV_ID_MCP_HSI_VER_CURRENT :
725 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
726
727 memset(&mb_params, 0, sizeof(mb_params));
728 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
729 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
730 mb_params.p_data_src = &load_req;
731 mb_params.data_src_size = sizeof(load_req);
732 mb_params.p_data_dst = &load_rsp;
733 mb_params.data_dst_size = sizeof(load_rsp);
734
735 DP_VERBOSE(p_hwfn, QED_MSG_SP,
736 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
737 mb_params.param,
738 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
739 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
740 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
741 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
742
743 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
744 DP_VERBOSE(p_hwfn, QED_MSG_SP,
745 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
746 load_req.drv_ver_0,
747 load_req.drv_ver_1,
748 load_req.fw_ver,
749 load_req.misc0,
750 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
751 QED_MFW_GET_FIELD(load_req.misc0,
752 LOAD_REQ_LOCK_TO),
753 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
754 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
755 }
756
757 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
758 if (rc) {
759 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
760 return rc;
761 }
762
763 DP_VERBOSE(p_hwfn, QED_MSG_SP,
764 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
765 p_out_params->load_code = mb_params.mcp_resp;
766
767 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
768 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
769 DP_VERBOSE(p_hwfn,
770 QED_MSG_SP,
771 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
772 load_rsp.drv_ver_0,
773 load_rsp.drv_ver_1,
774 load_rsp.fw_ver,
775 load_rsp.misc0,
776 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
777 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
778 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
779
780 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
781 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
782 p_out_params->exist_fw_ver = load_rsp.fw_ver;
783 p_out_params->exist_drv_role =
784 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
785 p_out_params->mfw_hsi_ver =
786 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
787 p_out_params->drv_exists =
788 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
789 LOAD_RSP_FLAGS0_DRV_EXISTS;
790 }
791
792 return 0;
793 }
794
795 static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
796 enum qed_drv_role drv_role,
797 u8 *p_mfw_drv_role)
798 {
799 switch (drv_role) {
800 case QED_DRV_ROLE_OS:
801 *p_mfw_drv_role = DRV_ROLE_OS;
802 break;
803 case QED_DRV_ROLE_KDUMP:
804 *p_mfw_drv_role = DRV_ROLE_KDUMP;
805 break;
806 default:
807 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
808 return -EINVAL;
809 }
810
811 return 0;
812 }
813
814 enum qed_load_req_force {
815 QED_LOAD_REQ_FORCE_NONE,
816 QED_LOAD_REQ_FORCE_PF,
817 QED_LOAD_REQ_FORCE_ALL,
818 };
819
820 static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
821
822 enum qed_load_req_force force_cmd,
823 u8 *p_mfw_force_cmd)
824 {
825 switch (force_cmd) {
826 case QED_LOAD_REQ_FORCE_NONE:
827 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
828 break;
829 case QED_LOAD_REQ_FORCE_PF:
830 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
831 break;
832 case QED_LOAD_REQ_FORCE_ALL:
833 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
834 break;
835 }
836 }
837
838 int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
839 struct qed_ptt *p_ptt,
840 struct qed_load_req_params *p_params)
841 {
842 struct qed_load_req_out_params out_params;
843 struct qed_load_req_in_params in_params;
844 u8 mfw_drv_role, mfw_force_cmd;
845 int rc;
846
847 memset(&in_params, 0, sizeof(in_params));
848 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
849 in_params.drv_ver_0 = QED_VERSION;
850 in_params.drv_ver_1 = qed_get_config_bitmap();
851 in_params.fw_ver = STORM_FW_VERSION;
852 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
853 if (rc)
854 return rc;
855
856 in_params.drv_role = mfw_drv_role;
857 in_params.timeout_val = p_params->timeout_val;
858 qed_get_mfw_force_cmd(p_hwfn,
859 QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
860
861 in_params.force_cmd = mfw_force_cmd;
862 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
863
864 memset(&out_params, 0, sizeof(out_params));
865 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
866 if (rc)
867 return rc;
868
869 /* First handle cases where another load request should/might be sent:
870 * - MFW expects the old interface [HSI version = 1]
871 * - MFW responds that a force load request is required
872 */
873 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
874 DP_INFO(p_hwfn,
875 "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
876
877 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
878 memset(&out_params, 0, sizeof(out_params));
879 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
880 if (rc)
881 return rc;
882 } else if (out_params.load_code ==
883 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
884 if (qed_mcp_can_force_load(in_params.drv_role,
885 out_params.exist_drv_role,
886 p_params->override_force_load)) {
887 DP_INFO(p_hwfn,
888 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
889 in_params.drv_role, in_params.fw_ver,
890 in_params.drv_ver_0, in_params.drv_ver_1,
891 out_params.exist_drv_role,
892 out_params.exist_fw_ver,
893 out_params.exist_drv_ver_0,
894 out_params.exist_drv_ver_1);
895
896 qed_get_mfw_force_cmd(p_hwfn,
897 QED_LOAD_REQ_FORCE_ALL,
898 &mfw_force_cmd);
899
900 in_params.force_cmd = mfw_force_cmd;
901 memset(&out_params, 0, sizeof(out_params));
902 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
903 &out_params);
904 if (rc)
905 return rc;
906 } else {
907 DP_NOTICE(p_hwfn,
908 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
909 in_params.drv_role, in_params.fw_ver,
910 in_params.drv_ver_0, in_params.drv_ver_1,
911 out_params.exist_drv_role,
912 out_params.exist_fw_ver,
913 out_params.exist_drv_ver_0,
914 out_params.exist_drv_ver_1);
915 DP_NOTICE(p_hwfn,
916 "Avoid sending a force load request to prevent disruption of active PFs\n");
917
918 qed_mcp_cancel_load_req(p_hwfn, p_ptt);
919 return -EBUSY;
920 }
921 }
922
923 /* Now handle the other types of responses.
924 * The "REFUSED_HSI_1" and "REFUSED_REQUIRES_FORCE" responses are not
925 * expected here after the additional revised load requests were sent.
926 */
927 switch (out_params.load_code) {
928 case FW_MSG_CODE_DRV_LOAD_ENGINE:
929 case FW_MSG_CODE_DRV_LOAD_PORT:
930 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
931 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
932 out_params.drv_exists) {
933 /* The role and fw/driver version match, but the PF is
934 * already loaded and has not been unloaded gracefully.
935 */
936 DP_NOTICE(p_hwfn,
937 "PF is already loaded\n");
938 return -EINVAL;
939 }
940 break;
941 default:
942 DP_NOTICE(p_hwfn,
943 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
944 out_params.load_code);
945 return -EBUSY;
946 }
947
948 p_params->load_code = out_params.load_code;
949
950 return 0;
951 }
952
953 int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
954 {
955 u32 wol_param, mcp_resp, mcp_param;
956
957 switch (p_hwfn->cdev->wol_config) {
958 case QED_OV_WOL_DISABLED:
959 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
960 break;
961 case QED_OV_WOL_ENABLED:
962 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
963 break;
964 default:
965 DP_NOTICE(p_hwfn,
966 "Unknown WoL configuration %02x\n",
967 p_hwfn->cdev->wol_config);
968 /* Fallthrough */
969 case QED_OV_WOL_DEFAULT:
970 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
971 }
972
973 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
974 &mcp_resp, &mcp_param);
975 }
976
977 int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
978 {
979 struct qed_mcp_mb_params mb_params;
980 struct mcp_mac wol_mac;
981
982 memset(&mb_params, 0, sizeof(mb_params));
983 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
984
985 /* Set the primary MAC if WoL is enabled */
986 if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
987 u8 *p_mac = p_hwfn->cdev->wol_mac;
988
989 memset(&wol_mac, 0, sizeof(wol_mac));
990 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
991 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
992 p_mac[4] << 8 | p_mac[5];
993
994 DP_VERBOSE(p_hwfn,
995 (QED_MSG_SP | NETIF_MSG_IFDOWN),
996 "Setting WoL MAC: %pM --> [%08x,%08x]\n",
997 p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
998
999 mb_params.p_data_src = &wol_mac;
1000 mb_params.data_src_size = sizeof(wol_mac);
1001 }
1002
1003 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1004 }
1005
1006 static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1007 struct qed_ptt *p_ptt)
1008 {
1009 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1010 PUBLIC_PATH);
1011 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1012 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1013 QED_PATH_ID(p_hwfn));
1014 u32 disabled_vfs[VF_MAX_STATIC / 32];
1015 int i;
1016
1017 DP_VERBOSE(p_hwfn,
1018 QED_MSG_SP,
1019 "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1020 mfw_path_offsize, path_addr);
1021
1022 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1023 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1024 path_addr +
1025 offsetof(struct public_path,
1026 mcp_vf_disabled) +
1027 sizeof(u32) * i);
1028 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1029 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1030 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1031 }
1032
1033 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1034 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1035 }
1036
1037 int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1038 struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1039 {
1040 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1041 PUBLIC_FUNC);
1042 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1043 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1044 MCP_PF_ID(p_hwfn));
1045 struct qed_mcp_mb_params mb_params;
1046 int rc;
1047 int i;
1048
1049 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1050 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1051 "Acking VFs [%08x,...,%08x] - %08x\n",
1052 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1053
1054 memset(&mb_params, 0, sizeof(mb_params));
1055 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1056 mb_params.p_data_src = vfs_to_ack;
1057 mb_params.data_src_size = VF_MAX_STATIC / 8;
1058 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1059 if (rc) {
1060 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1061 return -EBUSY;
1062 }
1063
1064 /* Clear the ACK bits */
1065 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1066 qed_wr(p_hwfn, p_ptt,
1067 func_addr +
1068 offsetof(struct public_func, drv_ack_vf_disabled) +
1069 i * sizeof(u32), 0);
1070
1071 return rc;
1072 }
1073
1074 static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1075 struct qed_ptt *p_ptt)
1076 {
1077 u32 transceiver_state;
1078
1079 transceiver_state = qed_rd(p_hwfn, p_ptt,
1080 p_hwfn->mcp_info->port_addr +
1081 offsetof(struct public_port,
1082 transceiver_data));
1083
1084 DP_VERBOSE(p_hwfn,
1085 (NETIF_MSG_HW | QED_MSG_SP),
1086 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1087 transceiver_state,
1088 (u32)(p_hwfn->mcp_info->port_addr +
1089 offsetof(struct public_port, transceiver_data)));
1090
1091 transceiver_state = GET_FIELD(transceiver_state,
1092 ETH_TRANSCEIVER_STATE);
1093
1094 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1095 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1096 else
1097 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1098 }
1099
1100 static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1101 struct qed_ptt *p_ptt,
1102 struct qed_mcp_link_state *p_link)
1103 {
1104 u32 eee_status, val;
1105
1106 p_link->eee_adv_caps = 0;
1107 p_link->eee_lp_adv_caps = 0;
1108 eee_status = qed_rd(p_hwfn,
1109 p_ptt,
1110 p_hwfn->mcp_info->port_addr +
1111 offsetof(struct public_port, eee_status));
1112 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1113 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1114 if (val & EEE_1G_ADV)
1115 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1116 if (val & EEE_10G_ADV)
1117 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1118 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1119 if (val & EEE_1G_ADV)
1120 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1121 if (val & EEE_10G_ADV)
1122 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1123 }
1124
1125 static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1126 struct qed_ptt *p_ptt, bool b_reset)
1127 {
1128 struct qed_mcp_link_state *p_link;
1129 u8 max_bw, min_bw;
1130 u32 status = 0;
1131
1132 /* Prevent SW/attentions from doing this at the same time */
1133 spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1134
1135 p_link = &p_hwfn->mcp_info->link_output;
1136 memset(p_link, 0, sizeof(*p_link));
1137 if (!b_reset) {
1138 status = qed_rd(p_hwfn, p_ptt,
1139 p_hwfn->mcp_info->port_addr +
1140 offsetof(struct public_port, link_status));
1141 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1142 "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1143 status,
1144 (u32)(p_hwfn->mcp_info->port_addr +
1145 offsetof(struct public_port, link_status)));
1146 } else {
1147 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1148 "Resetting link indications\n");
1149 goto out;
1150 }
1151
1152 if (p_hwfn->b_drv_link_init)
1153 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1154 else
1155 p_link->link_up = false;
1156
1157 p_link->full_duplex = true;
1158 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1159 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1160 p_link->speed = 100000;
1161 break;
1162 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1163 p_link->speed = 50000;
1164 break;
1165 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1166 p_link->speed = 40000;
1167 break;
1168 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1169 p_link->speed = 25000;
1170 break;
1171 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1172 p_link->speed = 20000;
1173 break;
1174 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1175 p_link->speed = 10000;
1176 break;
1177 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1178 p_link->full_duplex = false;
1179 /* Fall-through */
1180 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1181 p_link->speed = 1000;
1182 break;
1183 default:
1184 p_link->speed = 0;
1185 }
1186
1187 if (p_link->link_up && p_link->speed)
1188 p_link->line_speed = p_link->speed;
1189 else
1190 p_link->line_speed = 0;
1191
1192 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1193 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1194
1195 /* Max bandwidth configuration */
1196 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1197
1198 /* Min bandwidth configuration */
1199 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1200 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1201 p_link->min_pf_rate);
1202
1203 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1204 p_link->an_complete = !!(status &
1205 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1206 p_link->parallel_detection = !!(status &
1207 LINK_STATUS_PARALLEL_DETECTION_USED);
1208 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1209
1210 p_link->partner_adv_speed |=
1211 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1212 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1213 p_link->partner_adv_speed |=
1214 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1215 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1216 p_link->partner_adv_speed |=
1217 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1218 QED_LINK_PARTNER_SPEED_10G : 0;
1219 p_link->partner_adv_speed |=
1220 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1221 QED_LINK_PARTNER_SPEED_20G : 0;
1222 p_link->partner_adv_speed |=
1223 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1224 QED_LINK_PARTNER_SPEED_25G : 0;
1225 p_link->partner_adv_speed |=
1226 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1227 QED_LINK_PARTNER_SPEED_40G : 0;
1228 p_link->partner_adv_speed |=
1229 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1230 QED_LINK_PARTNER_SPEED_50G : 0;
1231 p_link->partner_adv_speed |=
1232 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1233 QED_LINK_PARTNER_SPEED_100G : 0;
1234
1235 p_link->partner_tx_flow_ctrl_en =
1236 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1237 p_link->partner_rx_flow_ctrl_en =
1238 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1239
1240 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1241 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1242 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1243 break;
1244 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1245 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1246 break;
1247 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1248 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1249 break;
1250 default:
1251 p_link->partner_adv_pause = 0;
1252 }
1253
1254 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1255
1256 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1257 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1258
1259 qed_link_update(p_hwfn);
1260 out:
1261 spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1262 }
1263
1264 int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1265 {
1266 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1267 struct qed_mcp_mb_params mb_params;
1268 struct eth_phy_cfg phy_cfg;
1269 int rc = 0;
1270 u32 cmd;
1271
1272 /* Set the shmem configuration according to params */
1273 memset(&phy_cfg, 0, sizeof(phy_cfg));
1274 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1275 if (!params->speed.autoneg)
1276 phy_cfg.speed = params->speed.forced_speed;
1277 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1278 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1279 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1280 phy_cfg.adv_speed = params->speed.advertised_speeds;
1281 phy_cfg.loopback_mode = params->loopback_mode;
1282 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
1283 if (params->eee.enable)
1284 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1285 if (params->eee.tx_lpi_enable)
1286 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1287 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1288 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1289 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1290 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1291 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1292 EEE_TX_TIMER_USEC_OFFSET) &
1293 EEE_TX_TIMER_USEC_MASK;
1294 }
1295
1296 p_hwfn->b_drv_link_init = b_up;
1297
1298 if (b_up) {
1299 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1300 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1301 phy_cfg.speed,
1302 phy_cfg.pause,
1303 phy_cfg.adv_speed,
1304 phy_cfg.loopback_mode,
1305 phy_cfg.feature_config_flags);
1306 } else {
1307 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1308 "Resetting link\n");
1309 }
1310
1311 memset(&mb_params, 0, sizeof(mb_params));
1312 mb_params.cmd = cmd;
1313 mb_params.p_data_src = &phy_cfg;
1314 mb_params.data_src_size = sizeof(phy_cfg);
1315 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1316
1317 /* if mcp fails to respond we must abort */
1318 if (rc) {
1319 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1320 return rc;
1321 }
1322
1323 /* Mimic link-change attention, done for several reasons:
1324 * - On reset, there's no guarantee MFW would trigger
1325 * an attention.
1326 * - On initialization, older MFWs might not indicate link change
1327 * during LFA, so we'll never get an UP indication.
1328 */
1329 qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1330
1331 return 0;
1332 }
1333
1334 static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1335 struct qed_ptt *p_ptt,
1336 enum MFW_DRV_MSG_TYPE type)
1337 {
1338 enum qed_mcp_protocol_type stats_type;
1339 union qed_mcp_protocol_stats stats;
1340 struct qed_mcp_mb_params mb_params;
1341 u32 hsi_param;
1342
1343 switch (type) {
1344 case MFW_DRV_MSG_GET_LAN_STATS:
1345 stats_type = QED_MCP_LAN_STATS;
1346 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1347 break;
1348 case MFW_DRV_MSG_GET_FCOE_STATS:
1349 stats_type = QED_MCP_FCOE_STATS;
1350 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1351 break;
1352 case MFW_DRV_MSG_GET_ISCSI_STATS:
1353 stats_type = QED_MCP_ISCSI_STATS;
1354 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1355 break;
1356 case MFW_DRV_MSG_GET_RDMA_STATS:
1357 stats_type = QED_MCP_RDMA_STATS;
1358 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1359 break;
1360 default:
1361 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1362 return;
1363 }
1364
1365 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1366
1367 memset(&mb_params, 0, sizeof(mb_params));
1368 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1369 mb_params.param = hsi_param;
1370 mb_params.p_data_src = &stats;
1371 mb_params.data_src_size = sizeof(stats);
1372 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1373 }
1374
1375 static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1376 struct public_func *p_shmem_info)
1377 {
1378 struct qed_mcp_function_info *p_info;
1379
1380 p_info = &p_hwfn->mcp_info->func_info;
1381
1382 p_info->bandwidth_min = (p_shmem_info->config &
1383 FUNC_MF_CFG_MIN_BW_MASK) >>
1384 FUNC_MF_CFG_MIN_BW_SHIFT;
1385 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1386 DP_INFO(p_hwfn,
1387 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1388 p_info->bandwidth_min);
1389 p_info->bandwidth_min = 1;
1390 }
1391
1392 p_info->bandwidth_max = (p_shmem_info->config &
1393 FUNC_MF_CFG_MAX_BW_MASK) >>
1394 FUNC_MF_CFG_MAX_BW_SHIFT;
1395 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1396 DP_INFO(p_hwfn,
1397 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1398 p_info->bandwidth_max);
1399 p_info->bandwidth_max = 100;
1400 }
1401 }
1402
1403 static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1404 struct qed_ptt *p_ptt,
1405 struct public_func *p_data, int pfid)
1406 {
1407 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1408 PUBLIC_FUNC);
1409 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1410 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1411 u32 i, size;
1412
1413 memset(p_data, 0, sizeof(*p_data));
1414
1415 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1416 for (i = 0; i < size / sizeof(u32); i++)
1417 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1418 func_addr + (i << 2));
1419 return size;
1420 }
1421
1422 static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1423 {
1424 struct qed_mcp_function_info *p_info;
1425 struct public_func shmem_info;
1426 u32 resp = 0, param = 0;
1427
1428 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1429
1430 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1431
1432 p_info = &p_hwfn->mcp_info->func_info;
1433
1434 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1435 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1436
1437 /* Acknowledge the MFW */
1438 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1439 &param);
1440 }
1441
1442 static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1443 {
1444 struct public_func shmem_info;
1445 u32 resp = 0, param = 0;
1446
1447 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1448
1449 p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1450 FUNC_MF_CFG_OV_STAG_MASK;
1451 p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1452 if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) &&
1453 (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) {
1454 qed_wr(p_hwfn, p_ptt,
1455 NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan);
1456 qed_sp_pf_update_stag(p_hwfn);
1457 }
1458
1459 /* Acknowledge the MFW */
1460 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1461 &resp, &param);
1462 }
1463
1464 int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1465 struct qed_ptt *p_ptt)
1466 {
1467 struct qed_mcp_info *info = p_hwfn->mcp_info;
1468 int rc = 0;
1469 bool found = false;
1470 u16 i;
1471
1472 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1473
1474 /* Read Messages from MFW */
1475 qed_mcp_read_mb(p_hwfn, p_ptt);
1476
1477 /* Compare current messages to old ones */
1478 for (i = 0; i < info->mfw_mb_length; i++) {
1479 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1480 continue;
1481
1482 found = true;
1483
1484 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1485 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1486 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1487
1488 switch (i) {
1489 case MFW_DRV_MSG_LINK_CHANGE:
1490 qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1491 break;
1492 case MFW_DRV_MSG_VF_DISABLED:
1493 qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1494 break;
1495 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1496 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1497 QED_DCBX_REMOTE_LLDP_MIB);
1498 break;
1499 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1500 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1501 QED_DCBX_REMOTE_MIB);
1502 break;
1503 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1504 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1505 QED_DCBX_OPERATIONAL_MIB);
1506 break;
1507 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1508 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1509 break;
1510 case MFW_DRV_MSG_GET_LAN_STATS:
1511 case MFW_DRV_MSG_GET_FCOE_STATS:
1512 case MFW_DRV_MSG_GET_ISCSI_STATS:
1513 case MFW_DRV_MSG_GET_RDMA_STATS:
1514 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1515 break;
1516 case MFW_DRV_MSG_BW_UPDATE:
1517 qed_mcp_update_bw(p_hwfn, p_ptt);
1518 break;
1519 case MFW_DRV_MSG_S_TAG_UPDATE:
1520 qed_mcp_update_stag(p_hwfn, p_ptt);
1521 break;
1522 break;
1523 default:
1524 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1525 rc = -EINVAL;
1526 }
1527 }
1528
1529 /* ACK everything */
1530 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1531 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1532
1533 /* MFW expect answer in BE, so we force write in that format */
1534 qed_wr(p_hwfn, p_ptt,
1535 info->mfw_mb_addr + sizeof(u32) +
1536 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1537 sizeof(u32) + i * sizeof(u32),
1538 (__force u32)val);
1539 }
1540
1541 if (!found) {
1542 DP_NOTICE(p_hwfn,
1543 "Received an MFW message indication but no new message!\n");
1544 rc = -EINVAL;
1545 }
1546
1547 /* Copy the new mfw messages into the shadow */
1548 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1549
1550 return rc;
1551 }
1552
1553 int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1554 struct qed_ptt *p_ptt,
1555 u32 *p_mfw_ver, u32 *p_running_bundle_id)
1556 {
1557 u32 global_offsize;
1558
1559 if (IS_VF(p_hwfn->cdev)) {
1560 if (p_hwfn->vf_iov_info) {
1561 struct pfvf_acquire_resp_tlv *p_resp;
1562
1563 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1564 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1565 return 0;
1566 } else {
1567 DP_VERBOSE(p_hwfn,
1568 QED_MSG_IOV,
1569 "VF requested MFW version prior to ACQUIRE\n");
1570 return -EINVAL;
1571 }
1572 }
1573
1574 global_offsize = qed_rd(p_hwfn, p_ptt,
1575 SECTION_OFFSIZE_ADDR(p_hwfn->
1576 mcp_info->public_base,
1577 PUBLIC_GLOBAL));
1578 *p_mfw_ver =
1579 qed_rd(p_hwfn, p_ptt,
1580 SECTION_ADDR(global_offsize,
1581 0) + offsetof(struct public_global, mfw_ver));
1582
1583 if (p_running_bundle_id != NULL) {
1584 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1585 SECTION_ADDR(global_offsize, 0) +
1586 offsetof(struct public_global,
1587 running_bundle_id));
1588 }
1589
1590 return 0;
1591 }
1592
1593 int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
1594 struct qed_ptt *p_ptt, u32 *p_mbi_ver)
1595 {
1596 u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
1597
1598 if (IS_VF(p_hwfn->cdev))
1599 return -EINVAL;
1600
1601 /* Read the address of the nvm_cfg */
1602 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1603 if (!nvm_cfg_addr) {
1604 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1605 return -EINVAL;
1606 }
1607
1608 /* Read the offset of nvm_cfg1 */
1609 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1610
1611 mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1612 offsetof(struct nvm_cfg1, glob) +
1613 offsetof(struct nvm_cfg1_glob, mbi_version);
1614 *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
1615 mbi_ver_addr) &
1616 (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
1617 NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
1618 NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
1619
1620 return 0;
1621 }
1622
1623 int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1624 {
1625 struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1626 struct qed_ptt *p_ptt;
1627
1628 if (IS_VF(cdev))
1629 return -EINVAL;
1630
1631 if (!qed_mcp_is_init(p_hwfn)) {
1632 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1633 return -EBUSY;
1634 }
1635
1636 *p_media_type = MEDIA_UNSPECIFIED;
1637
1638 p_ptt = qed_ptt_acquire(p_hwfn);
1639 if (!p_ptt)
1640 return -EBUSY;
1641
1642 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1643 offsetof(struct public_port, media_type));
1644
1645 qed_ptt_release(p_hwfn, p_ptt);
1646
1647 return 0;
1648 }
1649
1650 /* Old MFW has a global configuration for all PFs regarding RDMA support */
1651 static void
1652 qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1653 enum qed_pci_personality *p_proto)
1654 {
1655 /* There wasn't ever a legacy MFW that published iwarp.
1656 * So at this point, this is either plain l2 or RoCE.
1657 */
1658 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1659 *p_proto = QED_PCI_ETH_ROCE;
1660 else
1661 *p_proto = QED_PCI_ETH;
1662
1663 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1664 "According to Legacy capabilities, L2 personality is %08x\n",
1665 (u32) *p_proto);
1666 }
1667
1668 static int
1669 qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1670 struct qed_ptt *p_ptt,
1671 enum qed_pci_personality *p_proto)
1672 {
1673 u32 resp = 0, param = 0;
1674 int rc;
1675
1676 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1677 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, &param);
1678 if (rc)
1679 return rc;
1680 if (resp != FW_MSG_CODE_OK) {
1681 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1682 "MFW lacks support for command; Returns %08x\n",
1683 resp);
1684 return -EINVAL;
1685 }
1686
1687 switch (param) {
1688 case FW_MB_PARAM_GET_PF_RDMA_NONE:
1689 *p_proto = QED_PCI_ETH;
1690 break;
1691 case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1692 *p_proto = QED_PCI_ETH_ROCE;
1693 break;
1694 case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1695 *p_proto = QED_PCI_ETH_IWARP;
1696 break;
1697 case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1698 *p_proto = QED_PCI_ETH_RDMA;
1699 break;
1700 default:
1701 DP_NOTICE(p_hwfn,
1702 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1703 param);
1704 return -EINVAL;
1705 }
1706
1707 DP_VERBOSE(p_hwfn,
1708 NETIF_MSG_IFUP,
1709 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1710 (u32) *p_proto, resp, param);
1711 return 0;
1712 }
1713
1714 static int
1715 qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1716 struct public_func *p_info,
1717 struct qed_ptt *p_ptt,
1718 enum qed_pci_personality *p_proto)
1719 {
1720 int rc = 0;
1721
1722 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1723 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1724 if (!IS_ENABLED(CONFIG_QED_RDMA))
1725 *p_proto = QED_PCI_ETH;
1726 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1727 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1728 break;
1729 case FUNC_MF_CFG_PROTOCOL_ISCSI:
1730 *p_proto = QED_PCI_ISCSI;
1731 break;
1732 case FUNC_MF_CFG_PROTOCOL_FCOE:
1733 *p_proto = QED_PCI_FCOE;
1734 break;
1735 case FUNC_MF_CFG_PROTOCOL_ROCE:
1736 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1737 /* Fallthrough */
1738 default:
1739 rc = -EINVAL;
1740 }
1741
1742 return rc;
1743 }
1744
1745 int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1746 struct qed_ptt *p_ptt)
1747 {
1748 struct qed_mcp_function_info *info;
1749 struct public_func shmem_info;
1750
1751 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1752 info = &p_hwfn->mcp_info->func_info;
1753
1754 info->pause_on_host = (shmem_info.config &
1755 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1756
1757 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1758 &info->protocol)) {
1759 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1760 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1761 return -EINVAL;
1762 }
1763
1764 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1765
1766 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1767 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1768 info->mac[1] = (u8)(shmem_info.mac_upper);
1769 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1770 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1771 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1772 info->mac[5] = (u8)(shmem_info.mac_lower);
1773
1774 /* Store primary MAC for later possible WoL */
1775 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
1776 } else {
1777 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1778 }
1779
1780 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
1781 (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
1782 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
1783 (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
1784
1785 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1786
1787 info->mtu = (u16)shmem_info.mtu_size;
1788
1789 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
1790 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
1791 if (qed_mcp_is_init(p_hwfn)) {
1792 u32 resp = 0, param = 0;
1793 int rc;
1794
1795 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1796 DRV_MSG_CODE_OS_WOL, 0, &resp, &param);
1797 if (rc)
1798 return rc;
1799 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
1800 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
1801 }
1802
1803 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1804 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
1805 info->pause_on_host, info->protocol,
1806 info->bandwidth_min, info->bandwidth_max,
1807 info->mac[0], info->mac[1], info->mac[2],
1808 info->mac[3], info->mac[4], info->mac[5],
1809 info->wwn_port, info->wwn_node,
1810 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
1811
1812 return 0;
1813 }
1814
1815 struct qed_mcp_link_params
1816 *qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1817 {
1818 if (!p_hwfn || !p_hwfn->mcp_info)
1819 return NULL;
1820 return &p_hwfn->mcp_info->link_input;
1821 }
1822
1823 struct qed_mcp_link_state
1824 *qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1825 {
1826 if (!p_hwfn || !p_hwfn->mcp_info)
1827 return NULL;
1828 return &p_hwfn->mcp_info->link_output;
1829 }
1830
1831 struct qed_mcp_link_capabilities
1832 *qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1833 {
1834 if (!p_hwfn || !p_hwfn->mcp_info)
1835 return NULL;
1836 return &p_hwfn->mcp_info->link_capabilities;
1837 }
1838
1839 int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1840 {
1841 u32 resp = 0, param = 0;
1842 int rc;
1843
1844 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1845 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
1846
1847 /* Wait for the drain to complete before returning */
1848 msleep(1020);
1849
1850 return rc;
1851 }
1852
1853 int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1854 struct qed_ptt *p_ptt, u32 *p_flash_size)
1855 {
1856 u32 flash_size;
1857
1858 if (IS_VF(p_hwfn->cdev))
1859 return -EINVAL;
1860
1861 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1862 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1863 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1864 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1865
1866 *p_flash_size = flash_size;
1867
1868 return 0;
1869 }
1870
1871 static int
1872 qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
1873 struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1874 {
1875 u32 resp = 0, param = 0, rc_param = 0;
1876 int rc;
1877
1878 /* Only Leader can configure MSIX, and need to take CMT into account */
1879 if (!IS_LEAD_HWFN(p_hwfn))
1880 return 0;
1881 num *= p_hwfn->cdev->num_hwfns;
1882
1883 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1884 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1885 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1886 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1887
1888 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1889 &resp, &rc_param);
1890
1891 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1892 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1893 rc = -EINVAL;
1894 } else {
1895 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1896 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1897 num, vf_id);
1898 }
1899
1900 return rc;
1901 }
1902
1903 static int
1904 qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
1905 struct qed_ptt *p_ptt, u8 num)
1906 {
1907 u32 resp = 0, param = num, rc_param = 0;
1908 int rc;
1909
1910 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
1911 param, &resp, &rc_param);
1912
1913 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
1914 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
1915 rc = -EINVAL;
1916 } else {
1917 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1918 "Requested 0x%02x MSI-x interrupts for VFs\n", num);
1919 }
1920
1921 return rc;
1922 }
1923
1924 int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
1925 struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1926 {
1927 if (QED_IS_BB(p_hwfn->cdev))
1928 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
1929 else
1930 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
1931 }
1932
1933 int
1934 qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1935 struct qed_ptt *p_ptt,
1936 struct qed_mcp_drv_version *p_ver)
1937 {
1938 struct qed_mcp_mb_params mb_params;
1939 struct drv_version_stc drv_version;
1940 __be32 val;
1941 u32 i;
1942 int rc;
1943
1944 memset(&drv_version, 0, sizeof(drv_version));
1945 drv_version.version = p_ver->version;
1946 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
1947 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
1948 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
1949 }
1950
1951 memset(&mb_params, 0, sizeof(mb_params));
1952 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1953 mb_params.p_data_src = &drv_version;
1954 mb_params.data_src_size = sizeof(drv_version);
1955 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1956 if (rc)
1957 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1958
1959 return rc;
1960 }
1961
1962 int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1963 {
1964 u32 resp = 0, param = 0;
1965 int rc;
1966
1967 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1968 &param);
1969 if (rc)
1970 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1971
1972 return rc;
1973 }
1974
1975 int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1976 {
1977 u32 value, cpu_mode;
1978
1979 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
1980
1981 value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1982 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
1983 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
1984 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
1985
1986 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
1987 }
1988
1989 int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
1990 struct qed_ptt *p_ptt,
1991 enum qed_ov_client client)
1992 {
1993 u32 resp = 0, param = 0;
1994 u32 drv_mb_param;
1995 int rc;
1996
1997 switch (client) {
1998 case QED_OV_CLIENT_DRV:
1999 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2000 break;
2001 case QED_OV_CLIENT_USER:
2002 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2003 break;
2004 case QED_OV_CLIENT_VENDOR_SPEC:
2005 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2006 break;
2007 default:
2008 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2009 return -EINVAL;
2010 }
2011
2012 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2013 drv_mb_param, &resp, &param);
2014 if (rc)
2015 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2016
2017 return rc;
2018 }
2019
2020 int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2021 struct qed_ptt *p_ptt,
2022 enum qed_ov_driver_state drv_state)
2023 {
2024 u32 resp = 0, param = 0;
2025 u32 drv_mb_param;
2026 int rc;
2027
2028 switch (drv_state) {
2029 case QED_OV_DRIVER_STATE_NOT_LOADED:
2030 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2031 break;
2032 case QED_OV_DRIVER_STATE_DISABLED:
2033 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2034 break;
2035 case QED_OV_DRIVER_STATE_ACTIVE:
2036 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2037 break;
2038 default:
2039 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2040 return -EINVAL;
2041 }
2042
2043 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2044 drv_mb_param, &resp, &param);
2045 if (rc)
2046 DP_ERR(p_hwfn, "Failed to send driver state\n");
2047
2048 return rc;
2049 }
2050
2051 int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2052 struct qed_ptt *p_ptt, u16 mtu)
2053 {
2054 u32 resp = 0, param = 0;
2055 u32 drv_mb_param;
2056 int rc;
2057
2058 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2059 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2060 drv_mb_param, &resp, &param);
2061 if (rc)
2062 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2063
2064 return rc;
2065 }
2066
2067 int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2068 struct qed_ptt *p_ptt, u8 *mac)
2069 {
2070 struct qed_mcp_mb_params mb_params;
2071 u32 mfw_mac[2];
2072 int rc;
2073
2074 memset(&mb_params, 0, sizeof(mb_params));
2075 mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2076 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2077 DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2078 mb_params.param |= MCP_PF_ID(p_hwfn);
2079
2080 /* MCP is BE, and on LE platforms PCI would swap access to SHMEM
2081 * in 32-bit granularity.
2082 * So the MAC has to be set in native order [and not byte order],
2083 * otherwise it would be read incorrectly by MFW after swap.
2084 */
2085 mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2086 mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2087
2088 mb_params.p_data_src = (u8 *)mfw_mac;
2089 mb_params.data_src_size = 8;
2090 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2091 if (rc)
2092 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2093
2094 /* Store primary MAC for later possible WoL */
2095 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2096
2097 return rc;
2098 }
2099
2100 int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2101 struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2102 {
2103 u32 resp = 0, param = 0;
2104 u32 drv_mb_param;
2105 int rc;
2106
2107 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2108 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2109 "Can't change WoL configuration when WoL isn't supported\n");
2110 return -EINVAL;
2111 }
2112
2113 switch (wol) {
2114 case QED_OV_WOL_DEFAULT:
2115 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2116 break;
2117 case QED_OV_WOL_DISABLED:
2118 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2119 break;
2120 case QED_OV_WOL_ENABLED:
2121 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2122 break;
2123 default:
2124 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2125 return -EINVAL;
2126 }
2127
2128 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2129 drv_mb_param, &resp, &param);
2130 if (rc)
2131 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2132
2133 /* Store the WoL update for a future unload */
2134 p_hwfn->cdev->wol_config = (u8)wol;
2135
2136 return rc;
2137 }
2138
2139 int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2140 struct qed_ptt *p_ptt,
2141 enum qed_ov_eswitch eswitch)
2142 {
2143 u32 resp = 0, param = 0;
2144 u32 drv_mb_param;
2145 int rc;
2146
2147 switch (eswitch) {
2148 case QED_OV_ESWITCH_NONE:
2149 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2150 break;
2151 case QED_OV_ESWITCH_VEB:
2152 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2153 break;
2154 case QED_OV_ESWITCH_VEPA:
2155 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2156 break;
2157 default:
2158 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2159 return -EINVAL;
2160 }
2161
2162 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2163 drv_mb_param, &resp, &param);
2164 if (rc)
2165 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2166
2167 return rc;
2168 }
2169
2170 int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2171 struct qed_ptt *p_ptt, enum qed_led_mode mode)
2172 {
2173 u32 resp = 0, param = 0, drv_mb_param;
2174 int rc;
2175
2176 switch (mode) {
2177 case QED_LED_MODE_ON:
2178 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2179 break;
2180 case QED_LED_MODE_OFF:
2181 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2182 break;
2183 case QED_LED_MODE_RESTORE:
2184 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2185 break;
2186 default:
2187 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2188 return -EINVAL;
2189 }
2190
2191 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2192 drv_mb_param, &resp, &param);
2193
2194 return rc;
2195 }
2196
2197 int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2198 struct qed_ptt *p_ptt, u32 mask_parities)
2199 {
2200 u32 resp = 0, param = 0;
2201 int rc;
2202
2203 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2204 mask_parities, &resp, &param);
2205
2206 if (rc) {
2207 DP_ERR(p_hwfn,
2208 "MCP response failure for mask parities, aborting\n");
2209 } else if (resp != FW_MSG_CODE_OK) {
2210 DP_ERR(p_hwfn,
2211 "MCP did not acknowledge mask parity request. Old MFW?\n");
2212 rc = -EINVAL;
2213 }
2214
2215 return rc;
2216 }
2217
2218 int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2219 {
2220 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2221 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2222 u32 resp = 0, resp_param = 0;
2223 struct qed_ptt *p_ptt;
2224 int rc = 0;
2225
2226 p_ptt = qed_ptt_acquire(p_hwfn);
2227 if (!p_ptt)
2228 return -EBUSY;
2229
2230 while (bytes_left > 0) {
2231 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2232
2233 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2234 DRV_MSG_CODE_NVM_READ_NVRAM,
2235 addr + offset +
2236 (bytes_to_copy <<
2237 DRV_MB_PARAM_NVM_LEN_OFFSET),
2238 &resp, &resp_param,
2239 &read_len,
2240 (u32 *)(p_buf + offset));
2241
2242 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2243 DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2244 break;
2245 }
2246
2247 /* This can be a lengthy process, and it's possible scheduler
2248 * isn't preemptable. Sleep a bit to prevent CPU hogging.
2249 */
2250 if (bytes_left % 0x1000 <
2251 (bytes_left - read_len) % 0x1000)
2252 usleep_range(1000, 2000);
2253
2254 offset += read_len;
2255 bytes_left -= read_len;
2256 }
2257
2258 cdev->mcp_nvm_resp = resp;
2259 qed_ptt_release(p_hwfn, p_ptt);
2260
2261 return rc;
2262 }
2263
2264 int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2265 {
2266 u32 drv_mb_param = 0, rsp, param;
2267 int rc = 0;
2268
2269 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2270 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2271
2272 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2273 drv_mb_param, &rsp, &param);
2274
2275 if (rc)
2276 return rc;
2277
2278 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2279 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2280 rc = -EAGAIN;
2281
2282 return rc;
2283 }
2284
2285 int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2286 {
2287 u32 drv_mb_param, rsp, param;
2288 int rc = 0;
2289
2290 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2291 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2292
2293 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2294 drv_mb_param, &rsp, &param);
2295
2296 if (rc)
2297 return rc;
2298
2299 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2300 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2301 rc = -EAGAIN;
2302
2303 return rc;
2304 }
2305
2306 int qed_mcp_bist_nvm_test_get_num_images(struct qed_hwfn *p_hwfn,
2307 struct qed_ptt *p_ptt,
2308 u32 *num_images)
2309 {
2310 u32 drv_mb_param = 0, rsp;
2311 int rc = 0;
2312
2313 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2314 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2315
2316 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2317 drv_mb_param, &rsp, num_images);
2318 if (rc)
2319 return rc;
2320
2321 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2322 rc = -EINVAL;
2323
2324 return rc;
2325 }
2326
2327 int qed_mcp_bist_nvm_test_get_image_att(struct qed_hwfn *p_hwfn,
2328 struct qed_ptt *p_ptt,
2329 struct bist_nvm_image_att *p_image_att,
2330 u32 image_index)
2331 {
2332 u32 buf_size = 0, param, resp = 0, resp_param = 0;
2333 int rc;
2334
2335 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2336 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2337 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2338
2339 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2340 DRV_MSG_CODE_BIST_TEST, param,
2341 &resp, &resp_param,
2342 &buf_size,
2343 (u32 *)p_image_att);
2344 if (rc)
2345 return rc;
2346
2347 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2348 (p_image_att->return_code != 1))
2349 rc = -EINVAL;
2350
2351 return rc;
2352 }
2353
2354 static int
2355 qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
2356 struct qed_ptt *p_ptt,
2357 enum qed_nvm_images image_id,
2358 struct qed_nvm_image_att *p_image_att)
2359 {
2360 struct bist_nvm_image_att mfw_image_att;
2361 enum nvm_image_type type;
2362 u32 num_images, i;
2363 int rc;
2364
2365 /* Translate image_id into MFW definitions */
2366 switch (image_id) {
2367 case QED_NVM_IMAGE_ISCSI_CFG:
2368 type = NVM_TYPE_ISCSI_CFG;
2369 break;
2370 case QED_NVM_IMAGE_FCOE_CFG:
2371 type = NVM_TYPE_FCOE_CFG;
2372 break;
2373 default:
2374 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
2375 image_id);
2376 return -EINVAL;
2377 }
2378
2379 /* Learn number of images, then traverse and see if one fits */
2380 rc = qed_mcp_bist_nvm_test_get_num_images(p_hwfn, p_ptt, &num_images);
2381 if (rc || !num_images)
2382 return -EINVAL;
2383
2384 for (i = 0; i < num_images; i++) {
2385 rc = qed_mcp_bist_nvm_test_get_image_att(p_hwfn, p_ptt,
2386 &mfw_image_att, i);
2387 if (rc)
2388 return rc;
2389
2390 if (type == mfw_image_att.image_type)
2391 break;
2392 }
2393 if (i == num_images) {
2394 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2395 "Failed to find nvram image of type %08x\n",
2396 image_id);
2397 return -EINVAL;
2398 }
2399
2400 p_image_att->start_addr = mfw_image_att.nvm_start_addr;
2401 p_image_att->length = mfw_image_att.len;
2402
2403 return 0;
2404 }
2405
2406 int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
2407 struct qed_ptt *p_ptt,
2408 enum qed_nvm_images image_id,
2409 u8 *p_buffer, u32 buffer_len)
2410 {
2411 struct qed_nvm_image_att image_att;
2412 int rc;
2413
2414 memset(p_buffer, 0, buffer_len);
2415
2416 rc = qed_mcp_get_nvm_image_att(p_hwfn, p_ptt, image_id, &image_att);
2417 if (rc)
2418 return rc;
2419
2420 /* Validate sizes - both the image's and the supplied buffer's */
2421 if (image_att.length <= 4) {
2422 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2423 "Image [%d] is too small - only %d bytes\n",
2424 image_id, image_att.length);
2425 return -EINVAL;
2426 }
2427
2428 /* Each NVM image is suffixed by CRC; Upper-layer has no need for it */
2429 image_att.length -= 4;
2430
2431 if (image_att.length > buffer_len) {
2432 DP_VERBOSE(p_hwfn,
2433 QED_MSG_STORAGE,
2434 "Image [%d] is too big - %08x bytes where only %08x are available\n",
2435 image_id, image_att.length, buffer_len);
2436 return -ENOMEM;
2437 }
2438
2439 return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
2440 p_buffer, image_att.length);
2441 }
2442
2443 static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2444 {
2445 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2446
2447 switch (res_id) {
2448 case QED_SB:
2449 mfw_res_id = RESOURCE_NUM_SB_E;
2450 break;
2451 case QED_L2_QUEUE:
2452 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2453 break;
2454 case QED_VPORT:
2455 mfw_res_id = RESOURCE_NUM_VPORT_E;
2456 break;
2457 case QED_RSS_ENG:
2458 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2459 break;
2460 case QED_PQ:
2461 mfw_res_id = RESOURCE_NUM_PQ_E;
2462 break;
2463 case QED_RL:
2464 mfw_res_id = RESOURCE_NUM_RL_E;
2465 break;
2466 case QED_MAC:
2467 case QED_VLAN:
2468 /* Each VFC resource can accommodate both a MAC and a VLAN */
2469 mfw_res_id = RESOURCE_VFC_FILTER_E;
2470 break;
2471 case QED_ILT:
2472 mfw_res_id = RESOURCE_ILT_E;
2473 break;
2474 case QED_LL2_QUEUE:
2475 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2476 break;
2477 case QED_RDMA_CNQ_RAM:
2478 case QED_CMDQS_CQS:
2479 /* CNQ/CMDQS are the same resource */
2480 mfw_res_id = RESOURCE_CQS_E;
2481 break;
2482 case QED_RDMA_STATS_QUEUE:
2483 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2484 break;
2485 case QED_BDQ:
2486 mfw_res_id = RESOURCE_BDQ_E;
2487 break;
2488 default:
2489 break;
2490 }
2491
2492 return mfw_res_id;
2493 }
2494
2495 #define QED_RESC_ALLOC_VERSION_MAJOR 2
2496 #define QED_RESC_ALLOC_VERSION_MINOR 0
2497 #define QED_RESC_ALLOC_VERSION \
2498 ((QED_RESC_ALLOC_VERSION_MAJOR << \
2499 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2500 (QED_RESC_ALLOC_VERSION_MINOR << \
2501 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2502
2503 struct qed_resc_alloc_in_params {
2504 u32 cmd;
2505 enum qed_resources res_id;
2506 u32 resc_max_val;
2507 };
2508
2509 struct qed_resc_alloc_out_params {
2510 u32 mcp_resp;
2511 u32 mcp_param;
2512 u32 resc_num;
2513 u32 resc_start;
2514 u32 vf_resc_num;
2515 u32 vf_resc_start;
2516 u32 flags;
2517 };
2518
2519 static int
2520 qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
2521 struct qed_ptt *p_ptt,
2522 struct qed_resc_alloc_in_params *p_in_params,
2523 struct qed_resc_alloc_out_params *p_out_params)
2524 {
2525 struct qed_mcp_mb_params mb_params;
2526 struct resource_info mfw_resc_info;
2527 int rc;
2528
2529 memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
2530
2531 mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
2532 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2533 DP_ERR(p_hwfn,
2534 "Failed to match resource %d [%s] with the MFW resources\n",
2535 p_in_params->res_id,
2536 qed_hw_get_resc_name(p_in_params->res_id));
2537 return -EINVAL;
2538 }
2539
2540 switch (p_in_params->cmd) {
2541 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2542 mfw_resc_info.size = p_in_params->resc_max_val;
2543 /* Fallthrough */
2544 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2545 break;
2546 default:
2547 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2548 p_in_params->cmd);
2549 return -EINVAL;
2550 }
2551
2552 memset(&mb_params, 0, sizeof(mb_params));
2553 mb_params.cmd = p_in_params->cmd;
2554 mb_params.param = QED_RESC_ALLOC_VERSION;
2555 mb_params.p_data_src = &mfw_resc_info;
2556 mb_params.data_src_size = sizeof(mfw_resc_info);
2557 mb_params.p_data_dst = mb_params.p_data_src;
2558 mb_params.data_dst_size = mb_params.data_src_size;
2559
2560 DP_VERBOSE(p_hwfn,
2561 QED_MSG_SP,
2562 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2563 p_in_params->cmd,
2564 p_in_params->res_id,
2565 qed_hw_get_resc_name(p_in_params->res_id),
2566 QED_MFW_GET_FIELD(mb_params.param,
2567 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2568 QED_MFW_GET_FIELD(mb_params.param,
2569 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2570 p_in_params->resc_max_val);
2571
2572 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2573 if (rc)
2574 return rc;
2575
2576 p_out_params->mcp_resp = mb_params.mcp_resp;
2577 p_out_params->mcp_param = mb_params.mcp_param;
2578 p_out_params->resc_num = mfw_resc_info.size;
2579 p_out_params->resc_start = mfw_resc_info.offset;
2580 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
2581 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
2582 p_out_params->flags = mfw_resc_info.flags;
2583
2584 DP_VERBOSE(p_hwfn,
2585 QED_MSG_SP,
2586 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
2587 QED_MFW_GET_FIELD(p_out_params->mcp_param,
2588 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2589 QED_MFW_GET_FIELD(p_out_params->mcp_param,
2590 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2591 p_out_params->resc_num,
2592 p_out_params->resc_start,
2593 p_out_params->vf_resc_num,
2594 p_out_params->vf_resc_start, p_out_params->flags);
2595
2596 return 0;
2597 }
2598
2599 int
2600 qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
2601 struct qed_ptt *p_ptt,
2602 enum qed_resources res_id,
2603 u32 resc_max_val, u32 *p_mcp_resp)
2604 {
2605 struct qed_resc_alloc_out_params out_params;
2606 struct qed_resc_alloc_in_params in_params;
2607 int rc;
2608
2609 memset(&in_params, 0, sizeof(in_params));
2610 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
2611 in_params.res_id = res_id;
2612 in_params.resc_max_val = resc_max_val;
2613 memset(&out_params, 0, sizeof(out_params));
2614 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2615 &out_params);
2616 if (rc)
2617 return rc;
2618
2619 *p_mcp_resp = out_params.mcp_resp;
2620
2621 return 0;
2622 }
2623
2624 int
2625 qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
2626 struct qed_ptt *p_ptt,
2627 enum qed_resources res_id,
2628 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
2629 {
2630 struct qed_resc_alloc_out_params out_params;
2631 struct qed_resc_alloc_in_params in_params;
2632 int rc;
2633
2634 memset(&in_params, 0, sizeof(in_params));
2635 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2636 in_params.res_id = res_id;
2637 memset(&out_params, 0, sizeof(out_params));
2638 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2639 &out_params);
2640 if (rc)
2641 return rc;
2642
2643 *p_mcp_resp = out_params.mcp_resp;
2644
2645 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2646 *p_resc_num = out_params.resc_num;
2647 *p_resc_start = out_params.resc_start;
2648 }
2649
2650 return 0;
2651 }
2652
2653 int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2654 {
2655 u32 mcp_resp, mcp_param;
2656
2657 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2658 &mcp_resp, &mcp_param);
2659 }
2660
2661 static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
2662 struct qed_ptt *p_ptt,
2663 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
2664 {
2665 int rc;
2666
2667 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
2668 p_mcp_resp, p_mcp_param);
2669 if (rc)
2670 return rc;
2671
2672 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
2673 DP_INFO(p_hwfn,
2674 "The resource command is unsupported by the MFW\n");
2675 return -EINVAL;
2676 }
2677
2678 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
2679 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
2680
2681 DP_NOTICE(p_hwfn,
2682 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
2683 param, opcode);
2684 return -EINVAL;
2685 }
2686
2687 return rc;
2688 }
2689
2690 int
2691 __qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2692 struct qed_ptt *p_ptt,
2693 struct qed_resc_lock_params *p_params)
2694 {
2695 u32 param = 0, mcp_resp, mcp_param;
2696 u8 opcode;
2697 int rc;
2698
2699 switch (p_params->timeout) {
2700 case QED_MCP_RESC_LOCK_TO_DEFAULT:
2701 opcode = RESOURCE_OPCODE_REQ;
2702 p_params->timeout = 0;
2703 break;
2704 case QED_MCP_RESC_LOCK_TO_NONE:
2705 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
2706 p_params->timeout = 0;
2707 break;
2708 default:
2709 opcode = RESOURCE_OPCODE_REQ_W_AGING;
2710 break;
2711 }
2712
2713 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2714 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2715 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
2716
2717 DP_VERBOSE(p_hwfn,
2718 QED_MSG_SP,
2719 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
2720 param, p_params->timeout, opcode, p_params->resource);
2721
2722 /* Attempt to acquire the resource */
2723 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2724 if (rc)
2725 return rc;
2726
2727 /* Analyze the response */
2728 p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
2729 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2730
2731 DP_VERBOSE(p_hwfn,
2732 QED_MSG_SP,
2733 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
2734 mcp_param, opcode, p_params->owner);
2735
2736 switch (opcode) {
2737 case RESOURCE_OPCODE_GNT:
2738 p_params->b_granted = true;
2739 break;
2740 case RESOURCE_OPCODE_BUSY:
2741 p_params->b_granted = false;
2742 break;
2743 default:
2744 DP_NOTICE(p_hwfn,
2745 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
2746 mcp_param, opcode);
2747 return -EINVAL;
2748 }
2749
2750 return 0;
2751 }
2752
2753 int
2754 qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2755 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
2756 {
2757 u32 retry_cnt = 0;
2758 int rc;
2759
2760 do {
2761 /* No need for an interval before the first iteration */
2762 if (retry_cnt) {
2763 if (p_params->sleep_b4_retry) {
2764 u16 retry_interval_in_ms =
2765 DIV_ROUND_UP(p_params->retry_interval,
2766 1000);
2767
2768 msleep(retry_interval_in_ms);
2769 } else {
2770 udelay(p_params->retry_interval);
2771 }
2772 }
2773
2774 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
2775 if (rc)
2776 return rc;
2777
2778 if (p_params->b_granted)
2779 break;
2780 } while (retry_cnt++ < p_params->retry_num);
2781
2782 return 0;
2783 }
2784
2785 int
2786 qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
2787 struct qed_ptt *p_ptt,
2788 struct qed_resc_unlock_params *p_params)
2789 {
2790 u32 param = 0, mcp_resp, mcp_param;
2791 u8 opcode;
2792 int rc;
2793
2794 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
2795 : RESOURCE_OPCODE_RELEASE;
2796 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2797 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2798
2799 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2800 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
2801 param, opcode, p_params->resource);
2802
2803 /* Attempt to release the resource */
2804 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2805 if (rc)
2806 return rc;
2807
2808 /* Analyze the response */
2809 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2810
2811 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2812 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
2813 mcp_param, opcode);
2814
2815 switch (opcode) {
2816 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
2817 DP_INFO(p_hwfn,
2818 "Resource unlock request for an already released resource [%d]\n",
2819 p_params->resource);
2820 /* Fallthrough */
2821 case RESOURCE_OPCODE_RELEASED:
2822 p_params->b_released = true;
2823 break;
2824 case RESOURCE_OPCODE_WRONG_OWNER:
2825 p_params->b_released = false;
2826 break;
2827 default:
2828 DP_NOTICE(p_hwfn,
2829 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
2830 mcp_param, opcode);
2831 return -EINVAL;
2832 }
2833
2834 return 0;
2835 }
2836
2837 void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
2838 struct qed_resc_unlock_params *p_unlock,
2839 enum qed_resc_lock
2840 resource, bool b_is_permanent)
2841 {
2842 if (p_lock) {
2843 memset(p_lock, 0, sizeof(*p_lock));
2844
2845 /* Permanent resources don't require aging, and there's no
2846 * point in trying to acquire them more than once since it's
2847 * unexpected another entity would release them.
2848 */
2849 if (b_is_permanent) {
2850 p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
2851 } else {
2852 p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
2853 p_lock->retry_interval =
2854 QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
2855 p_lock->sleep_b4_retry = true;
2856 }
2857
2858 p_lock->resource = resource;
2859 }
2860
2861 if (p_unlock) {
2862 memset(p_unlock, 0, sizeof(*p_unlock));
2863 p_unlock->resource = resource;
2864 }
2865 }
2866
2867 int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2868 {
2869 u32 mcp_resp;
2870 int rc;
2871
2872 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
2873 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
2874 if (!rc)
2875 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
2876 "MFW supported features: %08x\n",
2877 p_hwfn->mcp_info->capabilities);
2878
2879 return rc;
2880 }
2881
2882 int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2883 {
2884 u32 mcp_resp, mcp_param, features;
2885
2886 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
2887
2888 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
2889 features, &mcp_resp, &mcp_param);
2890 }
Linux with added FPC-III support