2 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 * Purpose: Implement functions to access baseband
24 * BBuGetFrameTime - Calculate data frame transmitting time
25 * BBvCaculateParameter - Caculate PhyLength, PhyService and Phy Signal
26 * parameter for baseband Tx
27 * BBbReadEmbedded - Embedded read baseband register via MAC
28 * BBbWriteEmbedded - Embedded write baseband register via MAC
29 * BBbVT3253Init - VIA VT3253 baseband chip init code
32 * 06-10-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
33 * 08-07-2003 Bryan YC Fan: Add MAXIM2827/2825 and RFMD2959 support.
34 * 08-26-2003 Kyle Hsu : Modify BBuGetFrameTime() and
35 * BBvCalculateParameter().
36 * cancel the setting of MAC_REG_SOFTPWRCTL on
39 * 09-01-2003 Bryan YC Fan: RF & BB tables updated.
40 * Modified BBvLoopbackOn & BBvLoopbackOff().
51 /*--------------------- Static Classes ----------------------------*/
53 /*--------------------- Static Variables --------------------------*/
55 /*--------------------- Static Functions --------------------------*/
57 /*--------------------- Export Variables --------------------------*/
59 /*--------------------- Static Definitions -------------------------*/
61 /*--------------------- Static Classes ----------------------------*/
63 /*--------------------- Static Variables --------------------------*/
65 #define CB_VT3253_INIT_FOR_RFMD 446
66 static const unsigned char byVT3253InitTab_RFMD
[CB_VT3253_INIT_FOR_RFMD
][2] = {
515 #define CB_VT3253B0_INIT_FOR_RFMD 256
516 static const unsigned char byVT3253B0_RFMD
[CB_VT3253B0_INIT_FOR_RFMD
][2] = {
775 #define CB_VT3253B0_AGC_FOR_RFMD2959 195
778 unsigned char byVT3253B0_AGC4_RFMD2959
[CB_VT3253B0_AGC_FOR_RFMD2959
][2] = {
976 #define CB_VT3253B0_INIT_FOR_AIROHA2230 256
979 unsigned char byVT3253B0_AIROHA2230
[CB_VT3253B0_INIT_FOR_AIROHA2230
][2] = {
1088 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1238 #define CB_VT3253B0_INIT_FOR_UW2451 256
1240 static unsigned char byVT3253B0_UW2451
[CB_VT3253B0_INIT_FOR_UW2451
][2] = {
1349 {0x6c, 0x00}, /* RobertYu:20050125, request by JJSue */
1499 #define CB_VT3253B0_AGC 193
1501 static unsigned char byVT3253B0_AGC
[CB_VT3253B0_AGC
][2] = {
1697 static const unsigned short awcFrameTime
[MAX_RATE
] = {
1698 10, 20, 55, 110, 24, 36, 48, 72, 96, 144, 192, 216
1701 /*--------------------- Export Variables --------------------------*/
1703 * Description: Calculate data frame transmitting time
1707 * byPreambleType - Preamble Type
1708 * byPktType - PK_TYPE_11A, PK_TYPE_11B, PK_TYPE_11GB, PK_TYPE_11GA
1709 * cbFrameLength - Baseband Type
1713 * Return Value: FrameTime
1718 unsigned char byPreambleType
,
1719 unsigned char byPktType
,
1720 unsigned int cbFrameLength
,
1721 unsigned short wRate
1724 unsigned int uFrameTime
;
1725 unsigned int uPreamble
;
1727 unsigned int uRateIdx
= (unsigned int)wRate
;
1728 unsigned int uRate
= 0;
1730 if (uRateIdx
> RATE_54M
)
1733 uRate
= (unsigned int)awcFrameTime
[uRateIdx
];
1735 if (uRateIdx
<= 3) { /* CCK mode */
1736 if (byPreambleType
== 1) /* Short */
1741 uFrameTime
= (cbFrameLength
* 80) / uRate
; /* ????? */
1742 uTmp
= (uFrameTime
* uRate
) / 80;
1743 if (cbFrameLength
!= uTmp
)
1746 return uPreamble
+ uFrameTime
;
1748 uFrameTime
= (cbFrameLength
* 8 + 22) / uRate
; /* ???????? */
1749 uTmp
= ((uFrameTime
* uRate
) - 22) / 8;
1750 if (cbFrameLength
!= uTmp
)
1753 uFrameTime
= uFrameTime
* 4; /* ??????? */
1754 if (byPktType
!= PK_TYPE_11A
)
1755 uFrameTime
+= 6; /* ?????? */
1757 return 20 + uFrameTime
; /* ?????? */
1761 * Description: Calculate Length, Service, and Signal fields of Phy for Tx
1765 * priv - Device Structure
1766 * frame_length - Tx Frame Length
1769 * struct vnt_phy_field *phy
1770 * - pointer to Phy Length field
1771 * - pointer to Phy Service field
1772 * - pointer to Phy Signal field
1774 * Return Value: none
1777 void vnt_get_phy_field(struct vnt_private
*priv
, u32 frame_length
,
1778 u16 tx_rate
, u8 pkt_type
, struct vnt_phy_field
*phy
)
1784 u8 preamble_type
= priv
->byPreambleType
;
1786 bit_count
= frame_length
* 8;
1797 count
= bit_count
/ 2;
1799 if (preamble_type
== 1)
1806 count
= (bit_count
* 10) / 55;
1807 tmp
= (count
* 55) / 10;
1809 if (tmp
!= bit_count
)
1812 if (preamble_type
== 1)
1819 count
= bit_count
/ 11;
1822 if (tmp
!= bit_count
) {
1825 if ((bit_count
- tmp
) <= 3)
1829 if (preamble_type
== 1)
1836 if (pkt_type
== PK_TYPE_11A
)
1843 if (pkt_type
== PK_TYPE_11A
)
1850 if (pkt_type
== PK_TYPE_11A
)
1857 if (pkt_type
== PK_TYPE_11A
)
1864 if (pkt_type
== PK_TYPE_11A
)
1871 if (pkt_type
== PK_TYPE_11A
)
1878 if (pkt_type
== PK_TYPE_11A
)
1885 if (pkt_type
== PK_TYPE_11A
)
1891 if (pkt_type
== PK_TYPE_11A
)
1898 if (pkt_type
== PK_TYPE_11B
) {
1899 phy
->service
= 0x00;
1901 phy
->service
|= 0x80;
1902 phy
->len
= cpu_to_le16((u16
)count
);
1904 phy
->service
= 0x00;
1905 phy
->len
= cpu_to_le16((u16
)frame_length
);
1910 * Description: Read a byte from BASEBAND, by embedded programming
1914 * iobase - I/O base address
1915 * byBBAddr - address of register in Baseband
1917 * pbyData - data read
1919 * Return Value: true if succeeded; false if failed.
1922 bool BBbReadEmbedded(struct vnt_private
*priv
,
1923 unsigned char byBBAddr
, unsigned char *pbyData
)
1925 void __iomem
*iobase
= priv
->PortOffset
;
1927 unsigned char byValue
;
1930 VNSvOutPortB(iobase
+ MAC_REG_BBREGADR
, byBBAddr
);
1933 MACvRegBitsOn(iobase
, MAC_REG_BBREGCTL
, BBREGCTL_REGR
);
1934 /* W_MAX_TIMEOUT is the timeout period */
1935 for (ww
= 0; ww
< W_MAX_TIMEOUT
; ww
++) {
1936 VNSvInPortB(iobase
+ MAC_REG_BBREGCTL
, &byValue
);
1937 if (byValue
& BBREGCTL_DONE
)
1942 VNSvInPortB(iobase
+ MAC_REG_BBREGDATA
, pbyData
);
1944 if (ww
== W_MAX_TIMEOUT
) {
1945 pr_debug(" DBG_PORT80(0x30)\n");
1952 * Description: Write a Byte to BASEBAND, by embedded programming
1956 * iobase - I/O base address
1957 * byBBAddr - address of register in Baseband
1958 * byData - data to write
1962 * Return Value: true if succeeded; false if failed.
1965 bool BBbWriteEmbedded(struct vnt_private
*priv
,
1966 unsigned char byBBAddr
, unsigned char byData
)
1968 void __iomem
*iobase
= priv
->PortOffset
;
1970 unsigned char byValue
;
1973 VNSvOutPortB(iobase
+ MAC_REG_BBREGADR
, byBBAddr
);
1975 VNSvOutPortB(iobase
+ MAC_REG_BBREGDATA
, byData
);
1977 /* turn on BBREGCTL_REGW */
1978 MACvRegBitsOn(iobase
, MAC_REG_BBREGCTL
, BBREGCTL_REGW
);
1979 /* W_MAX_TIMEOUT is the timeout period */
1980 for (ww
= 0; ww
< W_MAX_TIMEOUT
; ww
++) {
1981 VNSvInPortB(iobase
+ MAC_REG_BBREGCTL
, &byValue
);
1982 if (byValue
& BBREGCTL_DONE
)
1986 if (ww
== W_MAX_TIMEOUT
) {
1987 pr_debug(" DBG_PORT80(0x31)\n");
1994 * Description: VIA VT3253 Baseband chip init function
1998 * iobase - I/O base address
1999 * byRevId - Revision ID
2000 * byRFType - RF type
2004 * Return Value: true if succeeded; false if failed.
2008 bool BBbVT3253Init(struct vnt_private
*priv
)
2010 bool bResult
= true;
2012 void __iomem
*iobase
= priv
->PortOffset
;
2013 unsigned char byRFType
= priv
->byRFType
;
2014 unsigned char byLocalID
= priv
->byLocalID
;
2016 if (byRFType
== RF_RFMD2959
) {
2017 if (byLocalID
<= REV_ID_VT3253_A1
) {
2018 for (ii
= 0; ii
< CB_VT3253_INIT_FOR_RFMD
; ii
++)
2019 bResult
&= BBbWriteEmbedded(priv
,
2020 byVT3253InitTab_RFMD
[ii
][0],
2021 byVT3253InitTab_RFMD
[ii
][1]);
2024 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_RFMD
; ii
++)
2025 bResult
&= BBbWriteEmbedded(priv
,
2026 byVT3253B0_RFMD
[ii
][0],
2027 byVT3253B0_RFMD
[ii
][1]);
2029 for (ii
= 0; ii
< CB_VT3253B0_AGC_FOR_RFMD2959
; ii
++)
2030 bResult
&= BBbWriteEmbedded(priv
,
2031 byVT3253B0_AGC4_RFMD2959
[ii
][0],
2032 byVT3253B0_AGC4_RFMD2959
[ii
][1]);
2034 VNSvOutPortD(iobase
+ MAC_REG_ITRTMSET
, 0x23);
2035 MACvRegBitsOn(iobase
, MAC_REG_PAPEDELAY
, BIT(0));
2037 priv
->abyBBVGA
[0] = 0x18;
2038 priv
->abyBBVGA
[1] = 0x0A;
2039 priv
->abyBBVGA
[2] = 0x0;
2040 priv
->abyBBVGA
[3] = 0x0;
2041 priv
->ldBmThreshold
[0] = -70;
2042 priv
->ldBmThreshold
[1] = -50;
2043 priv
->ldBmThreshold
[2] = 0;
2044 priv
->ldBmThreshold
[3] = 0;
2045 } else if ((byRFType
== RF_AIROHA
) || (byRFType
== RF_AL2230S
)) {
2046 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_AIROHA2230
; ii
++)
2047 bResult
&= BBbWriteEmbedded(priv
,
2048 byVT3253B0_AIROHA2230
[ii
][0],
2049 byVT3253B0_AIROHA2230
[ii
][1]);
2051 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++)
2052 bResult
&= BBbWriteEmbedded(priv
,
2053 byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2055 priv
->abyBBVGA
[0] = 0x1C;
2056 priv
->abyBBVGA
[1] = 0x10;
2057 priv
->abyBBVGA
[2] = 0x0;
2058 priv
->abyBBVGA
[3] = 0x0;
2059 priv
->ldBmThreshold
[0] = -70;
2060 priv
->ldBmThreshold
[1] = -48;
2061 priv
->ldBmThreshold
[2] = 0;
2062 priv
->ldBmThreshold
[3] = 0;
2063 } else if (byRFType
== RF_UW2451
) {
2064 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_UW2451
; ii
++)
2065 bResult
&= BBbWriteEmbedded(priv
,
2066 byVT3253B0_UW2451
[ii
][0],
2067 byVT3253B0_UW2451
[ii
][1]);
2069 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++)
2070 bResult
&= BBbWriteEmbedded(priv
,
2071 byVT3253B0_AGC
[ii
][0],
2072 byVT3253B0_AGC
[ii
][1]);
2074 VNSvOutPortB(iobase
+ MAC_REG_ITRTMSET
, 0x23);
2075 MACvRegBitsOn(iobase
, MAC_REG_PAPEDELAY
, BIT(0));
2077 priv
->abyBBVGA
[0] = 0x14;
2078 priv
->abyBBVGA
[1] = 0x0A;
2079 priv
->abyBBVGA
[2] = 0x0;
2080 priv
->abyBBVGA
[3] = 0x0;
2081 priv
->ldBmThreshold
[0] = -60;
2082 priv
->ldBmThreshold
[1] = -50;
2083 priv
->ldBmThreshold
[2] = 0;
2084 priv
->ldBmThreshold
[3] = 0;
2085 } else if (byRFType
== RF_UW2452
) {
2086 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_UW2451
; ii
++)
2087 bResult
&= BBbWriteEmbedded(priv
,
2088 byVT3253B0_UW2451
[ii
][0],
2089 byVT3253B0_UW2451
[ii
][1]);
2091 /* Init ANT B select,
2092 * TX Config CR09 = 0x61->0x45,
2093 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2096 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2098 /* Init ANT B select,
2099 * RX Config CR10 = 0x28->0x2A,
2100 * 0x2A->0x28(VC1/VC2 define,
2101 * make the ANT_A, ANT_B inverted)
2104 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2105 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2106 bResult
&= BBbWriteEmbedded(priv
, 0xd7, 0x06);
2108 /* {{RobertYu:20050125, request by Jack */
2109 bResult
&= BBbWriteEmbedded(priv
, 0x90, 0x20);
2110 bResult
&= BBbWriteEmbedded(priv
, 0x97, 0xeb);
2113 /* {{RobertYu:20050221, request by Jack */
2114 bResult
&= BBbWriteEmbedded(priv
, 0xa6, 0x00);
2115 bResult
&= BBbWriteEmbedded(priv
, 0xa8, 0x30);
2117 bResult
&= BBbWriteEmbedded(priv
, 0xb0, 0x58);
2119 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++)
2120 bResult
&= BBbWriteEmbedded(priv
,
2121 byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2123 priv
->abyBBVGA
[0] = 0x14;
2124 priv
->abyBBVGA
[1] = 0x0A;
2125 priv
->abyBBVGA
[2] = 0x0;
2126 priv
->abyBBVGA
[3] = 0x0;
2127 priv
->ldBmThreshold
[0] = -60;
2128 priv
->ldBmThreshold
[1] = -50;
2129 priv
->ldBmThreshold
[2] = 0;
2130 priv
->ldBmThreshold
[3] = 0;
2133 } else if (byRFType
== RF_VT3226
) {
2134 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_AIROHA2230
; ii
++)
2135 bResult
&= BBbWriteEmbedded(priv
,
2136 byVT3253B0_AIROHA2230
[ii
][0],
2137 byVT3253B0_AIROHA2230
[ii
][1]);
2139 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++)
2140 bResult
&= BBbWriteEmbedded(priv
,
2141 byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2143 priv
->abyBBVGA
[0] = 0x1C;
2144 priv
->abyBBVGA
[1] = 0x10;
2145 priv
->abyBBVGA
[2] = 0x0;
2146 priv
->abyBBVGA
[3] = 0x0;
2147 priv
->ldBmThreshold
[0] = -70;
2148 priv
->ldBmThreshold
[1] = -48;
2149 priv
->ldBmThreshold
[2] = 0;
2150 priv
->ldBmThreshold
[3] = 0;
2151 /* Fix VT3226 DFC system timing issue */
2152 MACvSetRFLE_LatchBase(iobase
);
2153 /* {{ RobertYu: 20050104 */
2154 } else if (byRFType
== RF_AIROHA7230
) {
2155 for (ii
= 0; ii
< CB_VT3253B0_INIT_FOR_AIROHA2230
; ii
++)
2156 bResult
&= BBbWriteEmbedded(priv
,
2157 byVT3253B0_AIROHA2230
[ii
][0],
2158 byVT3253B0_AIROHA2230
[ii
][1]);
2160 /* {{ RobertYu:20050223, request by JerryChung */
2161 /* Init ANT B select,TX Config CR09 = 0x61->0x45,
2162 * 0x45->0x41(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2164 /*bResult &= BBbWriteEmbedded(iobase,0x09,0x41);*/
2165 /* Init ANT B select,RX Config CR10 = 0x28->0x2A,
2166 * 0x2A->0x28(VC1/VC2 define, make the ANT_A, ANT_B inverted)
2168 /*bResult &= BBbWriteEmbedded(iobase,0x0a,0x28);*/
2169 /* Select VC1/VC2, CR215 = 0x02->0x06 */
2170 bResult
&= BBbWriteEmbedded(priv
, 0xd7, 0x06);
2173 for (ii
= 0; ii
< CB_VT3253B0_AGC
; ii
++)
2174 bResult
&= BBbWriteEmbedded(priv
,
2175 byVT3253B0_AGC
[ii
][0], byVT3253B0_AGC
[ii
][1]);
2177 priv
->abyBBVGA
[0] = 0x1C;
2178 priv
->abyBBVGA
[1] = 0x10;
2179 priv
->abyBBVGA
[2] = 0x0;
2180 priv
->abyBBVGA
[3] = 0x0;
2181 priv
->ldBmThreshold
[0] = -70;
2182 priv
->ldBmThreshold
[1] = -48;
2183 priv
->ldBmThreshold
[2] = 0;
2184 priv
->ldBmThreshold
[3] = 0;
2187 /* No VGA Table now */
2188 priv
->bUpdateBBVGA
= false;
2189 priv
->abyBBVGA
[0] = 0x1C;
2192 if (byLocalID
> REV_ID_VT3253_A1
) {
2193 BBbWriteEmbedded(priv
, 0x04, 0x7F);
2194 BBbWriteEmbedded(priv
, 0x0D, 0x01);
2201 * Description: Set ShortSlotTime mode
2205 * priv - Device Structure
2209 * Return Value: none
2213 BBvSetShortSlotTime(struct vnt_private
*priv
)
2215 unsigned char byBBRxConf
= 0;
2216 unsigned char byBBVGA
= 0;
2218 BBbReadEmbedded(priv
, 0x0A, &byBBRxConf
); /* CR10 */
2220 if (priv
->bShortSlotTime
)
2221 byBBRxConf
&= 0xDF; /* 1101 1111 */
2223 byBBRxConf
|= 0x20; /* 0010 0000 */
2225 /* patch for 3253B0 Baseband with Cardbus module */
2226 BBbReadEmbedded(priv
, 0xE7, &byBBVGA
);
2227 if (byBBVGA
== priv
->abyBBVGA
[0])
2228 byBBRxConf
|= 0x20; /* 0010 0000 */
2230 BBbWriteEmbedded(priv
, 0x0A, byBBRxConf
); /* CR10 */
2233 void BBvSetVGAGainOffset(struct vnt_private
*priv
, unsigned char byData
)
2235 unsigned char byBBRxConf
= 0;
2237 BBbWriteEmbedded(priv
, 0xE7, byData
);
2239 BBbReadEmbedded(priv
, 0x0A, &byBBRxConf
); /* CR10 */
2240 /* patch for 3253B0 Baseband with Cardbus module */
2241 if (byData
== priv
->abyBBVGA
[0])
2242 byBBRxConf
|= 0x20; /* 0010 0000 */
2243 else if (priv
->bShortSlotTime
)
2244 byBBRxConf
&= 0xDF; /* 1101 1111 */
2246 byBBRxConf
|= 0x20; /* 0010 0000 */
2247 priv
->byBBVGACurrent
= byData
;
2248 BBbWriteEmbedded(priv
, 0x0A, byBBRxConf
); /* CR10 */
2252 * Description: Baseband SoftwareReset
2256 * iobase - I/O base address
2260 * Return Value: none
2264 BBvSoftwareReset(struct vnt_private
*priv
)
2266 BBbWriteEmbedded(priv
, 0x50, 0x40);
2267 BBbWriteEmbedded(priv
, 0x50, 0);
2268 BBbWriteEmbedded(priv
, 0x9C, 0x01);
2269 BBbWriteEmbedded(priv
, 0x9C, 0);
2273 * Description: Baseband Power Save Mode ON
2277 * iobase - I/O base address
2281 * Return Value: none
2285 BBvPowerSaveModeON(struct vnt_private
*priv
)
2287 unsigned char byOrgData
;
2289 BBbReadEmbedded(priv
, 0x0D, &byOrgData
);
2290 byOrgData
|= BIT(0);
2291 BBbWriteEmbedded(priv
, 0x0D, byOrgData
);
2295 * Description: Baseband Power Save Mode OFF
2299 * iobase - I/O base address
2303 * Return Value: none
2307 BBvPowerSaveModeOFF(struct vnt_private
*priv
)
2309 unsigned char byOrgData
;
2311 BBbReadEmbedded(priv
, 0x0D, &byOrgData
);
2312 byOrgData
&= ~(BIT(0));
2313 BBbWriteEmbedded(priv
, 0x0D, byOrgData
);
2317 * Description: Set Tx Antenna mode
2321 * priv - Device Structure
2322 * byAntennaMode - Antenna Mode
2326 * Return Value: none
2331 BBvSetTxAntennaMode(struct vnt_private
*priv
, unsigned char byAntennaMode
)
2333 unsigned char byBBTxConf
;
2335 BBbReadEmbedded(priv
, 0x09, &byBBTxConf
); /* CR09 */
2336 if (byAntennaMode
== ANT_DIVERSITY
) {
2337 /* bit 1 is diversity */
2339 } else if (byAntennaMode
== ANT_A
) {
2340 /* bit 2 is ANTSEL */
2341 byBBTxConf
&= 0xF9; /* 1111 1001 */
2342 } else if (byAntennaMode
== ANT_B
) {
2343 byBBTxConf
&= 0xFD; /* 1111 1101 */
2346 BBbWriteEmbedded(priv
, 0x09, byBBTxConf
); /* CR09 */
2350 * Description: Set Rx Antenna mode
2354 * priv - Device Structure
2355 * byAntennaMode - Antenna Mode
2359 * Return Value: none
2364 BBvSetRxAntennaMode(struct vnt_private
*priv
, unsigned char byAntennaMode
)
2366 unsigned char byBBRxConf
;
2368 BBbReadEmbedded(priv
, 0x0A, &byBBRxConf
); /* CR10 */
2369 if (byAntennaMode
== ANT_DIVERSITY
) {
2372 } else if (byAntennaMode
== ANT_A
) {
2373 byBBRxConf
&= 0xFC; /* 1111 1100 */
2374 } else if (byAntennaMode
== ANT_B
) {
2375 byBBRxConf
&= 0xFE; /* 1111 1110 */
2378 BBbWriteEmbedded(priv
, 0x0A, byBBRxConf
); /* CR10 */
2382 * Description: BBvSetDeepSleep
2386 * priv - Device Structure
2390 * Return Value: none
2394 BBvSetDeepSleep(struct vnt_private
*priv
, unsigned char byLocalID
)
2396 BBbWriteEmbedded(priv
, 0x0C, 0x17); /* CR12 */
2397 BBbWriteEmbedded(priv
, 0x0D, 0xB9); /* CR13 */
2401 BBvExitDeepSleep(struct vnt_private
*priv
, unsigned char byLocalID
)
2403 BBbWriteEmbedded(priv
, 0x0C, 0x00); /* CR12 */
2404 BBbWriteEmbedded(priv
, 0x0D, 0x01); /* CR13 */