drivers/video/sis/sis.h

   1 /*
   2  * SiS 300/540/630[S]/730[S],
   3  * SiS 315[E|PRO]/550/[M]65x/[M]661[F|M]X/740/[M]741[GX]/330/[M]76x[GX],
   4  * XGI V3XT/V5/V8, Z7
   5  * frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
   6  *
   7  * Copyright (C) 2001-2005 Thomas Winischhofer, Vienna, Austria.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the named License,
  12  * or any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
  22  */
  23
  24 #ifndef _SIS_H_
  25 #define _SIS_H_
  26
  27 #include <linux/config.h>
  28 #include <linux/version.h>
  29
  30 #include "osdef.h"
  31 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
  32 #include <video/sisfb.h>
  33 #else
  34 #include <linux/sisfb.h>
  35 #endif
  36
  37 #include "vgatypes.h"
  38 #include "vstruct.h"
  39
  40 #define VER_MAJOR               1
  41 #define VER_MINOR               8
  42 #define VER_LEVEL               9
  43
  44 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
  45 #include <linux/spinlock.h>
  46 #define SIS_PCI_GET_CLASS(a, b) pci_get_class(a, b)
  47 #define SIS_PCI_GET_DEVICE(a,b,c) pci_get_device(a,b,c)
  48 #define SIS_PCI_GET_SLOT(a,b) pci_get_slot(a,b)
  49 #define SIS_PCI_PUT_DEVICE(a) pci_dev_put(a)
  50 #ifdef CONFIG_COMPAT
  51 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,10)
  52 #include <linux/ioctl32.h>
  53 #define SIS_OLD_CONFIG_COMPAT
  54 #else
  55 #include <linux/smp_lock.h>
  56 #define SIS_NEW_CONFIG_COMPAT
  57 #endif
  58 #endif  /* CONFIG_COMPAT */
  59 #else  /* 2.4 */
  60 #define SIS_PCI_GET_CLASS(a, b) pci_find_class(a, b)
  61 #define SIS_PCI_GET_DEVICE(a,b,c) pci_find_device(a,b,c)
  62 #define SIS_PCI_GET_SLOT(a,b) pci_find_slot(a,b)
  63 #define SIS_PCI_PUT_DEVICE(a)
  64 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,19)
  65 #ifdef __x86_64__       /* Shouldn't we check for CONFIG_IA32_EMULATION here? */
  66 #include <asm/ioctl32.h>
  67 #define SIS_OLD_CONFIG_COMPAT
  68 #endif
  69 #endif
  70 #endif /* 2.4 */
  71 #if LINUX_VERSION_CODE > KERNEL_VERSION(2,6,8)
  72 #define SIS_IOTYPE1 void __iomem
  73 #define SIS_IOTYPE2 __iomem
  74 #define SISINITSTATIC static
  75 #else
  76 #define SIS_IOTYPE1 unsigned char
  77 #define SIS_IOTYPE2
  78 #define SISINITSTATIC
  79 #endif
  80
  81 #undef SISFBDEBUG
  82
  83 #ifdef SISFBDEBUG
  84 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  85 #define TWDEBUG(x) printk(KERN_INFO x "\n");
  86 #else
  87 #define DPRINTK(fmt, args...)
  88 #define TWDEBUG(x)
  89 #endif
  90
  91 #define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
  92
  93 /* To be included in pci_ids.h */
  94 #ifndef PCI_DEVICE_ID_SI_650_VGA
  95 #define PCI_DEVICE_ID_SI_650_VGA        0x6325
  96 #endif
  97 #ifndef PCI_DEVICE_ID_SI_650
  98 #define PCI_DEVICE_ID_SI_650            0x0650
  99 #endif
 100 #ifndef PCI_DEVICE_ID_SI_651
 101 #define PCI_DEVICE_ID_SI_651            0x0651
 102 #endif
 103 #ifndef PCI_DEVICE_ID_SI_740
 104 #define PCI_DEVICE_ID_SI_740            0x0740
 105 #endif
 106 #ifndef PCI_DEVICE_ID_SI_330
 107 #define PCI_DEVICE_ID_SI_330            0x0330
 108 #endif
 109 #ifndef PCI_DEVICE_ID_SI_660_VGA
 110 #define PCI_DEVICE_ID_SI_660_VGA        0x6330
 111 #endif
 112 #ifndef PCI_DEVICE_ID_SI_661
 113 #define PCI_DEVICE_ID_SI_661            0x0661
 114 #endif
 115 #ifndef PCI_DEVICE_ID_SI_741
 116 #define PCI_DEVICE_ID_SI_741            0x0741
 117 #endif
 118 #ifndef PCI_DEVICE_ID_SI_660
 119 #define PCI_DEVICE_ID_SI_660            0x0660
 120 #endif
 121 #ifndef PCI_DEVICE_ID_SI_760
 122 #define PCI_DEVICE_ID_SI_760            0x0760
 123 #endif
 124 #ifndef PCI_DEVICE_ID_SI_761
 125 #define PCI_DEVICE_ID_SI_761            0x0761
 126 #endif
 127
 128 #ifndef PCI_VENDOR_ID_XGI
 129 #define PCI_VENDOR_ID_XGI               0x18ca
 130 #endif
 131
 132 #ifndef PCI_DEVICE_ID_XGI_20
 133 #define PCI_DEVICE_ID_XGI_20            0x0020
 134 #endif
 135
 136 #ifndef PCI_DEVICE_ID_XGI_40
 137 #define PCI_DEVICE_ID_XGI_40            0x0040
 138 #endif
 139
 140 /* To be included in fb.h */
 141 #ifndef FB_ACCEL_SIS_GLAMOUR_2
 142 #define FB_ACCEL_SIS_GLAMOUR_2  40      /* SiS 315, 65x, 740, 661, 741  */
 143 #endif
 144 #ifndef FB_ACCEL_SIS_XABRE
 145 #define FB_ACCEL_SIS_XABRE      41      /* SiS 330 ("Xabre"), 76x       */
 146 #endif
 147 #ifndef FB_ACCEL_XGI_VOLARI_V
 148 #define FB_ACCEL_XGI_VOLARI_V   47      /* XGI Volari Vx (V3XT, V5, V8) */
 149 #endif
 150 #ifndef FB_ACCEL_XGI_VOLARI_Z
 151 #define FB_ACCEL_XGI_VOLARI_Z   48      /* XGI Volari Z7                */
 152 #endif
 153
 154 /* ivideo->caps */
 155 #define HW_CURSOR_CAP           0x80
 156 #define TURBO_QUEUE_CAP         0x40
 157 #define AGP_CMD_QUEUE_CAP       0x20
 158 #define VM_CMD_QUEUE_CAP        0x10
 159 #define MMIO_CMD_QUEUE_CAP      0x08
 160
 161 /* For 300 series */
 162 #define TURBO_QUEUE_AREA_SIZE   (512 * 1024)    /* 512K */
 163 #define HW_CURSOR_AREA_SIZE_300 4096            /* 4K */
 164
 165 /* For 315/Xabre series */
 166 #define COMMAND_QUEUE_AREA_SIZE (512 * 1024)    /* 512K */
 167 #define COMMAND_QUEUE_AREA_SIZE_Z7 (128 * 1024) /* 128k for XGI Z7 */
 168 #define HW_CURSOR_AREA_SIZE_315 16384           /* 16K */
 169 #define COMMAND_QUEUE_THRESHOLD 0x1F
 170
 171 #define SIS_OH_ALLOC_SIZE       4000
 172 #define SENTINEL                0x7fffffff
 173
 174 #define SEQ_ADR                 0x14
 175 #define SEQ_DATA                0x15
 176 #define DAC_ADR                 0x18
 177 #define DAC_DATA                0x19
 178 #define CRTC_ADR                0x24
 179 #define CRTC_DATA               0x25
 180 #define DAC2_ADR                (0x16-0x30)
 181 #define DAC2_DATA               (0x17-0x30)
 182 #define VB_PART1_ADR            (0x04-0x30)
 183 #define VB_PART1_DATA           (0x05-0x30)
 184 #define VB_PART2_ADR            (0x10-0x30)
 185 #define VB_PART2_DATA           (0x11-0x30)
 186 #define VB_PART3_ADR            (0x12-0x30)
 187 #define VB_PART3_DATA           (0x13-0x30)
 188 #define VB_PART4_ADR            (0x14-0x30)
 189 #define VB_PART4_DATA           (0x15-0x30)
 190
 191 #define SISSR                   ivideo->SiS_Pr.SiS_P3c4
 192 #define SISCR                   ivideo->SiS_Pr.SiS_P3d4
 193 #define SISDACA                 ivideo->SiS_Pr.SiS_P3c8
 194 #define SISDACD                 ivideo->SiS_Pr.SiS_P3c9
 195 #define SISPART1                ivideo->SiS_Pr.SiS_Part1Port
 196 #define SISPART2                ivideo->SiS_Pr.SiS_Part2Port
 197 #define SISPART3                ivideo->SiS_Pr.SiS_Part3Port
 198 #define SISPART4                ivideo->SiS_Pr.SiS_Part4Port
 199 #define SISPART5                ivideo->SiS_Pr.SiS_Part5Port
 200 #define SISDAC2A                SISPART5
 201 #define SISDAC2D                (SISPART5 + 1)
 202 #define SISMISCR                (ivideo->SiS_Pr.RelIO + 0x1c)
 203 #define SISMISCW                ivideo->SiS_Pr.SiS_P3c2
 204 #define SISINPSTAT              (ivideo->SiS_Pr.RelIO + 0x2a)
 205 #define SISPEL                  ivideo->SiS_Pr.SiS_P3c6
 206 #define SISVGAENABLE            (ivideo->SiS_Pr.RelIO + 0x13)
 207 #define SISVID                  (ivideo->SiS_Pr.RelIO + 0x02 - 0x30)
 208 #define SISCAP                  (ivideo->SiS_Pr.RelIO + 0x00 - 0x30)
 209
 210 #define IND_SIS_PASSWORD                0x05  /* SRs */
 211 #define IND_SIS_COLOR_MODE              0x06
 212 #define IND_SIS_RAMDAC_CONTROL          0x07
 213 #define IND_SIS_DRAM_SIZE               0x14
 214 #define IND_SIS_MODULE_ENABLE           0x1E
 215 #define IND_SIS_PCI_ADDRESS_SET         0x20
 216 #define IND_SIS_TURBOQUEUE_ADR          0x26
 217 #define IND_SIS_TURBOQUEUE_SET          0x27
 218 #define IND_SIS_POWER_ON_TRAP           0x38
 219 #define IND_SIS_POWER_ON_TRAP2          0x39
 220 #define IND_SIS_CMDQUEUE_SET            0x26
 221 #define IND_SIS_CMDQUEUE_THRESHOLD      0x27
 222
 223 #define IND_SIS_AGP_IO_PAD      0x48
 224
 225 #define SIS_CRT2_WENABLE_300    0x24  /* Part1 */
 226 #define SIS_CRT2_WENABLE_315    0x2F
 227
 228 #define SIS_PASSWORD            0x86  /* SR05 */
 229
 230 #define SIS_INTERLACED_MODE     0x20  /* SR06 */
 231 #define SIS_8BPP_COLOR_MODE     0x0
 232 #define SIS_15BPP_COLOR_MODE    0x1
 233 #define SIS_16BPP_COLOR_MODE    0x2
 234 #define SIS_32BPP_COLOR_MODE    0x4
 235
 236 #define SIS_ENABLE_2D           0x40  /* SR1E */
 237
 238 #define SIS_MEM_MAP_IO_ENABLE   0x01  /* SR20 */
 239 #define SIS_PCI_ADDR_ENABLE     0x80
 240
 241 #define SIS_AGP_CMDQUEUE_ENABLE         0x80  /* 315/330/340 series SR26 */
 242 #define SIS_VRAM_CMDQUEUE_ENABLE        0x40
 243 #define SIS_MMIO_CMD_ENABLE             0x20
 244 #define SIS_CMD_QUEUE_SIZE_512k         0x00
 245 #define SIS_CMD_QUEUE_SIZE_1M           0x04
 246 #define SIS_CMD_QUEUE_SIZE_2M           0x08
 247 #define SIS_CMD_QUEUE_SIZE_4M           0x0C
 248 #define SIS_CMD_QUEUE_RESET             0x01
 249 #define SIS_CMD_AUTO_CORR               0x02
 250
 251 #define SIS_CMD_QUEUE_SIZE_Z7_64k       0x00 /* XGI Z7 */
 252 #define SIS_CMD_QUEUE_SIZE_Z7_128k      0x04
 253
 254 #define SIS_SIMULTANEOUS_VIEW_ENABLE    0x01  /* CR30 */
 255 #define SIS_MODE_SELECT_CRT2            0x02
 256 #define SIS_VB_OUTPUT_COMPOSITE         0x04
 257 #define SIS_VB_OUTPUT_SVIDEO            0x08
 258 #define SIS_VB_OUTPUT_SCART             0x10
 259 #define SIS_VB_OUTPUT_LCD               0x20
 260 #define SIS_VB_OUTPUT_CRT2              0x40
 261 #define SIS_VB_OUTPUT_HIVISION          0x80
 262
 263 #define SIS_VB_OUTPUT_DISABLE   0x20  /* CR31 */
 264 #define SIS_DRIVER_MODE         0x40
 265
 266 #define SIS_VB_COMPOSITE        0x01  /* CR32 */
 267 #define SIS_VB_SVIDEO           0x02
 268 #define SIS_VB_SCART            0x04
 269 #define SIS_VB_LCD              0x08
 270 #define SIS_VB_CRT2             0x10
 271 #define SIS_CRT1                0x20
 272 #define SIS_VB_HIVISION         0x40
 273 #define SIS_VB_YPBPR            0x80
 274 #define SIS_VB_TV               (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
 275                                 SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR)
 276
 277 #define SIS_EXTERNAL_CHIP_MASK                  0x0E  /* CR37 (< SiS 660) */
 278 #define SIS_EXTERNAL_CHIP_SIS301                0x01  /* in CR37 << 1 ! */
 279 #define SIS_EXTERNAL_CHIP_LVDS                  0x02
 280 #define SIS_EXTERNAL_CHIP_TRUMPION              0x03
 281 #define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL         0x04
 282 #define SIS_EXTERNAL_CHIP_CHRONTEL              0x05
 283 #define SIS310_EXTERNAL_CHIP_LVDS               0x02
 284 #define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL      0x03
 285
 286 #define SIS_AGP_2X              0x20  /* CR48 */
 287
 288 /* vbflags, private entries (others in sisfb.h) */
 289 #define VB_CONEXANT             0x00000800      /* 661 series only */
 290 #define VB_TRUMPION             VB_CONEXANT     /* 300 series only */
 291 #define VB_302ELV               0x00004000
 292 #define VB_301                  0x00100000      /* Video bridge type */
 293 #define VB_301B                 0x00200000
 294 #define VB_302B                 0x00400000
 295 #define VB_30xBDH               0x00800000      /* 30xB DH version (w/o LCD support) */
 296 #define VB_LVDS                 0x01000000
 297 #define VB_CHRONTEL             0x02000000
 298 #define VB_301LV                0x04000000
 299 #define VB_302LV                0x08000000
 300 #define VB_301C                 0x10000000
 301
 302 #define VB_SISBRIDGE            (VB_301|VB_301B|VB_301C|VB_302B|VB_301LV|VB_302LV|VB_302ELV)
 303 #define VB_VIDEOBRIDGE          (VB_SISBRIDGE | VB_LVDS | VB_CHRONTEL | VB_CONEXANT)
 304
 305 /* vbflags2 (static stuff only!) */
 306 #define VB2_SISUMC              0x00000001
 307 #define VB2_301                 0x00000002      /* Video bridge type */
 308 #define VB2_301B                0x00000004
 309 #define VB2_301C                0x00000008
 310 #define VB2_307T                0x00000010
 311 #define VB2_302B                0x00000800
 312 #define VB2_301LV               0x00001000
 313 #define VB2_302LV               0x00002000
 314 #define VB2_302ELV              0x00004000
 315 #define VB2_307LV               0x00008000
 316 #define VB2_30xBDH              0x08000000      /* 30xB DH version (w/o LCD support) */
 317 #define VB2_CONEXANT            0x10000000
 318 #define VB2_TRUMPION            0x20000000
 319 #define VB2_LVDS                0x40000000
 320 #define VB2_CHRONTEL            0x80000000
 321
 322 #define VB2_SISLVDSBRIDGE       (VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
 323 #define VB2_SISTMDSBRIDGE       (VB2_301   | VB2_301B  | VB2_301C   | VB2_302B | VB2_307T)
 324 #define VB2_SISBRIDGE           (VB2_SISLVDSBRIDGE | VB2_SISTMDSBRIDGE)
 325
 326 #define VB2_SISTMDSLCDABRIDGE   (VB2_301C | VB2_307T)
 327 #define VB2_SISLCDABRIDGE       (VB2_SISTMDSLCDABRIDGE | VB2_301LV | VB2_302LV | VB2_302ELV | VB2_307LV)
 328
 329 #define VB2_SISHIVISIONBRIDGE   (VB2_301  | VB2_301B | VB2_302B)
 330 #define VB2_SISYPBPRBRIDGE      (VB2_301C | VB2_307T | VB2_SISLVDSBRIDGE)
 331 #define VB2_SISYPBPRARBRIDGE    (VB2_301C | VB2_307T | VB2_307LV)
 332 #define VB2_SISTAP4SCALER       (VB2_301C | VB2_307T | VB2_302ELV | VB2_307LV)
 333 #define VB2_SISTVBRIDGE         (VB2_SISHIVISIONBRIDGE | VB2_SISYPBPRBRIDGE)
 334
 335 #define VB2_SISVGA2BRIDGE       (VB2_301 | VB2_301B | VB2_301C | VB2_302B | VB2_307T)
 336
 337 #define VB2_VIDEOBRIDGE         (VB2_SISBRIDGE | VB2_LVDS | VB2_CHRONTEL | VB2_CONEXANT)
 338
 339 #define VB2_30xB                (VB2_301B  | VB2_301C   | VB2_302B  | VB2_307T)
 340 #define VB2_30xBLV              (VB2_30xB  | VB2_SISLVDSBRIDGE)
 341 #define VB2_30xC                (VB2_301C  | VB2_307T)
 342 #define VB2_30xCLV              (VB2_301C  | VB2_307T   | VB2_302ELV| VB2_307LV)
 343 #define VB2_SISEMIBRIDGE        (VB2_302LV | VB2_302ELV | VB2_307LV)
 344 #define VB2_LCD162MHZBRIDGE     (VB2_301C  | VB2_307T)
 345 #define VB2_LCDOVER1280BRIDGE   (VB2_301C  | VB2_307T   | VB2_302LV | VB2_302ELV | VB2_307LV)
 346 #define VB2_LCDOVER1600BRIDGE   (VB2_307T  | VB2_307LV)
 347 #define VB2_RAMDAC202MHZBRIDGE  (VB2_301C  | VB2_307T)
 348
 349 /* I/O port access macros */
 350 #define inSISREG(base)          inb(base)
 351
 352 #define outSISREG(base,val)     outb(val,base)
 353
 354 #define orSISREG(base,val)                              \
 355                 do {                                    \
 356                         u8 __Temp = inSISREG(base);     \
 357                         outSISREG(base, __Temp | (val));\
 358                 } while (0)
 359
 360 #define andSISREG(base,val)                             \
 361                 do {                                    \
 362                         u8 __Temp = inSISREG(base);     \
 363                         outSISREG(base, __Temp & (val));\
 364                 } while (0)
 365
 366 #define inSISIDXREG(base,idx,var)                       \
 367                 do {                                    \
 368                         outSISREG(base, idx);           \
 369                         var = inSISREG((base)+1);       \
 370                 } while (0)
 371
 372 #define outSISIDXREG(base,idx,val)                      \
 373                 do {                                    \
 374                         outSISREG(base, idx);           \
 375                         outSISREG((base)+1, val);       \
 376                 } while (0)
 377
 378 #define orSISIDXREG(base,idx,val)                               \
 379                 do {                                            \
 380                         u8 __Temp;                              \
 381                         outSISREG(base, idx);                   \
 382                         __Temp = inSISREG((base)+1) | (val);    \
 383                         outSISREG((base)+1, __Temp);            \
 384                 } while (0)
 385
 386 #define andSISIDXREG(base,idx,and)                              \
 387                 do {                                            \
 388                         u8 __Temp;                              \
 389                         outSISREG(base, idx);                   \
 390                         __Temp = inSISREG((base)+1) & (and);    \
 391                         outSISREG((base)+1, __Temp);            \
 392                 } while (0)
 393
 394 #define setSISIDXREG(base,idx,and,or)                                   \
 395                 do {                                                    \
 396                         u8 __Temp;                                      \
 397                         outSISREG(base, idx);                           \
 398                         __Temp = (inSISREG((base)+1) & (and)) | (or);   \
 399                         outSISREG((base)+1, __Temp);                    \
 400                 } while (0)
 401
 402 /* MMIO access macros */
 403 #define MMIO_IN8(base, offset)  readb((base+offset))
 404 #define MMIO_IN16(base, offset) readw((base+offset))
 405 #define MMIO_IN32(base, offset) readl((base+offset))
 406
 407 #define MMIO_OUT8(base, offset, val)  writeb(((u8)(val)), (base+offset))
 408 #define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
 409 #define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
 410
 411 /* Queue control MMIO registers */
 412 #define Q_BASE_ADDR             0x85C0  /* Base address of software queue */
 413 #define Q_WRITE_PTR             0x85C4  /* Current write pointer */
 414 #define Q_READ_PTR              0x85C8  /* Current read pointer */
 415 #define Q_STATUS                0x85CC  /* queue status */
 416
 417 #define MMIO_QUEUE_PHYBASE      Q_BASE_ADDR
 418 #define MMIO_QUEUE_WRITEPORT    Q_WRITE_PTR
 419 #define MMIO_QUEUE_READPORT     Q_READ_PTR
 420
 421 #ifndef FB_BLANK_UNBLANK
 422 #define FB_BLANK_UNBLANK        0
 423 #endif
 424 #ifndef FB_BLANK_NORMAL
 425 #define FB_BLANK_NORMAL         1
 426 #endif
 427 #ifndef FB_BLANK_VSYNC_SUSPEND
 428 #define FB_BLANK_VSYNC_SUSPEND  2
 429 #endif
 430 #ifndef FB_BLANK_HSYNC_SUSPEND
 431 #define FB_BLANK_HSYNC_SUSPEND  3
 432 #endif
 433 #ifndef FB_BLANK_POWERDOWN
 434 #define FB_BLANK_POWERDOWN      4
 435 #endif
 436
 437 enum _SIS_LCD_TYPE {
 438     LCD_INVALID = 0,
 439     LCD_800x600,
 440     LCD_1024x768,
 441     LCD_1280x1024,
 442     LCD_1280x960,
 443     LCD_640x480,
 444     LCD_1600x1200,
 445     LCD_1920x1440,
 446     LCD_2048x1536,
 447     LCD_320x240,        /* FSTN */
 448     LCD_1400x1050,
 449     LCD_1152x864,
 450     LCD_1152x768,
 451     LCD_1280x768,
 452     LCD_1024x600,
 453     LCD_320x240_2,      /* DSTN */
 454     LCD_320x240_3,      /* DSTN */
 455     LCD_848x480,
 456     LCD_1280x800,
 457     LCD_1680x1050,
 458     LCD_1280x720,
 459     LCD_1280x854,
 460     LCD_CUSTOM,
 461     LCD_UNKNOWN
 462 };
 463
 464 enum _SIS_CMDTYPE {
 465     MMIO_CMD = 0,
 466     AGP_CMD_QUEUE,
 467     VM_CMD_QUEUE,
 468 };
 469
 470 struct SIS_OH {
 471         struct SIS_OH *poh_next;
 472         struct SIS_OH *poh_prev;
 473         u32            offset;
 474         u32            size;
 475 };
 476
 477 struct SIS_OHALLOC {
 478         struct SIS_OHALLOC *poha_next;
 479         struct SIS_OH aoh[1];
 480 };
 481
 482 struct SIS_HEAP {
 483         struct SIS_OH   oh_free;
 484         struct SIS_OH   oh_used;
 485         struct SIS_OH   *poh_freelist;
 486         struct SIS_OHALLOC *poha_chain;
 487         u32             max_freesize;
 488         struct sis_video_info *vinfo;
 489 };
 490
 491 /* Our "par" */
 492 struct sis_video_info {
 493         int             cardnumber;
 494         struct fb_info  *memyselfandi;
 495
 496         struct SiS_Private SiS_Pr;
 497
 498         struct sisfb_info sisfbinfo;    /* For ioctl SISFB_GET_INFO */
 499
 500         struct fb_var_screeninfo default_var;
 501
 502 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
 503         struct fb_fix_screeninfo sisfb_fix;
 504         u32             pseudo_palette[17];
 505 #endif
 506
 507 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 508         struct display           sis_disp;
 509         struct display_switch    sisfb_sw;
 510         struct {
 511                 u16 red, green, blue, pad;
 512         }               sis_palette[256];
 513         union {
 514 #ifdef FBCON_HAS_CFB16
 515                 u16 cfb16[16];
 516 #endif
 517 #ifdef FBCON_HAS_CFB32
 518                 u32 cfb32[16];
 519 #endif
 520         }               sis_fbcon_cmap;
 521 #endif
 522
 523         struct sisfb_monitor {
 524                 u16 hmin;
 525                 u16 hmax;
 526                 u16 vmin;
 527                 u16 vmax;
 528                 u32 dclockmax;
 529                 u8  feature;
 530                 BOOLEAN datavalid;
 531         }               sisfb_thismonitor;
 532
 533         unsigned short  chip_id;        /* PCI ID of chip */
 534         unsigned short  chip_vendor;    /* PCI ID of vendor */
 535         char            myid[40];
 536
 537         struct pci_dev  *nbridge;
 538         struct pci_dev  *lpcdev;
 539
 540         int             mni;    /* Mode number index */
 541
 542 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 543         int             currcon;
 544 #endif
 545
 546         unsigned long   video_size;
 547         unsigned long   video_base;
 548         unsigned long   mmio_size;
 549         unsigned long   mmio_base;
 550         unsigned long   vga_base;
 551
 552         unsigned long   video_offset;
 553
 554         unsigned long   UMAsize, LFBsize;
 555
 556         SIS_IOTYPE1     *video_vbase;
 557         SIS_IOTYPE1     *mmio_vbase;
 558
 559         unsigned char   *bios_abase;
 560
 561         int             mtrr;
 562
 563         u32             sisfb_mem;
 564
 565         u32             sisfb_parm_mem;
 566         int             sisfb_accel;
 567         int             sisfb_ypan;
 568         int             sisfb_max;
 569         int             sisfb_userom;
 570         int             sisfb_useoem;
 571         int             sisfb_mode_idx;
 572         int             sisfb_parm_rate;
 573         int             sisfb_crt1off;
 574         int             sisfb_forcecrt1;
 575         int             sisfb_crt2type;
 576         int             sisfb_crt2flags;
 577         int             sisfb_dstn;
 578         int             sisfb_fstn;
 579         int             sisfb_tvplug;
 580         int             sisfb_tvstd;
 581         int             sisfb_nocrt2rate;
 582 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 583         int             sisfb_inverse;
 584 #endif
 585
 586         u32             heapstart;              /* offset  */
 587         SIS_IOTYPE1     *sisfb_heap_start;      /* address */
 588         SIS_IOTYPE1     *sisfb_heap_end;        /* address */
 589         u32             sisfb_heap_size;
 590         int             havenoheap;
 591
 592         struct SIS_HEAP sisfb_heap;             /* This card's vram heap */
 593
 594         int             video_bpp;
 595         int             video_cmap_len;
 596         int             video_width;
 597         int             video_height;
 598         unsigned int    refresh_rate;
 599
 600         unsigned int    chip;
 601         u8              revision_id;
 602         int             sisvga_enabled;         /* PCI device was enabled */
 603
 604         int             video_linelength;       /* real pitch */
 605         int             scrnpitchCRT1;          /* pitch regarding interlace */
 606
 607         u16             DstColor;               /* For 2d acceleration */
 608         u32             SiS310_AccelDepth;
 609         u32             CommandReg;
 610         int             cmdqueuelength;         /* Current (for accel) */
 611         u32             cmdQueueSize;           /* Total size in KB */
 612
 613         spinlock_t      lockaccel;              /* Do not use outside of kernel! */
 614
 615         unsigned int    pcibus;
 616         unsigned int    pcislot;
 617         unsigned int    pcifunc;
 618
 619         int             accel;
 620         int             engineok;
 621
 622         u16             subsysvendor;
 623         u16             subsysdevice;
 624
 625         u32             vbflags;                /* Replacing deprecated stuff from above */
 626         u32             currentvbflags;
 627         u32             vbflags2;
 628
 629         int             lcdxres, lcdyres;
 630         int             lcddefmodeidx, tvdefmodeidx, defmodeidx;
 631         u32             CRT2LCDType;            /* defined in "SIS_LCD_TYPE" */
 632         u32             curFSTN, curDSTN;
 633
 634         int             current_bpp;
 635         int             current_width;
 636         int             current_height;
 637         int             current_htotal;
 638         int             current_vtotal;
 639         int             current_linelength;
 640         __u32           current_pixclock;
 641         int             current_refresh_rate;
 642
 643         unsigned int    current_base;
 644
 645         u8              mode_no;
 646         u8              rate_idx;
 647         int             modechanged;
 648         unsigned char   modeprechange;
 649
 650 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
 651         u8              sisfb_lastrates[128];
 652 #endif
 653
 654         int             newrom;
 655         int             haveXGIROM;
 656         int             registered;
 657         int             warncount;
 658 #ifdef SIS_OLD_CONFIG_COMPAT
 659         int             ioctl32registered;
 660 #endif
 661
 662         int             sisvga_engine;
 663         int             hwcursor_size;
 664         int             CRT2_write_enable;
 665         u8              caps;
 666
 667         u8              detectedpdc;
 668         u8              detectedpdca;
 669         u8              detectedlcda;
 670
 671         SIS_IOTYPE1     *hwcursor_vbase;
 672
 673         int             chronteltype;
 674         int             tvxpos, tvypos;
 675         u8              p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
 676         int             tvx, tvy;
 677
 678         u8              sisfblocked;
 679
 680         struct sisfb_info sisfb_infoblock;
 681
 682         struct sisfb_cmd sisfb_command;
 683
 684         u32             sisfb_id;
 685
 686         u8              sisfb_can_post;
 687         u8              sisfb_card_posted;
 688         u8              sisfb_was_boot_device;
 689
 690         struct sis_video_info *next;
 691 };
 692
 693 #endif