drivers/clk/qcom/gdsc.c

   1 /*
   2  * Copyright (c) 2015, 2017-2018, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/delay.h>
  16 #include <linux/err.h>
  17 #include <linux/jiffies.h>
  18 #include <linux/kernel.h>
  19 #include <linux/ktime.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset-controller.h>
  23 #include <linux/slab.h>
  24 #include "gdsc.h"
  25
  26 #define PWR_ON_MASK             BIT(31)
  27 #define EN_REST_WAIT_MASK       GENMASK_ULL(23, 20)
  28 #define EN_FEW_WAIT_MASK        GENMASK_ULL(19, 16)
  29 #define CLK_DIS_WAIT_MASK       GENMASK_ULL(15, 12)
  30 #define SW_OVERRIDE_MASK        BIT(2)
  31 #define HW_CONTROL_MASK         BIT(1)
  32 #define SW_COLLAPSE_MASK        BIT(0)
  33 #define GMEM_CLAMP_IO_MASK      BIT(0)
  34 #define GMEM_RESET_MASK         BIT(4)
  35
  36 /* CFG_GDSCR */
  37 #define GDSC_POWER_UP_COMPLETE          BIT(16)
  38 #define GDSC_POWER_DOWN_COMPLETE        BIT(15)
  39 #define CFG_GDSCR_OFFSET                0x4
  40
  41 /* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
  42 #define EN_REST_WAIT_VAL        (0x2 << 20)
  43 #define EN_FEW_WAIT_VAL         (0x8 << 16)
  44 #define CLK_DIS_WAIT_VAL        (0x2 << 12)
  45
  46 #define RETAIN_MEM              BIT(14)
  47 #define RETAIN_PERIPH           BIT(13)
  48
  49 #define TIMEOUT_US              500
  50
  51 #define domain_to_gdsc(domain) container_of(domain, struct gdsc, pd)
  52
  53 enum gdsc_status {
  54         GDSC_OFF,
  55         GDSC_ON
  56 };
  57
  58 /* Returns 1 if GDSC status is status, 0 if not, and < 0 on error */
  59 static int gdsc_check_status(struct gdsc *sc, enum gdsc_status status)
  60 {
  61         unsigned int reg;
  62         u32 val;
  63         int ret;
  64
  65         if (sc->flags & POLL_CFG_GDSCR)
  66                 reg = sc->gdscr + CFG_GDSCR_OFFSET;
  67         else if (sc->gds_hw_ctrl)
  68                 reg = sc->gds_hw_ctrl;
  69         else
  70                 reg = sc->gdscr;
  71
  72         ret = regmap_read(sc->regmap, reg, &val);
  73         if (ret)
  74                 return ret;
  75
  76         if (sc->flags & POLL_CFG_GDSCR) {
  77                 switch (status) {
  78                 case GDSC_ON:
  79                         return !!(val & GDSC_POWER_UP_COMPLETE);
  80                 case GDSC_OFF:
  81                         return !!(val & GDSC_POWER_DOWN_COMPLETE);
  82                 }
  83         }
  84
  85         switch (status) {
  86         case GDSC_ON:
  87                 return !!(val & PWR_ON_MASK);
  88         case GDSC_OFF:
  89                 return !(val & PWR_ON_MASK);
  90         }
  91
  92         return -EINVAL;
  93 }
  94
  95 static int gdsc_hwctrl(struct gdsc *sc, bool en)
  96 {
  97         u32 val = en ? HW_CONTROL_MASK : 0;
  98
  99         return regmap_update_bits(sc->regmap, sc->gdscr, HW_CONTROL_MASK, val);
 100 }
 101
 102 static int gdsc_poll_status(struct gdsc *sc, enum gdsc_status status)
 103 {
 104         ktime_t start;
 105
 106         start = ktime_get();
 107         do {
 108                 if (gdsc_check_status(sc, status))
 109                         return 0;
 110         } while (ktime_us_delta(ktime_get(), start) < TIMEOUT_US);
 111
 112         if (gdsc_check_status(sc, status))
 113                 return 0;
 114
 115         return -ETIMEDOUT;
 116 }
 117
 118 static int gdsc_toggle_logic(struct gdsc *sc, enum gdsc_status status)
 119 {
 120         int ret;
 121         u32 val = (status == GDSC_ON) ? 0 : SW_COLLAPSE_MASK;
 122
 123         ret = regmap_update_bits(sc->regmap, sc->gdscr, SW_COLLAPSE_MASK, val);
 124         if (ret)
 125                 return ret;
 126
 127         /* If disabling votable gdscs, don't poll on status */
 128         if ((sc->flags & VOTABLE) && status == GDSC_OFF) {
 129                 /*
 130                  * Add a short delay here to ensure that an enable
 131                  * right after it was disabled does not put it in an
 132                  * unknown state
 133                  */
 134                 udelay(TIMEOUT_US);
 135                 return 0;
 136         }
 137
 138         if (sc->gds_hw_ctrl) {
 139                 /*
 140                  * The gds hw controller asserts/de-asserts the status bit soon
 141                  * after it receives a power on/off request from a master.
 142                  * The controller then takes around 8 xo cycles to start its
 143                  * internal state machine and update the status bit. During
 144                  * this time, the status bit does not reflect the true status
 145                  * of the core.
 146                  * Add a delay of 1 us between writing to the SW_COLLAPSE bit
 147                  * and polling the status bit.
 148                  */
 149                 udelay(1);
 150         }
 151
 152         return gdsc_poll_status(sc, status);
 153 }
 154
 155 static inline int gdsc_deassert_reset(struct gdsc *sc)
 156 {
 157         int i;
 158
 159         for (i = 0; i < sc->reset_count; i++)
 160                 sc->rcdev->ops->deassert(sc->rcdev, sc->resets[i]);
 161         return 0;
 162 }
 163
 164 static inline int gdsc_assert_reset(struct gdsc *sc)
 165 {
 166         int i;
 167
 168         for (i = 0; i < sc->reset_count; i++)
 169                 sc->rcdev->ops->assert(sc->rcdev, sc->resets[i]);
 170         return 0;
 171 }
 172
 173 static inline void gdsc_force_mem_on(struct gdsc *sc)
 174 {
 175         int i;
 176         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 177
 178         for (i = 0; i < sc->cxc_count; i++)
 179                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, mask);
 180 }
 181
 182 static inline void gdsc_clear_mem_on(struct gdsc *sc)
 183 {
 184         int i;
 185         u32 mask = RETAIN_MEM | RETAIN_PERIPH;
 186
 187         for (i = 0; i < sc->cxc_count; i++)
 188                 regmap_update_bits(sc->regmap, sc->cxcs[i], mask, 0);
 189 }
 190
 191 static inline void gdsc_deassert_clamp_io(struct gdsc *sc)
 192 {
 193         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 194                            GMEM_CLAMP_IO_MASK, 0);
 195 }
 196
 197 static inline void gdsc_assert_clamp_io(struct gdsc *sc)
 198 {
 199         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 200                            GMEM_CLAMP_IO_MASK, 1);
 201 }
 202
 203 static inline void gdsc_assert_reset_aon(struct gdsc *sc)
 204 {
 205         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 206                            GMEM_RESET_MASK, 1);
 207         udelay(1);
 208         regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
 209                            GMEM_RESET_MASK, 0);
 210 }
 211 static int gdsc_enable(struct generic_pm_domain *domain)
 212 {
 213         struct gdsc *sc = domain_to_gdsc(domain);
 214         int ret;
 215
 216         if (sc->pwrsts == PWRSTS_ON)
 217                 return gdsc_deassert_reset(sc);
 218
 219         if (sc->flags & SW_RESET) {
 220                 gdsc_assert_reset(sc);
 221                 udelay(1);
 222                 gdsc_deassert_reset(sc);
 223         }
 224
 225         if (sc->flags & CLAMP_IO) {
 226                 if (sc->flags & AON_RESET)
 227                         gdsc_assert_reset_aon(sc);
 228                 gdsc_deassert_clamp_io(sc);
 229         }
 230
 231         ret = gdsc_toggle_logic(sc, GDSC_ON);
 232         if (ret)
 233                 return ret;
 234
 235         if (sc->pwrsts & PWRSTS_OFF)
 236                 gdsc_force_mem_on(sc);
 237
 238         /*
 239          * If clocks to this power domain were already on, they will take an
 240          * additional 4 clock cycles to re-enable after the power domain is
 241          * enabled. Delay to account for this. A delay is also needed to ensure
 242          * clocks are not enabled within 400ns of enabling power to the
 243          * memories.
 244          */
 245         udelay(1);
 246
 247         /* Turn on HW trigger mode if supported */
 248         if (sc->flags & HW_CTRL) {
 249                 ret = gdsc_hwctrl(sc, true);
 250                 if (ret)
 251                         return ret;
 252                 /*
 253                  * Wait for the GDSC to go through a power down and
 254                  * up cycle.  In case a firmware ends up polling status
 255                  * bits for the gdsc, it might read an 'on' status before
 256                  * the GDSC can finish the power cycle.
 257                  * We wait 1us before returning to ensure the firmware
 258                  * can't immediately poll the status bits.
 259                  */
 260                 udelay(1);
 261         }
 262
 263         return 0;
 264 }
 265
 266 static int gdsc_disable(struct generic_pm_domain *domain)
 267 {
 268         struct gdsc *sc = domain_to_gdsc(domain);
 269         int ret;
 270
 271         if (sc->pwrsts == PWRSTS_ON)
 272                 return gdsc_assert_reset(sc);
 273
 274         /* Turn off HW trigger mode if supported */
 275         if (sc->flags & HW_CTRL) {
 276                 ret = gdsc_hwctrl(sc, false);
 277                 if (ret < 0)
 278                         return ret;
 279                 /*
 280                  * Wait for the GDSC to go through a power down and
 281                  * up cycle.  In case we end up polling status
 282                  * bits for the gdsc before the power cycle is completed
 283                  * it might read an 'on' status wrongly.
 284                  */
 285                 udelay(1);
 286
 287                 ret = gdsc_poll_status(sc, GDSC_ON);
 288                 if (ret)
 289                         return ret;
 290         }
 291
 292         if (sc->pwrsts & PWRSTS_OFF)
 293                 gdsc_clear_mem_on(sc);
 294
 295         ret = gdsc_toggle_logic(sc, GDSC_OFF);
 296         if (ret)
 297                 return ret;
 298
 299         if (sc->flags & CLAMP_IO)
 300                 gdsc_assert_clamp_io(sc);
 301
 302         return 0;
 303 }
 304
 305 static int gdsc_init(struct gdsc *sc)
 306 {
 307         u32 mask, val;
 308         int on, ret;
 309
 310         /*
 311          * Disable HW trigger: collapse/restore occur based on registers writes.
 312          * Disable SW override: Use hardware state-machine for sequencing.
 313          * Configure wait time between states.
 314          */
 315         mask = HW_CONTROL_MASK | SW_OVERRIDE_MASK |
 316                EN_REST_WAIT_MASK | EN_FEW_WAIT_MASK | CLK_DIS_WAIT_MASK;
 317         val = EN_REST_WAIT_VAL | EN_FEW_WAIT_VAL | CLK_DIS_WAIT_VAL;
 318         ret = regmap_update_bits(sc->regmap, sc->gdscr, mask, val);
 319         if (ret)
 320                 return ret;
 321
 322         /* Force gdsc ON if only ON state is supported */
 323         if (sc->pwrsts == PWRSTS_ON) {
 324                 ret = gdsc_toggle_logic(sc, GDSC_ON);
 325                 if (ret)
 326                         return ret;
 327         }
 328
 329         on = gdsc_check_status(sc, GDSC_ON);
 330         if (on < 0)
 331                 return on;
 332
 333         /*
 334          * Votable GDSCs can be ON due to Vote from other masters.
 335          * If a Votable GDSC is ON, make sure we have a Vote.
 336          */
 337         if ((sc->flags & VOTABLE) && on)
 338                 gdsc_enable(&sc->pd);
 339
 340         /* If ALWAYS_ON GDSCs are not ON, turn them ON */
 341         if (sc->flags & ALWAYS_ON) {
 342                 if (!on)
 343                         gdsc_enable(&sc->pd);
 344                 on = true;
 345                 sc->pd.flags |= GENPD_FLAG_ALWAYS_ON;
 346         }
 347
 348         if (on || (sc->pwrsts & PWRSTS_RET))
 349                 gdsc_force_mem_on(sc);
 350         else
 351                 gdsc_clear_mem_on(sc);
 352
 353         sc->pd.power_off = gdsc_disable;
 354         sc->pd.power_on = gdsc_enable;
 355         pm_genpd_init(&sc->pd, NULL, !on);
 356
 357         return 0;
 358 }
 359
 360 int gdsc_register(struct gdsc_desc *desc,
 361                   struct reset_controller_dev *rcdev, struct regmap *regmap)
 362 {
 363         int i, ret;
 364         struct genpd_onecell_data *data;
 365         struct device *dev = desc->dev;
 366         struct gdsc **scs = desc->scs;
 367         size_t num = desc->num;
 368
 369         data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 370         if (!data)
 371                 return -ENOMEM;
 372
 373         data->domains = devm_kcalloc(dev, num, sizeof(*data->domains),
 374                                      GFP_KERNEL);
 375         if (!data->domains)
 376                 return -ENOMEM;
 377
 378         data->num_domains = num;
 379         for (i = 0; i < num; i++) {
 380                 if (!scs[i])
 381                         continue;
 382                 scs[i]->regmap = regmap;
 383                 scs[i]->rcdev = rcdev;
 384                 ret = gdsc_init(scs[i]);
 385                 if (ret)
 386                         return ret;
 387                 data->domains[i] = &scs[i]->pd;
 388         }
 389
 390         /* Add subdomains */
 391         for (i = 0; i < num; i++) {
 392                 if (!scs[i])
 393                         continue;
 394                 if (scs[i]->parent)
 395                         pm_genpd_add_subdomain(scs[i]->parent, &scs[i]->pd);
 396         }
 397
 398         return of_genpd_add_provider_onecell(dev->of_node, data);
 399 }
 400
 401 void gdsc_unregister(struct gdsc_desc *desc)
 402 {
 403         int i;
 404         struct device *dev = desc->dev;
 405         struct gdsc **scs = desc->scs;
 406         size_t num = desc->num;
 407
 408         /* Remove subdomains */
 409         for (i = 0; i < num; i++) {
 410                 if (!scs[i])
 411                         continue;
 412                 if (scs[i]->parent)
 413                         pm_genpd_remove_subdomain(scs[i]->parent, &scs[i]->pd);
 414         }
 415         of_genpd_del_provider(dev->of_node);
 416 }