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i2c: aspeed: Fix initial values of master and slave state
[linux/fpc-iii.git] / drivers / mmc / host / jz4740_mmc.c
blob993386c9ea500f2006c73b66c84876084f502c6f
1 /*
2 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
3 * Copyright (C) 2013, Imagination Technologies
4 *
5 * JZ4740 SD/MMC controller driver
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 *
12 * You should have received a copy of the GNU General Public License along
13 * with this program; if not, write to the Free Software Foundation, Inc.,
14 * 675 Mass Ave, Cambridge, MA 02139, USA.
15 *
16 */
17
18 #include <linux/bitops.h>
19 #include <linux/clk.h>
20 #include <linux/delay.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/err.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/module.h>
31 #include <linux/of_device.h>
32 #include <linux/pinctrl/consumer.h>
33 #include <linux/platform_device.h>
34 #include <linux/scatterlist.h>
35
36 #include <asm/cacheflush.h>
37
38 #include <asm/mach-jz4740/dma.h>
39 #include <asm/mach-jz4740/jz4740_mmc.h>
40
41 #define JZ_REG_MMC_STRPCL 0x00
42 #define JZ_REG_MMC_STATUS 0x04
43 #define JZ_REG_MMC_CLKRT 0x08
44 #define JZ_REG_MMC_CMDAT 0x0C
45 #define JZ_REG_MMC_RESTO 0x10
46 #define JZ_REG_MMC_RDTO 0x14
47 #define JZ_REG_MMC_BLKLEN 0x18
48 #define JZ_REG_MMC_NOB 0x1C
49 #define JZ_REG_MMC_SNOB 0x20
50 #define JZ_REG_MMC_IMASK 0x24
51 #define JZ_REG_MMC_IREG 0x28
52 #define JZ_REG_MMC_CMD 0x2C
53 #define JZ_REG_MMC_ARG 0x30
54 #define JZ_REG_MMC_RESP_FIFO 0x34
55 #define JZ_REG_MMC_RXFIFO 0x38
56 #define JZ_REG_MMC_TXFIFO 0x3C
57 #define JZ_REG_MMC_DMAC 0x44
58
59 #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7)
60 #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6)
61 #define JZ_MMC_STRPCL_START_READWAIT BIT(5)
62 #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4)
63 #define JZ_MMC_STRPCL_RESET BIT(3)
64 #define JZ_MMC_STRPCL_START_OP BIT(2)
65 #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0))
66 #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0)
67 #define JZ_MMC_STRPCL_CLOCK_START BIT(1)
68
69
70 #define JZ_MMC_STATUS_IS_RESETTING BIT(15)
71 #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14)
72 #define JZ_MMC_STATUS_PRG_DONE BIT(13)
73 #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12)
74 #define JZ_MMC_STATUS_END_CMD_RES BIT(11)
75 #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10)
76 #define JZ_MMC_STATUS_IS_READWAIT BIT(9)
77 #define JZ_MMC_STATUS_CLK_EN BIT(8)
78 #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7)
79 #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6)
80 #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5)
81 #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4)
82 #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3)
83 #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2)
84 #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1)
85 #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0)
86
87 #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0))
88 #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2))
89
90
91 #define JZ_MMC_CMDAT_IO_ABORT BIT(11)
92 #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10)
93 #define JZ_MMC_CMDAT_DMA_EN BIT(8)
94 #define JZ_MMC_CMDAT_INIT BIT(7)
95 #define JZ_MMC_CMDAT_BUSY BIT(6)
96 #define JZ_MMC_CMDAT_STREAM BIT(5)
97 #define JZ_MMC_CMDAT_WRITE BIT(4)
98 #define JZ_MMC_CMDAT_DATA_EN BIT(3)
99 #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0))
100 #define JZ_MMC_CMDAT_RSP_R1 1
101 #define JZ_MMC_CMDAT_RSP_R2 2
102 #define JZ_MMC_CMDAT_RSP_R3 3
103
104 #define JZ_MMC_IRQ_SDIO BIT(7)
105 #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6)
106 #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5)
107 #define JZ_MMC_IRQ_END_CMD_RES BIT(2)
108 #define JZ_MMC_IRQ_PRG_DONE BIT(1)
109 #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0)
110
111 #define JZ_MMC_DMAC_DMA_SEL BIT(1)
112 #define JZ_MMC_DMAC_DMA_EN BIT(0)
113
114 #define JZ_MMC_CLK_RATE 24000000
115
116 enum jz4740_mmc_version {
117 JZ_MMC_JZ4740,
118 JZ_MMC_JZ4750,
119 JZ_MMC_JZ4780,
120 };
121
122 enum jz4740_mmc_state {
123 JZ4740_MMC_STATE_READ_RESPONSE,
124 JZ4740_MMC_STATE_TRANSFER_DATA,
125 JZ4740_MMC_STATE_SEND_STOP,
126 JZ4740_MMC_STATE_DONE,
127 };
128
129 struct jz4740_mmc_host_next {
130 int sg_len;
131 s32 cookie;
132 };
133
134 struct jz4740_mmc_host {
135 struct mmc_host *mmc;
136 struct platform_device *pdev;
137 struct jz4740_mmc_platform_data *pdata;
138 struct clk *clk;
139
140 enum jz4740_mmc_version version;
141
142 int irq;
143 int card_detect_irq;
144
145 void __iomem *base;
146 struct resource *mem_res;
147 struct mmc_request *req;
148 struct mmc_command *cmd;
149
150 unsigned long waiting;
151
152 uint32_t cmdat;
153
154 uint32_t irq_mask;
155
156 spinlock_t lock;
157
158 struct timer_list timeout_timer;
159 struct sg_mapping_iter miter;
160 enum jz4740_mmc_state state;
161
162 /* DMA support */
163 struct dma_chan *dma_rx;
164 struct dma_chan *dma_tx;
165 struct jz4740_mmc_host_next next_data;
166 bool use_dma;
167 int sg_len;
168
169 /* The DMA trigger level is 8 words, that is to say, the DMA read
170 * trigger is when data words in MSC_RXFIFO is >= 8 and the DMA write
171 * trigger is when data words in MSC_TXFIFO is < 8.
172 */
173 #define JZ4740_MMC_FIFO_HALF_SIZE 8
174 };
175
176 static void jz4740_mmc_write_irq_mask(struct jz4740_mmc_host *host,
177 uint32_t val)
178 {
179 if (host->version >= JZ_MMC_JZ4750)
180 return writel(val, host->base + JZ_REG_MMC_IMASK);
181 else
182 return writew(val, host->base + JZ_REG_MMC_IMASK);
183 }
184
185 static void jz4740_mmc_write_irq_reg(struct jz4740_mmc_host *host,
186 uint32_t val)
187 {
188 if (host->version >= JZ_MMC_JZ4780)
189 return writel(val, host->base + JZ_REG_MMC_IREG);
190 else
191 return writew(val, host->base + JZ_REG_MMC_IREG);
192 }
193
194 static uint32_t jz4740_mmc_read_irq_reg(struct jz4740_mmc_host *host)
195 {
196 if (host->version >= JZ_MMC_JZ4780)
197 return readl(host->base + JZ_REG_MMC_IREG);
198 else
199 return readw(host->base + JZ_REG_MMC_IREG);
200 }
201
202 /*----------------------------------------------------------------------------*/
203 /* DMA infrastructure */
204
205 static void jz4740_mmc_release_dma_channels(struct jz4740_mmc_host *host)
206 {
207 if (!host->use_dma)
208 return;
209
210 dma_release_channel(host->dma_tx);
211 dma_release_channel(host->dma_rx);
212 }
213
214 static int jz4740_mmc_acquire_dma_channels(struct jz4740_mmc_host *host)
215 {
216 host->dma_tx = dma_request_chan(mmc_dev(host->mmc), "tx");
217 if (IS_ERR(host->dma_tx)) {
218 dev_err(mmc_dev(host->mmc), "Failed to get dma_tx channel\n");
219 return PTR_ERR(host->dma_tx);
220 }
221
222 host->dma_rx = dma_request_chan(mmc_dev(host->mmc), "rx");
223 if (IS_ERR(host->dma_rx)) {
224 dev_err(mmc_dev(host->mmc), "Failed to get dma_rx channel\n");
225 dma_release_channel(host->dma_tx);
226 return PTR_ERR(host->dma_rx);
227 }
228
229 /* Initialize DMA pre request cookie */
230 host->next_data.cookie = 1;
231
232 return 0;
233 }
234
235 static inline struct dma_chan *jz4740_mmc_get_dma_chan(struct jz4740_mmc_host *host,
236 struct mmc_data *data)
237 {
238 return (data->flags & MMC_DATA_READ) ? host->dma_rx : host->dma_tx;
239 }
240
241 static void jz4740_mmc_dma_unmap(struct jz4740_mmc_host *host,
242 struct mmc_data *data)
243 {
244 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
245 enum dma_data_direction dir = mmc_get_dma_dir(data);
246
247 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir);
248 }
249
250 /* Prepares DMA data for current/next transfer, returns non-zero on failure */
251 static int jz4740_mmc_prepare_dma_data(struct jz4740_mmc_host *host,
252 struct mmc_data *data,
253 struct jz4740_mmc_host_next *next,
254 struct dma_chan *chan)
255 {
256 struct jz4740_mmc_host_next *next_data = &host->next_data;
257 enum dma_data_direction dir = mmc_get_dma_dir(data);
258 int sg_len;
259
260 if (!next && data->host_cookie &&
261 data->host_cookie != host->next_data.cookie) {
262 dev_warn(mmc_dev(host->mmc),
263 "[%s] invalid cookie: data->host_cookie %d host->next_data.cookie %d\n",
264 __func__,
265 data->host_cookie,
266 host->next_data.cookie);
267 data->host_cookie = 0;
268 }
269
270 /* Check if next job is already prepared */
271 if (next || data->host_cookie != host->next_data.cookie) {
272 sg_len = dma_map_sg(chan->device->dev,
273 data->sg,
274 data->sg_len,
275 dir);
276
277 } else {
278 sg_len = next_data->sg_len;
279 next_data->sg_len = 0;
280 }
281
282 if (sg_len <= 0) {
283 dev_err(mmc_dev(host->mmc),
284 "Failed to map scatterlist for DMA operation\n");
285 return -EINVAL;
286 }
287
288 if (next) {
289 next->sg_len = sg_len;
290 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
291 } else
292 host->sg_len = sg_len;
293
294 return 0;
295 }
296
297 static int jz4740_mmc_start_dma_transfer(struct jz4740_mmc_host *host,
298 struct mmc_data *data)
299 {
300 int ret;
301 struct dma_chan *chan;
302 struct dma_async_tx_descriptor *desc;
303 struct dma_slave_config conf = {
304 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
305 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
306 .src_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
307 .dst_maxburst = JZ4740_MMC_FIFO_HALF_SIZE,
308 };
309
310 if (data->flags & MMC_DATA_WRITE) {
311 conf.direction = DMA_MEM_TO_DEV;
312 conf.dst_addr = host->mem_res->start + JZ_REG_MMC_TXFIFO;
313 conf.slave_id = JZ4740_DMA_TYPE_MMC_TRANSMIT;
314 chan = host->dma_tx;
315 } else {
316 conf.direction = DMA_DEV_TO_MEM;
317 conf.src_addr = host->mem_res->start + JZ_REG_MMC_RXFIFO;
318 conf.slave_id = JZ4740_DMA_TYPE_MMC_RECEIVE;
319 chan = host->dma_rx;
320 }
321
322 ret = jz4740_mmc_prepare_dma_data(host, data, NULL, chan);
323 if (ret)
324 return ret;
325
326 dmaengine_slave_config(chan, &conf);
327 desc = dmaengine_prep_slave_sg(chan,
328 data->sg,
329 host->sg_len,
330 conf.direction,
331 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
332 if (!desc) {
333 dev_err(mmc_dev(host->mmc),
334 "Failed to allocate DMA %s descriptor",
335 conf.direction == DMA_MEM_TO_DEV ? "TX" : "RX");
336 goto dma_unmap;
337 }
338
339 dmaengine_submit(desc);
340 dma_async_issue_pending(chan);
341
342 return 0;
343
344 dma_unmap:
345 jz4740_mmc_dma_unmap(host, data);
346 return -ENOMEM;
347 }
348
349 static void jz4740_mmc_pre_request(struct mmc_host *mmc,
350 struct mmc_request *mrq)
351 {
352 struct jz4740_mmc_host *host = mmc_priv(mmc);
353 struct mmc_data *data = mrq->data;
354 struct jz4740_mmc_host_next *next_data = &host->next_data;
355
356 BUG_ON(data->host_cookie);
357
358 if (host->use_dma) {
359 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
360
361 if (jz4740_mmc_prepare_dma_data(host, data, next_data, chan))
362 data->host_cookie = 0;
363 }
364 }
365
366 static void jz4740_mmc_post_request(struct mmc_host *mmc,
367 struct mmc_request *mrq,
368 int err)
369 {
370 struct jz4740_mmc_host *host = mmc_priv(mmc);
371 struct mmc_data *data = mrq->data;
372
373 if (host->use_dma && data->host_cookie) {
374 jz4740_mmc_dma_unmap(host, data);
375 data->host_cookie = 0;
376 }
377
378 if (err) {
379 struct dma_chan *chan = jz4740_mmc_get_dma_chan(host, data);
380
381 dmaengine_terminate_all(chan);
382 }
383 }
384
385 /*----------------------------------------------------------------------------*/
386
387 static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host,
388 unsigned int irq, bool enabled)
389 {
390 unsigned long flags;
391
392 spin_lock_irqsave(&host->lock, flags);
393 if (enabled)
394 host->irq_mask &= ~irq;
395 else
396 host->irq_mask |= irq;
397
398 jz4740_mmc_write_irq_mask(host, host->irq_mask);
399 spin_unlock_irqrestore(&host->lock, flags);
400 }
401
402 static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host,
403 bool start_transfer)
404 {
405 uint16_t val = JZ_MMC_STRPCL_CLOCK_START;
406
407 if (start_transfer)
408 val |= JZ_MMC_STRPCL_START_OP;
409
410 writew(val, host->base + JZ_REG_MMC_STRPCL);
411 }
412
413 static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host)
414 {
415 uint32_t status;
416 unsigned int timeout = 1000;
417
418 writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL);
419 do {
420 status = readl(host->base + JZ_REG_MMC_STATUS);
421 } while (status & JZ_MMC_STATUS_CLK_EN && --timeout);
422 }
423
424 static void jz4740_mmc_reset(struct jz4740_mmc_host *host)
425 {
426 uint32_t status;
427 unsigned int timeout = 1000;
428
429 writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL);
430 udelay(10);
431 do {
432 status = readl(host->base + JZ_REG_MMC_STATUS);
433 } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout);
434 }
435
436 static void jz4740_mmc_request_done(struct jz4740_mmc_host *host)
437 {
438 struct mmc_request *req;
439
440 req = host->req;
441 host->req = NULL;
442
443 mmc_request_done(host->mmc, req);
444 }
445
446 static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host,
447 unsigned int irq)
448 {
449 unsigned int timeout = 0x800;
450 uint32_t status;
451
452 do {
453 status = jz4740_mmc_read_irq_reg(host);
454 } while (!(status & irq) && --timeout);
455
456 if (timeout == 0) {
457 set_bit(0, &host->waiting);
458 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
459 jz4740_mmc_set_irq_enabled(host, irq, true);
460 return true;
461 }
462
463 return false;
464 }
465
466 static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host,
467 struct mmc_data *data)
468 {
469 int status;
470
471 status = readl(host->base + JZ_REG_MMC_STATUS);
472 if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) {
473 if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) {
474 host->req->cmd->error = -ETIMEDOUT;
475 data->error = -ETIMEDOUT;
476 } else {
477 host->req->cmd->error = -EIO;
478 data->error = -EIO;
479 }
480 } else if (status & JZ_MMC_STATUS_READ_ERROR_MASK) {
481 if (status & (JZ_MMC_STATUS_TIMEOUT_READ)) {
482 host->req->cmd->error = -ETIMEDOUT;
483 data->error = -ETIMEDOUT;
484 } else {
485 host->req->cmd->error = -EIO;
486 data->error = -EIO;
487 }
488 }
489 }
490
491 static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host,
492 struct mmc_data *data)
493 {
494 struct sg_mapping_iter *miter = &host->miter;
495 void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO;
496 uint32_t *buf;
497 bool timeout;
498 size_t i, j;
499
500 while (sg_miter_next(miter)) {
501 buf = miter->addr;
502 i = miter->length / 4;
503 j = i / 8;
504 i = i & 0x7;
505 while (j) {
506 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
507 if (unlikely(timeout))
508 goto poll_timeout;
509
510 writel(buf[0], fifo_addr);
511 writel(buf[1], fifo_addr);
512 writel(buf[2], fifo_addr);
513 writel(buf[3], fifo_addr);
514 writel(buf[4], fifo_addr);
515 writel(buf[5], fifo_addr);
516 writel(buf[6], fifo_addr);
517 writel(buf[7], fifo_addr);
518 buf += 8;
519 --j;
520 }
521 if (unlikely(i)) {
522 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ);
523 if (unlikely(timeout))
524 goto poll_timeout;
525
526 while (i) {
527 writel(*buf, fifo_addr);
528 ++buf;
529 --i;
530 }
531 }
532 data->bytes_xfered += miter->length;
533 }
534 sg_miter_stop(miter);
535
536 return false;
537
538 poll_timeout:
539 miter->consumed = (void *)buf - miter->addr;
540 data->bytes_xfered += miter->consumed;
541 sg_miter_stop(miter);
542
543 return true;
544 }
545
546 static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host,
547 struct mmc_data *data)
548 {
549 struct sg_mapping_iter *miter = &host->miter;
550 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO;
551 uint32_t *buf;
552 uint32_t d;
553 uint32_t status;
554 size_t i, j;
555 unsigned int timeout;
556
557 while (sg_miter_next(miter)) {
558 buf = miter->addr;
559 i = miter->length;
560 j = i / 32;
561 i = i & 0x1f;
562 while (j) {
563 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
564 if (unlikely(timeout))
565 goto poll_timeout;
566
567 buf[0] = readl(fifo_addr);
568 buf[1] = readl(fifo_addr);
569 buf[2] = readl(fifo_addr);
570 buf[3] = readl(fifo_addr);
571 buf[4] = readl(fifo_addr);
572 buf[5] = readl(fifo_addr);
573 buf[6] = readl(fifo_addr);
574 buf[7] = readl(fifo_addr);
575
576 buf += 8;
577 --j;
578 }
579
580 if (unlikely(i)) {
581 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ);
582 if (unlikely(timeout))
583 goto poll_timeout;
584
585 while (i >= 4) {
586 *buf++ = readl(fifo_addr);
587 i -= 4;
588 }
589 if (unlikely(i > 0)) {
590 d = readl(fifo_addr);
591 memcpy(buf, &d, i);
592 }
593 }
594 data->bytes_xfered += miter->length;
595
596 /* This can go away once MIPS implements
597 * flush_kernel_dcache_page */
598 flush_dcache_page(miter->page);
599 }
600 sg_miter_stop(miter);
601
602 /* For whatever reason there is sometime one word more in the fifo then
603 * requested */
604 timeout = 1000;
605 status = readl(host->base + JZ_REG_MMC_STATUS);
606 while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) {
607 d = readl(fifo_addr);
608 status = readl(host->base + JZ_REG_MMC_STATUS);
609 }
610
611 return false;
612
613 poll_timeout:
614 miter->consumed = (void *)buf - miter->addr;
615 data->bytes_xfered += miter->consumed;
616 sg_miter_stop(miter);
617
618 return true;
619 }
620
621 static void jz4740_mmc_timeout(struct timer_list *t)
622 {
623 struct jz4740_mmc_host *host = from_timer(host, t, timeout_timer);
624
625 if (!test_and_clear_bit(0, &host->waiting))
626 return;
627
628 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false);
629
630 host->req->cmd->error = -ETIMEDOUT;
631 jz4740_mmc_request_done(host);
632 }
633
634 static void jz4740_mmc_read_response(struct jz4740_mmc_host *host,
635 struct mmc_command *cmd)
636 {
637 int i;
638 uint16_t tmp;
639 void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO;
640
641 if (cmd->flags & MMC_RSP_136) {
642 tmp = readw(fifo_addr);
643 for (i = 0; i < 4; ++i) {
644 cmd->resp[i] = tmp << 24;
645 tmp = readw(fifo_addr);
646 cmd->resp[i] |= tmp << 8;
647 tmp = readw(fifo_addr);
648 cmd->resp[i] |= tmp >> 8;
649 }
650 } else {
651 cmd->resp[0] = readw(fifo_addr) << 24;
652 cmd->resp[0] |= readw(fifo_addr) << 8;
653 cmd->resp[0] |= readw(fifo_addr) & 0xff;
654 }
655 }
656
657 static void jz4740_mmc_send_command(struct jz4740_mmc_host *host,
658 struct mmc_command *cmd)
659 {
660 uint32_t cmdat = host->cmdat;
661
662 host->cmdat &= ~JZ_MMC_CMDAT_INIT;
663 jz4740_mmc_clock_disable(host);
664
665 host->cmd = cmd;
666
667 if (cmd->flags & MMC_RSP_BUSY)
668 cmdat |= JZ_MMC_CMDAT_BUSY;
669
670 switch (mmc_resp_type(cmd)) {
671 case MMC_RSP_R1B:
672 case MMC_RSP_R1:
673 cmdat |= JZ_MMC_CMDAT_RSP_R1;
674 break;
675 case MMC_RSP_R2:
676 cmdat |= JZ_MMC_CMDAT_RSP_R2;
677 break;
678 case MMC_RSP_R3:
679 cmdat |= JZ_MMC_CMDAT_RSP_R3;
680 break;
681 default:
682 break;
683 }
684
685 if (cmd->data) {
686 cmdat |= JZ_MMC_CMDAT_DATA_EN;
687 if (cmd->data->flags & MMC_DATA_WRITE)
688 cmdat |= JZ_MMC_CMDAT_WRITE;
689 if (host->use_dma) {
690 /*
691 * The 4780's MMC controller has integrated DMA ability
692 * in addition to being able to use the external DMA
693 * controller. It moves DMA control bits to a separate
694 * register. The DMA_SEL bit chooses the external
695 * controller over the integrated one. Earlier SoCs
696 * can only use the external controller, and have a
697 * single DMA enable bit in CMDAT.
698 */
699 if (host->version >= JZ_MMC_JZ4780) {
700 writel(JZ_MMC_DMAC_DMA_EN | JZ_MMC_DMAC_DMA_SEL,
701 host->base + JZ_REG_MMC_DMAC);
702 } else {
703 cmdat |= JZ_MMC_CMDAT_DMA_EN;
704 }
705 } else if (host->version >= JZ_MMC_JZ4780) {
706 writel(0, host->base + JZ_REG_MMC_DMAC);
707 }
708
709 writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN);
710 writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB);
711 }
712
713 writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD);
714 writel(cmd->arg, host->base + JZ_REG_MMC_ARG);
715 writel(cmdat, host->base + JZ_REG_MMC_CMDAT);
716
717 jz4740_mmc_clock_enable(host, 1);
718 }
719
720 static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host)
721 {
722 struct mmc_command *cmd = host->req->cmd;
723 struct mmc_data *data = cmd->data;
724 int direction;
725
726 if (data->flags & MMC_DATA_READ)
727 direction = SG_MITER_TO_SG;
728 else
729 direction = SG_MITER_FROM_SG;
730
731 sg_miter_start(&host->miter, data->sg, data->sg_len, direction);
732 }
733
734
735 static irqreturn_t jz_mmc_irq_worker(int irq, void *devid)
736 {
737 struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid;
738 struct mmc_command *cmd = host->req->cmd;
739 struct mmc_request *req = host->req;
740 struct mmc_data *data = cmd->data;
741 bool timeout = false;
742
743 if (cmd->error)
744 host->state = JZ4740_MMC_STATE_DONE;
745
746 switch (host->state) {
747 case JZ4740_MMC_STATE_READ_RESPONSE:
748 if (cmd->flags & MMC_RSP_PRESENT)
749 jz4740_mmc_read_response(host, cmd);
750
751 if (!data)
752 break;
753
754 jz_mmc_prepare_data_transfer(host);
755
756 case JZ4740_MMC_STATE_TRANSFER_DATA:
757 if (host->use_dma) {
758 /* Use DMA if enabled.
759 * Data transfer direction is defined later by
760 * relying on data flags in
761 * jz4740_mmc_prepare_dma_data() and
762 * jz4740_mmc_start_dma_transfer().
763 */
764 timeout = jz4740_mmc_start_dma_transfer(host, data);
765 data->bytes_xfered = data->blocks * data->blksz;
766 } else if (data->flags & MMC_DATA_READ)
767 /* Use PIO if DMA is not enabled.
768 * Data transfer direction was defined before
769 * by relying on data flags in
770 * jz_mmc_prepare_data_transfer().
771 */
772 timeout = jz4740_mmc_read_data(host, data);
773 else
774 timeout = jz4740_mmc_write_data(host, data);
775
776 if (unlikely(timeout)) {
777 host->state = JZ4740_MMC_STATE_TRANSFER_DATA;
778 break;
779 }
780
781 jz4740_mmc_transfer_check_state(host, data);
782
783 timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
784 if (unlikely(timeout)) {
785 host->state = JZ4740_MMC_STATE_SEND_STOP;
786 break;
787 }
788 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_DATA_TRAN_DONE);
789
790 case JZ4740_MMC_STATE_SEND_STOP:
791 if (!req->stop)
792 break;
793
794 jz4740_mmc_send_command(host, req->stop);
795
796 if (mmc_resp_type(req->stop) & MMC_RSP_BUSY) {
797 timeout = jz4740_mmc_poll_irq(host,
798 JZ_MMC_IRQ_PRG_DONE);
799 if (timeout) {
800 host->state = JZ4740_MMC_STATE_DONE;
801 break;
802 }
803 }
804 case JZ4740_MMC_STATE_DONE:
805 break;
806 }
807
808 if (!timeout)
809 jz4740_mmc_request_done(host);
810
811 return IRQ_HANDLED;
812 }
813
814 static irqreturn_t jz_mmc_irq(int irq, void *devid)
815 {
816 struct jz4740_mmc_host *host = devid;
817 struct mmc_command *cmd = host->cmd;
818 uint32_t irq_reg, status, tmp;
819
820 status = readl(host->base + JZ_REG_MMC_STATUS);
821 irq_reg = jz4740_mmc_read_irq_reg(host);
822
823 tmp = irq_reg;
824 irq_reg &= ~host->irq_mask;
825
826 tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ |
827 JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE);
828
829 if (tmp != irq_reg)
830 jz4740_mmc_write_irq_reg(host, tmp & ~irq_reg);
831
832 if (irq_reg & JZ_MMC_IRQ_SDIO) {
833 jz4740_mmc_write_irq_reg(host, JZ_MMC_IRQ_SDIO);
834 mmc_signal_sdio_irq(host->mmc);
835 irq_reg &= ~JZ_MMC_IRQ_SDIO;
836 }
837
838 if (host->req && cmd && irq_reg) {
839 if (test_and_clear_bit(0, &host->waiting)) {
840 del_timer(&host->timeout_timer);
841
842 if (status & JZ_MMC_STATUS_TIMEOUT_RES) {
843 cmd->error = -ETIMEDOUT;
844 } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) {
845 cmd->error = -EIO;
846 } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR |
847 JZ_MMC_STATUS_CRC_WRITE_ERROR)) {
848 if (cmd->data)
849 cmd->data->error = -EIO;
850 cmd->error = -EIO;
851 }
852
853 jz4740_mmc_set_irq_enabled(host, irq_reg, false);
854 jz4740_mmc_write_irq_reg(host, irq_reg);
855
856 return IRQ_WAKE_THREAD;
857 }
858 }
859
860 return IRQ_HANDLED;
861 }
862
863 static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate)
864 {
865 int div = 0;
866 int real_rate;
867
868 jz4740_mmc_clock_disable(host);
869 clk_set_rate(host->clk, host->mmc->f_max);
870
871 real_rate = clk_get_rate(host->clk);
872
873 while (real_rate > rate && div < 7) {
874 ++div;
875 real_rate >>= 1;
876 }
877
878 writew(div, host->base + JZ_REG_MMC_CLKRT);
879 return real_rate;
880 }
881
882 static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
883 {
884 struct jz4740_mmc_host *host = mmc_priv(mmc);
885
886 host->req = req;
887
888 jz4740_mmc_write_irq_reg(host, ~0);
889 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true);
890
891 host->state = JZ4740_MMC_STATE_READ_RESPONSE;
892 set_bit(0, &host->waiting);
893 mod_timer(&host->timeout_timer, jiffies + 5*HZ);
894 jz4740_mmc_send_command(host, req->cmd);
895 }
896
897 static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
898 {
899 struct jz4740_mmc_host *host = mmc_priv(mmc);
900 if (ios->clock)
901 jz4740_mmc_set_clock_rate(host, ios->clock);
902
903 switch (ios->power_mode) {
904 case MMC_POWER_UP:
905 jz4740_mmc_reset(host);
906 if (host->pdata && gpio_is_valid(host->pdata->gpio_power))
907 gpio_set_value(host->pdata->gpio_power,
908 !host->pdata->power_active_low);
909 host->cmdat |= JZ_MMC_CMDAT_INIT;
910 clk_prepare_enable(host->clk);
911 break;
912 case MMC_POWER_ON:
913 break;
914 default:
915 if (host->pdata && gpio_is_valid(host->pdata->gpio_power))
916 gpio_set_value(host->pdata->gpio_power,
917 host->pdata->power_active_low);
918 clk_disable_unprepare(host->clk);
919 break;
920 }
921
922 switch (ios->bus_width) {
923 case MMC_BUS_WIDTH_1:
924 host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
925 break;
926 case MMC_BUS_WIDTH_4:
927 host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT;
928 break;
929 default:
930 break;
931 }
932 }
933
934 static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
935 {
936 struct jz4740_mmc_host *host = mmc_priv(mmc);
937 jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable);
938 }
939
940 static const struct mmc_host_ops jz4740_mmc_ops = {
941 .request = jz4740_mmc_request,
942 .pre_req = jz4740_mmc_pre_request,
943 .post_req = jz4740_mmc_post_request,
944 .set_ios = jz4740_mmc_set_ios,
945 .get_ro = mmc_gpio_get_ro,
946 .get_cd = mmc_gpio_get_cd,
947 .enable_sdio_irq = jz4740_mmc_enable_sdio_irq,
948 };
949
950 static int jz4740_mmc_request_gpio(struct device *dev, int gpio,
951 const char *name, bool output, int value)
952 {
953 int ret;
954
955 if (!gpio_is_valid(gpio))
956 return 0;
957
958 ret = gpio_request(gpio, name);
959 if (ret) {
960 dev_err(dev, "Failed to request %s gpio: %d\n", name, ret);
961 return ret;
962 }
963
964 if (output)
965 gpio_direction_output(gpio, value);
966 else
967 gpio_direction_input(gpio);
968
969 return 0;
970 }
971
972 static int jz4740_mmc_request_gpios(struct mmc_host *mmc,
973 struct platform_device *pdev)
974 {
975 struct jz4740_mmc_platform_data *pdata = dev_get_platdata(&pdev->dev);
976 int ret = 0;
977
978 if (!pdata)
979 return 0;
980
981 if (!pdata->card_detect_active_low)
982 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
983 if (!pdata->read_only_active_low)
984 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
985
986 if (gpio_is_valid(pdata->gpio_card_detect)) {
987 ret = mmc_gpio_request_cd(mmc, pdata->gpio_card_detect, 0);
988 if (ret)
989 return ret;
990 }
991
992 if (gpio_is_valid(pdata->gpio_read_only)) {
993 ret = mmc_gpio_request_ro(mmc, pdata->gpio_read_only);
994 if (ret)
995 return ret;
996 }
997
998 return jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power,
999 "MMC read only", true, pdata->power_active_low);
1000 }
1001
1002 static void jz4740_mmc_free_gpios(struct platform_device *pdev)
1003 {
1004 struct jz4740_mmc_platform_data *pdata = dev_get_platdata(&pdev->dev);
1005
1006 if (!pdata)
1007 return;
1008
1009 if (gpio_is_valid(pdata->gpio_power))
1010 gpio_free(pdata->gpio_power);
1011 }
1012
1013 static const struct of_device_id jz4740_mmc_of_match[] = {
1014 { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 },
1015 { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 },
1016 {},
1017 };
1018 MODULE_DEVICE_TABLE(of, jz4740_mmc_of_match);
1019
1020 static int jz4740_mmc_probe(struct platform_device* pdev)
1021 {
1022 int ret;
1023 struct mmc_host *mmc;
1024 struct jz4740_mmc_host *host;
1025 const struct of_device_id *match;
1026 struct jz4740_mmc_platform_data *pdata;
1027
1028 pdata = dev_get_platdata(&pdev->dev);
1029
1030 mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev);
1031 if (!mmc) {
1032 dev_err(&pdev->dev, "Failed to alloc mmc host structure\n");
1033 return -ENOMEM;
1034 }
1035
1036 host = mmc_priv(mmc);
1037 host->pdata = pdata;
1038
1039 match = of_match_device(jz4740_mmc_of_match, &pdev->dev);
1040 if (match) {
1041 host->version = (enum jz4740_mmc_version)match->data;
1042 ret = mmc_of_parse(mmc);
1043 if (ret) {
1044 if (ret != -EPROBE_DEFER)
1045 dev_err(&pdev->dev,
1046 "could not parse of data: %d\n", ret);
1047 goto err_free_host;
1048 }
1049 } else {
1050 /* JZ4740 should be the only one using legacy probe */
1051 host->version = JZ_MMC_JZ4740;
1052 mmc->caps |= MMC_CAP_SDIO_IRQ;
1053 if (!(pdata && pdata->data_1bit))
1054 mmc->caps |= MMC_CAP_4_BIT_DATA;
1055 ret = jz4740_mmc_request_gpios(mmc, pdev);
1056 if (ret)
1057 goto err_free_host;
1058 }
1059
1060 host->irq = platform_get_irq(pdev, 0);
1061 if (host->irq < 0) {
1062 ret = host->irq;
1063 dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret);
1064 goto err_free_host;
1065 }
1066
1067 host->clk = devm_clk_get(&pdev->dev, "mmc");
1068 if (IS_ERR(host->clk)) {
1069 ret = PTR_ERR(host->clk);
1070 dev_err(&pdev->dev, "Failed to get mmc clock\n");
1071 goto err_free_host;
1072 }
1073
1074 host->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1075 host->base = devm_ioremap_resource(&pdev->dev, host->mem_res);
1076 if (IS_ERR(host->base)) {
1077 ret = PTR_ERR(host->base);
1078 dev_err(&pdev->dev, "Failed to ioremap base memory\n");
1079 goto err_free_host;
1080 }
1081
1082 mmc->ops = &jz4740_mmc_ops;
1083 if (!mmc->f_max)
1084 mmc->f_max = JZ_MMC_CLK_RATE;
1085 mmc->f_min = mmc->f_max / 128;
1086 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1087
1088 mmc->max_blk_size = (1 << 10) - 1;
1089 mmc->max_blk_count = (1 << 15) - 1;
1090 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1091
1092 mmc->max_segs = 128;
1093 mmc->max_seg_size = mmc->max_req_size;
1094
1095 host->mmc = mmc;
1096 host->pdev = pdev;
1097 spin_lock_init(&host->lock);
1098 host->irq_mask = ~0;
1099
1100 jz4740_mmc_reset(host);
1101
1102 ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0,
1103 dev_name(&pdev->dev), host);
1104 if (ret) {
1105 dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
1106 goto err_free_gpios;
1107 }
1108
1109 jz4740_mmc_clock_disable(host);
1110 timer_setup(&host->timeout_timer, jz4740_mmc_timeout, 0);
1111
1112 ret = jz4740_mmc_acquire_dma_channels(host);
1113 if (ret == -EPROBE_DEFER)
1114 goto err_free_irq;
1115 host->use_dma = !ret;
1116
1117 platform_set_drvdata(pdev, host);
1118 ret = mmc_add_host(mmc);
1119
1120 if (ret) {
1121 dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret);
1122 goto err_release_dma;
1123 }
1124 dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n");
1125
1126 dev_info(&pdev->dev, "Using %s, %d-bit mode\n",
1127 host->use_dma ? "DMA" : "PIO",
1128 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1129
1130 return 0;
1131
1132 err_release_dma:
1133 if (host->use_dma)
1134 jz4740_mmc_release_dma_channels(host);
1135 err_free_irq:
1136 free_irq(host->irq, host);
1137 err_free_gpios:
1138 jz4740_mmc_free_gpios(pdev);
1139 err_free_host:
1140 mmc_free_host(mmc);
1141
1142 return ret;
1143 }
1144
1145 static int jz4740_mmc_remove(struct platform_device *pdev)
1146 {
1147 struct jz4740_mmc_host *host = platform_get_drvdata(pdev);
1148
1149 del_timer_sync(&host->timeout_timer);
1150 jz4740_mmc_set_irq_enabled(host, 0xff, false);
1151 jz4740_mmc_reset(host);
1152
1153 mmc_remove_host(host->mmc);
1154
1155 free_irq(host->irq, host);
1156
1157 jz4740_mmc_free_gpios(pdev);
1158
1159 if (host->use_dma)
1160 jz4740_mmc_release_dma_channels(host);
1161
1162 mmc_free_host(host->mmc);
1163
1164 return 0;
1165 }
1166
1167 #ifdef CONFIG_PM_SLEEP
1168
1169 static int jz4740_mmc_suspend(struct device *dev)
1170 {
1171 return pinctrl_pm_select_sleep_state(dev);
1172 }
1173
1174 static int jz4740_mmc_resume(struct device *dev)
1175 {
1176 return pinctrl_pm_select_default_state(dev);
1177 }
1178
1179 static SIMPLE_DEV_PM_OPS(jz4740_mmc_pm_ops, jz4740_mmc_suspend,
1180 jz4740_mmc_resume);
1181 #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops)
1182 #else
1183 #define JZ4740_MMC_PM_OPS NULL
1184 #endif
1185
1186 static struct platform_driver jz4740_mmc_driver = {
1187 .probe = jz4740_mmc_probe,
1188 .remove = jz4740_mmc_remove,
1189 .driver = {
1190 .name = "jz4740-mmc",
1191 .of_match_table = of_match_ptr(jz4740_mmc_of_match),
1192 .pm = JZ4740_MMC_PM_OPS,
1193 },
1194 };
1195
1196 module_platform_driver(jz4740_mmc_driver);
1197
1198 MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver");
1199 MODULE_LICENSE("GPL");
1200 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
Linux with added FPC-III support