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i2c: aspeed: Fix initial values of master and slave state
[linux/fpc-iii.git] / drivers / mmc / host / sdhci-pci-core.c
blob77dd3521daae4aee806190db9f7970b44b87daa7
1 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
2 *
3 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or (at
8 * your option) any later version.
9 *
10 * Thanks to the following companies for their support:
11 *
12 * - JMicron (hardware and technical support)
13 */
14
15 #include <linux/string.h>
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/device.h>
23 #include <linux/mmc/host.h>
24 #include <linux/mmc/mmc.h>
25 #include <linux/scatterlist.h>
26 #include <linux/io.h>
27 #include <linux/gpio.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/mmc/slot-gpio.h>
30 #include <linux/mmc/sdhci-pci-data.h>
31 #include <linux/acpi.h>
32
33 #include "cqhci.h"
34
35 #include "sdhci.h"
36 #include "sdhci-pci.h"
37
38 static void sdhci_pci_hw_reset(struct sdhci_host *host);
39
40 #ifdef CONFIG_PM_SLEEP
41 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
42 {
43 mmc_pm_flag_t pm_flags = 0;
44 bool cap_cd_wake = false;
45 int i;
46
47 for (i = 0; i < chip->num_slots; i++) {
48 struct sdhci_pci_slot *slot = chip->slots[i];
49
50 if (slot) {
51 pm_flags |= slot->host->mmc->pm_flags;
52 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
53 cap_cd_wake = true;
54 }
55 }
56
57 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
58 return device_wakeup_enable(&chip->pdev->dev);
59 else if (!cap_cd_wake)
60 return device_wakeup_disable(&chip->pdev->dev);
61
62 return 0;
63 }
64
65 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
66 {
67 int i, ret;
68
69 sdhci_pci_init_wakeup(chip);
70
71 for (i = 0; i < chip->num_slots; i++) {
72 struct sdhci_pci_slot *slot = chip->slots[i];
73 struct sdhci_host *host;
74
75 if (!slot)
76 continue;
77
78 host = slot->host;
79
80 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
81 mmc_retune_needed(host->mmc);
82
83 ret = sdhci_suspend_host(host);
84 if (ret)
85 goto err_pci_suspend;
86
87 if (device_may_wakeup(&chip->pdev->dev))
88 mmc_gpio_set_cd_wake(host->mmc, true);
89 }
90
91 return 0;
92
93 err_pci_suspend:
94 while (--i >= 0)
95 sdhci_resume_host(chip->slots[i]->host);
96 return ret;
97 }
98
99 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
100 {
101 struct sdhci_pci_slot *slot;
102 int i, ret;
103
104 for (i = 0; i < chip->num_slots; i++) {
105 slot = chip->slots[i];
106 if (!slot)
107 continue;
108
109 ret = sdhci_resume_host(slot->host);
110 if (ret)
111 return ret;
112
113 mmc_gpio_set_cd_wake(slot->host->mmc, false);
114 }
115
116 return 0;
117 }
118
119 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
120 {
121 int ret;
122
123 ret = cqhci_suspend(chip->slots[0]->host->mmc);
124 if (ret)
125 return ret;
126
127 return sdhci_pci_suspend_host(chip);
128 }
129
130 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
131 {
132 int ret;
133
134 ret = sdhci_pci_resume_host(chip);
135 if (ret)
136 return ret;
137
138 return cqhci_resume(chip->slots[0]->host->mmc);
139 }
140 #endif
141
142 #ifdef CONFIG_PM
143 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
144 {
145 struct sdhci_pci_slot *slot;
146 struct sdhci_host *host;
147 int i, ret;
148
149 for (i = 0; i < chip->num_slots; i++) {
150 slot = chip->slots[i];
151 if (!slot)
152 continue;
153
154 host = slot->host;
155
156 ret = sdhci_runtime_suspend_host(host);
157 if (ret)
158 goto err_pci_runtime_suspend;
159
160 if (chip->rpm_retune &&
161 host->tuning_mode != SDHCI_TUNING_MODE_3)
162 mmc_retune_needed(host->mmc);
163 }
164
165 return 0;
166
167 err_pci_runtime_suspend:
168 while (--i >= 0)
169 sdhci_runtime_resume_host(chip->slots[i]->host);
170 return ret;
171 }
172
173 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
174 {
175 struct sdhci_pci_slot *slot;
176 int i, ret;
177
178 for (i = 0; i < chip->num_slots; i++) {
179 slot = chip->slots[i];
180 if (!slot)
181 continue;
182
183 ret = sdhci_runtime_resume_host(slot->host);
184 if (ret)
185 return ret;
186 }
187
188 return 0;
189 }
190
191 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
192 {
193 int ret;
194
195 ret = cqhci_suspend(chip->slots[0]->host->mmc);
196 if (ret)
197 return ret;
198
199 return sdhci_pci_runtime_suspend_host(chip);
200 }
201
202 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
203 {
204 int ret;
205
206 ret = sdhci_pci_runtime_resume_host(chip);
207 if (ret)
208 return ret;
209
210 return cqhci_resume(chip->slots[0]->host->mmc);
211 }
212 #endif
213
214 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
215 {
216 int cmd_error = 0;
217 int data_error = 0;
218
219 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
220 return intmask;
221
222 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
223
224 return 0;
225 }
226
227 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
228 {
229 sdhci_dumpregs(mmc_priv(mmc));
230 }
231
232 /*****************************************************************************\
233 * *
234 * Hardware specific quirk handling *
235 * *
236 \*****************************************************************************/
237
238 static int ricoh_probe(struct sdhci_pci_chip *chip)
239 {
240 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
241 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
242 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
243 return 0;
244 }
245
246 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
247 {
248 slot->host->caps =
249 ((0x21 << SDHCI_TIMEOUT_CLK_SHIFT)
250 & SDHCI_TIMEOUT_CLK_MASK) |
251
252 ((0x21 << SDHCI_CLOCK_BASE_SHIFT)
253 & SDHCI_CLOCK_BASE_MASK) |
254
255 SDHCI_TIMEOUT_CLK_UNIT |
256 SDHCI_CAN_VDD_330 |
257 SDHCI_CAN_DO_HISPD |
258 SDHCI_CAN_DO_SDMA;
259 return 0;
260 }
261
262 #ifdef CONFIG_PM_SLEEP
263 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
264 {
265 /* Apply a delay to allow controller to settle */
266 /* Otherwise it becomes confused if card state changed
267 during suspend */
268 msleep(500);
269 return sdhci_pci_resume_host(chip);
270 }
271 #endif
272
273 static const struct sdhci_pci_fixes sdhci_ricoh = {
274 .probe = ricoh_probe,
275 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
276 SDHCI_QUIRK_FORCE_DMA |
277 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
278 };
279
280 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
281 .probe_slot = ricoh_mmc_probe_slot,
282 #ifdef CONFIG_PM_SLEEP
283 .resume = ricoh_mmc_resume,
284 #endif
285 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
286 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
287 SDHCI_QUIRK_NO_CARD_NO_RESET |
288 SDHCI_QUIRK_MISSING_CAPS
289 };
290
291 static const struct sdhci_pci_fixes sdhci_ene_712 = {
292 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
293 SDHCI_QUIRK_BROKEN_DMA,
294 };
295
296 static const struct sdhci_pci_fixes sdhci_ene_714 = {
297 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
298 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS |
299 SDHCI_QUIRK_BROKEN_DMA,
300 };
301
302 static const struct sdhci_pci_fixes sdhci_cafe = {
303 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
304 SDHCI_QUIRK_NO_BUSY_IRQ |
305 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
306 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
307 };
308
309 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
310 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
311 };
312
313 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
314 {
315 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
316 return 0;
317 }
318
319 /*
320 * ADMA operation is disabled for Moorestown platform due to
321 * hardware bugs.
322 */
323 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
324 {
325 /*
326 * slots number is fixed here for MRST as SDIO3/5 are never used and
327 * have hardware bugs.
328 */
329 chip->num_slots = 1;
330 return 0;
331 }
332
333 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
334 {
335 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
336 return 0;
337 }
338
339 #ifdef CONFIG_PM
340
341 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id)
342 {
343 struct sdhci_pci_slot *slot = dev_id;
344 struct sdhci_host *host = slot->host;
345
346 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
347 return IRQ_HANDLED;
348 }
349
350 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
351 {
352 int err, irq, gpio = slot->cd_gpio;
353
354 slot->cd_gpio = -EINVAL;
355 slot->cd_irq = -EINVAL;
356
357 if (!gpio_is_valid(gpio))
358 return;
359
360 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd");
361 if (err < 0)
362 goto out;
363
364 err = gpio_direction_input(gpio);
365 if (err < 0)
366 goto out_free;
367
368 irq = gpio_to_irq(gpio);
369 if (irq < 0)
370 goto out_free;
371
372 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING |
373 IRQF_TRIGGER_FALLING, "sd_cd", slot);
374 if (err)
375 goto out_free;
376
377 slot->cd_gpio = gpio;
378 slot->cd_irq = irq;
379
380 return;
381
382 out_free:
383 devm_gpio_free(&slot->chip->pdev->dev, gpio);
384 out:
385 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n");
386 }
387
388 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
389 {
390 if (slot->cd_irq >= 0)
391 free_irq(slot->cd_irq, slot);
392 }
393
394 #else
395
396 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot)
397 {
398 }
399
400 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot)
401 {
402 }
403
404 #endif
405
406 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
407 {
408 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
409 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
410 return 0;
411 }
412
413 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
414 {
415 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
416 return 0;
417 }
418
419 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
420 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
421 .probe_slot = mrst_hc_probe_slot,
422 };
423
424 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
425 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
426 .probe = mrst_hc_probe,
427 };
428
429 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
430 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
431 .allow_runtime_pm = true,
432 .own_cd_for_runtime_pm = true,
433 };
434
435 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
436 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
437 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
438 .allow_runtime_pm = true,
439 .probe_slot = mfd_sdio_probe_slot,
440 };
441
442 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
443 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
444 .allow_runtime_pm = true,
445 .probe_slot = mfd_emmc_probe_slot,
446 };
447
448 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
449 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
450 .probe_slot = pch_hc_probe_slot,
451 };
452
453 enum {
454 INTEL_DSM_FNS = 0,
455 INTEL_DSM_V18_SWITCH = 3,
456 INTEL_DSM_V33_SWITCH = 4,
457 INTEL_DSM_DRV_STRENGTH = 9,
458 INTEL_DSM_D3_RETUNE = 10,
459 };
460
461 struct intel_host {
462 u32 dsm_fns;
463 int drv_strength;
464 bool d3_retune;
465 };
466
467 static const guid_t intel_dsm_guid =
468 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
469 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
470
471 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
472 unsigned int fn, u32 *result)
473 {
474 union acpi_object *obj;
475 int err = 0;
476 size_t len;
477
478 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
479 if (!obj)
480 return -EOPNOTSUPP;
481
482 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
483 err = -EINVAL;
484 goto out;
485 }
486
487 len = min_t(size_t, obj->buffer.length, 4);
488
489 *result = 0;
490 memcpy(result, obj->buffer.pointer, len);
491 out:
492 ACPI_FREE(obj);
493
494 return err;
495 }
496
497 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
498 unsigned int fn, u32 *result)
499 {
500 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
501 return -EOPNOTSUPP;
502
503 return __intel_dsm(intel_host, dev, fn, result);
504 }
505
506 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
507 struct mmc_host *mmc)
508 {
509 int err;
510 u32 val;
511
512 intel_host->d3_retune = true;
513
514 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
515 if (err) {
516 pr_debug("%s: DSM not supported, error %d\n",
517 mmc_hostname(mmc), err);
518 return;
519 }
520
521 pr_debug("%s: DSM function mask %#x\n",
522 mmc_hostname(mmc), intel_host->dsm_fns);
523
524 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
525 intel_host->drv_strength = err ? 0 : val;
526
527 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
528 intel_host->d3_retune = err ? true : !!val;
529 }
530
531 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
532 {
533 u8 reg;
534
535 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
536 reg |= 0x10;
537 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
538 /* For eMMC, minimum is 1us but give it 9us for good measure */
539 udelay(9);
540 reg &= ~0x10;
541 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
542 /* For eMMC, minimum is 200us but give it 300us for good measure */
543 usleep_range(300, 1000);
544 }
545
546 static int intel_select_drive_strength(struct mmc_card *card,
547 unsigned int max_dtr, int host_drv,
548 int card_drv, int *drv_type)
549 {
550 struct sdhci_host *host = mmc_priv(card->host);
551 struct sdhci_pci_slot *slot = sdhci_priv(host);
552 struct intel_host *intel_host = sdhci_pci_priv(slot);
553
554 return intel_host->drv_strength;
555 }
556
557 static int bxt_get_cd(struct mmc_host *mmc)
558 {
559 int gpio_cd = mmc_gpio_get_cd(mmc);
560 struct sdhci_host *host = mmc_priv(mmc);
561 unsigned long flags;
562 int ret = 0;
563
564 if (!gpio_cd)
565 return 0;
566
567 spin_lock_irqsave(&host->lock, flags);
568
569 if (host->flags & SDHCI_DEVICE_DEAD)
570 goto out;
571
572 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
573 out:
574 spin_unlock_irqrestore(&host->lock, flags);
575
576 return ret;
577 }
578
579 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
580 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
581
582 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
583 unsigned short vdd)
584 {
585 int cntr;
586 u8 reg;
587
588 sdhci_set_power(host, mode, vdd);
589
590 if (mode == MMC_POWER_OFF)
591 return;
592
593 /*
594 * Bus power might not enable after D3 -> D0 transition due to the
595 * present state not yet having propagated. Retry for up to 2ms.
596 */
597 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
598 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
599 if (reg & SDHCI_POWER_ON)
600 break;
601 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
602 reg |= SDHCI_POWER_ON;
603 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
604 }
605 }
606
607 #define INTEL_HS400_ES_REG 0x78
608 #define INTEL_HS400_ES_BIT BIT(0)
609
610 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
611 struct mmc_ios *ios)
612 {
613 struct sdhci_host *host = mmc_priv(mmc);
614 u32 val;
615
616 val = sdhci_readl(host, INTEL_HS400_ES_REG);
617 if (ios->enhanced_strobe)
618 val |= INTEL_HS400_ES_BIT;
619 else
620 val &= ~INTEL_HS400_ES_BIT;
621 sdhci_writel(host, val, INTEL_HS400_ES_REG);
622 }
623
624 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
625 struct mmc_ios *ios)
626 {
627 struct device *dev = mmc_dev(mmc);
628 struct sdhci_host *host = mmc_priv(mmc);
629 struct sdhci_pci_slot *slot = sdhci_priv(host);
630 struct intel_host *intel_host = sdhci_pci_priv(slot);
631 unsigned int fn;
632 u32 result = 0;
633 int err;
634
635 err = sdhci_start_signal_voltage_switch(mmc, ios);
636 if (err)
637 return err;
638
639 switch (ios->signal_voltage) {
640 case MMC_SIGNAL_VOLTAGE_330:
641 fn = INTEL_DSM_V33_SWITCH;
642 break;
643 case MMC_SIGNAL_VOLTAGE_180:
644 fn = INTEL_DSM_V18_SWITCH;
645 break;
646 default:
647 return 0;
648 }
649
650 err = intel_dsm(intel_host, dev, fn, &result);
651 pr_debug("%s: %s DSM fn %u error %d result %u\n",
652 mmc_hostname(mmc), __func__, fn, err, result);
653
654 return 0;
655 }
656
657 static const struct sdhci_ops sdhci_intel_byt_ops = {
658 .set_clock = sdhci_set_clock,
659 .set_power = sdhci_intel_set_power,
660 .enable_dma = sdhci_pci_enable_dma,
661 .set_bus_width = sdhci_set_bus_width,
662 .reset = sdhci_reset,
663 .set_uhs_signaling = sdhci_set_uhs_signaling,
664 .hw_reset = sdhci_pci_hw_reset,
665 };
666
667 static const struct sdhci_ops sdhci_intel_glk_ops = {
668 .set_clock = sdhci_set_clock,
669 .set_power = sdhci_intel_set_power,
670 .enable_dma = sdhci_pci_enable_dma,
671 .set_bus_width = sdhci_set_bus_width,
672 .reset = sdhci_reset,
673 .set_uhs_signaling = sdhci_set_uhs_signaling,
674 .hw_reset = sdhci_pci_hw_reset,
675 .irq = sdhci_cqhci_irq,
676 };
677
678 static void byt_read_dsm(struct sdhci_pci_slot *slot)
679 {
680 struct intel_host *intel_host = sdhci_pci_priv(slot);
681 struct device *dev = &slot->chip->pdev->dev;
682 struct mmc_host *mmc = slot->host->mmc;
683
684 intel_dsm_init(intel_host, dev, mmc);
685 slot->chip->rpm_retune = intel_host->d3_retune;
686 }
687
688 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
689 {
690 int err = sdhci_execute_tuning(mmc, opcode);
691 struct sdhci_host *host = mmc_priv(mmc);
692
693 if (err)
694 return err;
695
696 /*
697 * Tuning can leave the IP in an active state (Buffer Read Enable bit
698 * set) which prevents the entry to low power states (i.e. S0i3). Data
699 * reset will clear it.
700 */
701 sdhci_reset(host, SDHCI_RESET_DATA);
702
703 return 0;
704 }
705
706 static void byt_probe_slot(struct sdhci_pci_slot *slot)
707 {
708 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
709
710 byt_read_dsm(slot);
711
712 ops->execute_tuning = intel_execute_tuning;
713 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
714 }
715
716 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
717 {
718 byt_probe_slot(slot);
719 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
720 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
721 MMC_CAP_CMD_DURING_TFR |
722 MMC_CAP_WAIT_WHILE_BUSY;
723 slot->hw_reset = sdhci_pci_int_hw_reset;
724 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
725 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
726 slot->host->mmc_host_ops.select_drive_strength =
727 intel_select_drive_strength;
728 return 0;
729 }
730
731 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
732 {
733 int ret = byt_emmc_probe_slot(slot);
734
735 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
736
737 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
738 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES,
739 slot->host->mmc_host_ops.hs400_enhanced_strobe =
740 intel_hs400_enhanced_strobe;
741 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
742 }
743
744 return ret;
745 }
746
747 static const struct cqhci_host_ops glk_cqhci_ops = {
748 .enable = sdhci_cqe_enable,
749 .disable = sdhci_cqe_disable,
750 .dumpregs = sdhci_pci_dumpregs,
751 };
752
753 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
754 {
755 struct device *dev = &slot->chip->pdev->dev;
756 struct sdhci_host *host = slot->host;
757 struct cqhci_host *cq_host;
758 bool dma64;
759 int ret;
760
761 ret = sdhci_setup_host(host);
762 if (ret)
763 return ret;
764
765 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
766 if (!cq_host) {
767 ret = -ENOMEM;
768 goto cleanup;
769 }
770
771 cq_host->mmio = host->ioaddr + 0x200;
772 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
773 cq_host->ops = &glk_cqhci_ops;
774
775 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
776 if (dma64)
777 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
778
779 ret = cqhci_init(cq_host, host->mmc, dma64);
780 if (ret)
781 goto cleanup;
782
783 ret = __sdhci_add_host(host);
784 if (ret)
785 goto cleanup;
786
787 return 0;
788
789 cleanup:
790 sdhci_cleanup_host(host);
791 return ret;
792 }
793
794 #ifdef CONFIG_ACPI
795 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
796 {
797 acpi_status status;
798 unsigned long long max_freq;
799
800 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
801 "MXFQ", NULL, &max_freq);
802 if (ACPI_FAILURE(status)) {
803 dev_err(&slot->chip->pdev->dev,
804 "MXFQ not found in acpi table\n");
805 return -EINVAL;
806 }
807
808 slot->host->mmc->f_max = max_freq * 1000000;
809
810 return 0;
811 }
812 #else
813 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
814 {
815 return 0;
816 }
817 #endif
818
819 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
820 {
821 int err;
822
823 byt_probe_slot(slot);
824
825 err = ni_set_max_freq(slot);
826 if (err)
827 return err;
828
829 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
830 MMC_CAP_WAIT_WHILE_BUSY;
831 return 0;
832 }
833
834 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
835 {
836 byt_probe_slot(slot);
837 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
838 MMC_CAP_WAIT_WHILE_BUSY;
839 return 0;
840 }
841
842 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
843 {
844 byt_probe_slot(slot);
845 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
846 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
847 slot->cd_idx = 0;
848 slot->cd_override_level = true;
849 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
850 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
851 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
852 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
853 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
854
855 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
856 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
857 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
858
859 return 0;
860 }
861
862 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
863 .allow_runtime_pm = true,
864 .probe_slot = byt_emmc_probe_slot,
865 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
866 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
867 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
868 SDHCI_QUIRK2_STOP_WITH_TC,
869 .ops = &sdhci_intel_byt_ops,
870 .priv_size = sizeof(struct intel_host),
871 };
872
873 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
874 .allow_runtime_pm = true,
875 .probe_slot = glk_emmc_probe_slot,
876 .add_host = glk_emmc_add_host,
877 #ifdef CONFIG_PM_SLEEP
878 .suspend = sdhci_cqhci_suspend,
879 .resume = sdhci_cqhci_resume,
880 #endif
881 #ifdef CONFIG_PM
882 .runtime_suspend = sdhci_cqhci_runtime_suspend,
883 .runtime_resume = sdhci_cqhci_runtime_resume,
884 #endif
885 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
886 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
887 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
888 SDHCI_QUIRK2_STOP_WITH_TC,
889 .ops = &sdhci_intel_glk_ops,
890 .priv_size = sizeof(struct intel_host),
891 };
892
893 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
894 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
895 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
896 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
897 .allow_runtime_pm = true,
898 .probe_slot = ni_byt_sdio_probe_slot,
899 .ops = &sdhci_intel_byt_ops,
900 .priv_size = sizeof(struct intel_host),
901 };
902
903 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
904 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
905 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
906 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
907 .allow_runtime_pm = true,
908 .probe_slot = byt_sdio_probe_slot,
909 .ops = &sdhci_intel_byt_ops,
910 .priv_size = sizeof(struct intel_host),
911 };
912
913 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
914 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
915 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
916 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
917 SDHCI_QUIRK2_STOP_WITH_TC,
918 .allow_runtime_pm = true,
919 .own_cd_for_runtime_pm = true,
920 .probe_slot = byt_sd_probe_slot,
921 .ops = &sdhci_intel_byt_ops,
922 .priv_size = sizeof(struct intel_host),
923 };
924
925 /* Define Host controllers for Intel Merrifield platform */
926 #define INTEL_MRFLD_EMMC_0 0
927 #define INTEL_MRFLD_EMMC_1 1
928 #define INTEL_MRFLD_SD 2
929 #define INTEL_MRFLD_SDIO 3
930
931 #ifdef CONFIG_ACPI
932 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
933 {
934 struct acpi_device *device, *child;
935
936 device = ACPI_COMPANION(&slot->chip->pdev->dev);
937 if (!device)
938 return;
939
940 acpi_device_fix_up_power(device);
941 list_for_each_entry(child, &device->children, node)
942 if (child->status.present && child->status.enabled)
943 acpi_device_fix_up_power(child);
944 }
945 #else
946 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
947 #endif
948
949 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
950 {
951 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
952
953 switch (func) {
954 case INTEL_MRFLD_EMMC_0:
955 case INTEL_MRFLD_EMMC_1:
956 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
957 MMC_CAP_8_BIT_DATA |
958 MMC_CAP_1_8V_DDR;
959 break;
960 case INTEL_MRFLD_SD:
961 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
962 break;
963 case INTEL_MRFLD_SDIO:
964 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
965 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
966 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
967 MMC_CAP_POWER_OFF_CARD;
968 break;
969 default:
970 return -ENODEV;
971 }
972
973 intel_mrfld_mmc_fix_up_power_slot(slot);
974 return 0;
975 }
976
977 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
978 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
979 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
980 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
981 .allow_runtime_pm = true,
982 .probe_slot = intel_mrfld_mmc_probe_slot,
983 };
984
985 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
986 {
987 u8 scratch;
988 int ret;
989
990 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
991 if (ret)
992 return ret;
993
994 /*
995 * Turn PMOS on [bit 0], set over current detection to 2.4 V
996 * [bit 1:2] and enable over current debouncing [bit 6].
997 */
998 if (on)
999 scratch |= 0x47;
1000 else
1001 scratch &= ~0x47;
1002
1003 return pci_write_config_byte(chip->pdev, 0xAE, scratch);
1004 }
1005
1006 static int jmicron_probe(struct sdhci_pci_chip *chip)
1007 {
1008 int ret;
1009 u16 mmcdev = 0;
1010
1011 if (chip->pdev->revision == 0) {
1012 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1013 SDHCI_QUIRK_32BIT_DMA_SIZE |
1014 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1015 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1016 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1017 }
1018
1019 /*
1020 * JMicron chips can have two interfaces to the same hardware
1021 * in order to work around limitations in Microsoft's driver.
1022 * We need to make sure we only bind to one of them.
1023 *
1024 * This code assumes two things:
1025 *
1026 * 1. The PCI code adds subfunctions in order.
1027 *
1028 * 2. The MMC interface has a lower subfunction number
1029 * than the SD interface.
1030 */
1031 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1032 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1033 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1034 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1035
1036 if (mmcdev) {
1037 struct pci_dev *sd_dev;
1038
1039 sd_dev = NULL;
1040 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1041 mmcdev, sd_dev)) != NULL) {
1042 if ((PCI_SLOT(chip->pdev->devfn) ==
1043 PCI_SLOT(sd_dev->devfn)) &&
1044 (chip->pdev->bus == sd_dev->bus))
1045 break;
1046 }
1047
1048 if (sd_dev) {
1049 pci_dev_put(sd_dev);
1050 dev_info(&chip->pdev->dev, "Refusing to bind to "
1051 "secondary interface.\n");
1052 return -ENODEV;
1053 }
1054 }
1055
1056 /*
1057 * JMicron chips need a bit of a nudge to enable the power
1058 * output pins.
1059 */
1060 ret = jmicron_pmos(chip, 1);
1061 if (ret) {
1062 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1063 return ret;
1064 }
1065
1066 /* quirk for unsable RO-detection on JM388 chips */
1067 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1068 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1069 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1070
1071 return 0;
1072 }
1073
1074 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1075 {
1076 u8 scratch;
1077
1078 scratch = readb(host->ioaddr + 0xC0);
1079
1080 if (on)
1081 scratch |= 0x01;
1082 else
1083 scratch &= ~0x01;
1084
1085 writeb(scratch, host->ioaddr + 0xC0);
1086 }
1087
1088 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1089 {
1090 if (slot->chip->pdev->revision == 0) {
1091 u16 version;
1092
1093 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1094 version = (version & SDHCI_VENDOR_VER_MASK) >>
1095 SDHCI_VENDOR_VER_SHIFT;
1096
1097 /*
1098 * Older versions of the chip have lots of nasty glitches
1099 * in the ADMA engine. It's best just to avoid it
1100 * completely.
1101 */
1102 if (version < 0xAC)
1103 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1104 }
1105
1106 /* JM388 MMC doesn't support 1.8V while SD supports it */
1107 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1108 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1109 MMC_VDD_29_30 | MMC_VDD_30_31 |
1110 MMC_VDD_165_195; /* allow 1.8V */
1111 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1112 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1113 }
1114
1115 /*
1116 * The secondary interface requires a bit set to get the
1117 * interrupts.
1118 */
1119 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1120 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1121 jmicron_enable_mmc(slot->host, 1);
1122
1123 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1124
1125 return 0;
1126 }
1127
1128 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1129 {
1130 if (dead)
1131 return;
1132
1133 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1134 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1135 jmicron_enable_mmc(slot->host, 0);
1136 }
1137
1138 #ifdef CONFIG_PM_SLEEP
1139 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1140 {
1141 int i, ret;
1142
1143 ret = sdhci_pci_suspend_host(chip);
1144 if (ret)
1145 return ret;
1146
1147 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1148 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1149 for (i = 0; i < chip->num_slots; i++)
1150 jmicron_enable_mmc(chip->slots[i]->host, 0);
1151 }
1152
1153 return 0;
1154 }
1155
1156 static int jmicron_resume(struct sdhci_pci_chip *chip)
1157 {
1158 int ret, i;
1159
1160 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1161 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1162 for (i = 0; i < chip->num_slots; i++)
1163 jmicron_enable_mmc(chip->slots[i]->host, 1);
1164 }
1165
1166 ret = jmicron_pmos(chip, 1);
1167 if (ret) {
1168 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1169 return ret;
1170 }
1171
1172 return sdhci_pci_resume_host(chip);
1173 }
1174 #endif
1175
1176 static const struct sdhci_pci_fixes sdhci_o2 = {
1177 .probe = sdhci_pci_o2_probe,
1178 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1179 .quirks2 = SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD,
1180 .probe_slot = sdhci_pci_o2_probe_slot,
1181 #ifdef CONFIG_PM_SLEEP
1182 .resume = sdhci_pci_o2_resume,
1183 #endif
1184 };
1185
1186 static const struct sdhci_pci_fixes sdhci_jmicron = {
1187 .probe = jmicron_probe,
1188
1189 .probe_slot = jmicron_probe_slot,
1190 .remove_slot = jmicron_remove_slot,
1191
1192 #ifdef CONFIG_PM_SLEEP
1193 .suspend = jmicron_suspend,
1194 .resume = jmicron_resume,
1195 #endif
1196 };
1197
1198 /* SysKonnect CardBus2SDIO extra registers */
1199 #define SYSKT_CTRL 0x200
1200 #define SYSKT_RDFIFO_STAT 0x204
1201 #define SYSKT_WRFIFO_STAT 0x208
1202 #define SYSKT_POWER_DATA 0x20c
1203 #define SYSKT_POWER_330 0xef
1204 #define SYSKT_POWER_300 0xf8
1205 #define SYSKT_POWER_184 0xcc
1206 #define SYSKT_POWER_CMD 0x20d
1207 #define SYSKT_POWER_START (1 << 7)
1208 #define SYSKT_POWER_STATUS 0x20e
1209 #define SYSKT_POWER_STATUS_OK (1 << 0)
1210 #define SYSKT_BOARD_REV 0x210
1211 #define SYSKT_CHIP_REV 0x211
1212 #define SYSKT_CONF_DATA 0x212
1213 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1214 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1215 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1216
1217 static int syskt_probe(struct sdhci_pci_chip *chip)
1218 {
1219 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1220 chip->pdev->class &= ~0x0000FF;
1221 chip->pdev->class |= PCI_SDHCI_IFDMA;
1222 }
1223 return 0;
1224 }
1225
1226 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1227 {
1228 int tm, ps;
1229
1230 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1231 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1232 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1233 "board rev %d.%d, chip rev %d.%d\n",
1234 board_rev >> 4, board_rev & 0xf,
1235 chip_rev >> 4, chip_rev & 0xf);
1236 if (chip_rev >= 0x20)
1237 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1238
1239 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1240 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1241 udelay(50);
1242 tm = 10; /* Wait max 1 ms */
1243 do {
1244 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1245 if (ps & SYSKT_POWER_STATUS_OK)
1246 break;
1247 udelay(100);
1248 } while (--tm);
1249 if (!tm) {
1250 dev_err(&slot->chip->pdev->dev,
1251 "power regulator never stabilized");
1252 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1253 return -ENODEV;
1254 }
1255
1256 return 0;
1257 }
1258
1259 static const struct sdhci_pci_fixes sdhci_syskt = {
1260 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1261 .probe = syskt_probe,
1262 .probe_slot = syskt_probe_slot,
1263 };
1264
1265 static int via_probe(struct sdhci_pci_chip *chip)
1266 {
1267 if (chip->pdev->revision == 0x10)
1268 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1269
1270 return 0;
1271 }
1272
1273 static const struct sdhci_pci_fixes sdhci_via = {
1274 .probe = via_probe,
1275 };
1276
1277 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1278 {
1279 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1280 return 0;
1281 }
1282
1283 static const struct sdhci_pci_fixes sdhci_rtsx = {
1284 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1285 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1286 SDHCI_QUIRK2_BROKEN_DDR50,
1287 .probe_slot = rtsx_probe_slot,
1288 };
1289
1290 /*AMD chipset generation*/
1291 enum amd_chipset_gen {
1292 AMD_CHIPSET_BEFORE_ML,
1293 AMD_CHIPSET_CZ,
1294 AMD_CHIPSET_NL,
1295 AMD_CHIPSET_UNKNOWN,
1296 };
1297
1298 /* AMD registers */
1299 #define AMD_SD_AUTO_PATTERN 0xB8
1300 #define AMD_MSLEEP_DURATION 4
1301 #define AMD_SD_MISC_CONTROL 0xD0
1302 #define AMD_MAX_TUNE_VALUE 0x0B
1303 #define AMD_AUTO_TUNE_SEL 0x10800
1304 #define AMD_FIFO_PTR 0x30
1305 #define AMD_BIT_MASK 0x1F
1306
1307 static void amd_tuning_reset(struct sdhci_host *host)
1308 {
1309 unsigned int val;
1310
1311 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1312 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1313 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1314
1315 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1316 val &= ~SDHCI_CTRL_EXEC_TUNING;
1317 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1318 }
1319
1320 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1321 {
1322 unsigned int val;
1323
1324 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1325 val &= ~AMD_BIT_MASK;
1326 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1327 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1328 }
1329
1330 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1331 {
1332 unsigned int val;
1333
1334 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1335 val |= AMD_FIFO_PTR;
1336 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1337 }
1338
1339 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1340 {
1341 struct sdhci_pci_slot *slot = sdhci_priv(host);
1342 struct pci_dev *pdev = slot->chip->pdev;
1343 u8 valid_win = 0;
1344 u8 valid_win_max = 0;
1345 u8 valid_win_end = 0;
1346 u8 ctrl, tune_around;
1347
1348 amd_tuning_reset(host);
1349
1350 for (tune_around = 0; tune_around < 12; tune_around++) {
1351 amd_config_tuning_phase(pdev, tune_around);
1352
1353 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1354 valid_win = 0;
1355 msleep(AMD_MSLEEP_DURATION);
1356 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1357 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1358 } else if (++valid_win > valid_win_max) {
1359 valid_win_max = valid_win;
1360 valid_win_end = tune_around;
1361 }
1362 }
1363
1364 if (!valid_win_max) {
1365 dev_err(&pdev->dev, "no tuning point found\n");
1366 return -EIO;
1367 }
1368
1369 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1370
1371 amd_enable_manual_tuning(pdev);
1372
1373 host->mmc->retune_period = 0;
1374
1375 return 0;
1376 }
1377
1378 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1379 {
1380 struct sdhci_host *host = mmc_priv(mmc);
1381
1382 /* AMD requires custom HS200 tuning */
1383 if (host->timing == MMC_TIMING_MMC_HS200)
1384 return amd_execute_tuning_hs200(host, opcode);
1385
1386 /* Otherwise perform standard SDHCI tuning */
1387 return sdhci_execute_tuning(mmc, opcode);
1388 }
1389
1390 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1391 {
1392 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1393
1394 ops->execute_tuning = amd_execute_tuning;
1395
1396 return 0;
1397 }
1398
1399 static int amd_probe(struct sdhci_pci_chip *chip)
1400 {
1401 struct pci_dev *smbus_dev;
1402 enum amd_chipset_gen gen;
1403
1404 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1405 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1406 if (smbus_dev) {
1407 gen = AMD_CHIPSET_BEFORE_ML;
1408 } else {
1409 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1410 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1411 if (smbus_dev) {
1412 if (smbus_dev->revision < 0x51)
1413 gen = AMD_CHIPSET_CZ;
1414 else
1415 gen = AMD_CHIPSET_NL;
1416 } else {
1417 gen = AMD_CHIPSET_UNKNOWN;
1418 }
1419 }
1420
1421 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1422 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1423
1424 return 0;
1425 }
1426
1427 static const struct sdhci_ops amd_sdhci_pci_ops = {
1428 .set_clock = sdhci_set_clock,
1429 .enable_dma = sdhci_pci_enable_dma,
1430 .set_bus_width = sdhci_set_bus_width,
1431 .reset = sdhci_reset,
1432 .set_uhs_signaling = sdhci_set_uhs_signaling,
1433 };
1434
1435 static const struct sdhci_pci_fixes sdhci_amd = {
1436 .probe = amd_probe,
1437 .ops = &amd_sdhci_pci_ops,
1438 .probe_slot = amd_probe_slot,
1439 };
1440
1441 static const struct pci_device_id pci_ids[] = {
1442 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1443 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1444 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1445 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1446 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1447 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1448 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1449 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1450 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1451 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1452 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1453 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1454 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1455 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1456 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1457 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1458 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1459 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1460 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1461 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1462 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1463 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1464 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1465 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1466 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1467 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1468 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1469 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1470 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1471 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1472 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1473 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1474 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1475 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1476 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1477 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1478 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1479 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1480 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1481 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1482 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1483 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1484 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1485 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1486 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1487 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1488 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1489 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1490 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1491 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1492 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1493 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1494 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1495 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1496 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1497 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1498 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1499 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1500 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1501 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1502 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1503 SDHCI_PCI_DEVICE(O2, 8120, o2),
1504 SDHCI_PCI_DEVICE(O2, 8220, o2),
1505 SDHCI_PCI_DEVICE(O2, 8221, o2),
1506 SDHCI_PCI_DEVICE(O2, 8320, o2),
1507 SDHCI_PCI_DEVICE(O2, 8321, o2),
1508 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1509 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1510 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1511 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1512 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1513 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1514 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1515 /* Generic SD host controller */
1516 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1517 { /* end: all zeroes */ },
1518 };
1519
1520 MODULE_DEVICE_TABLE(pci, pci_ids);
1521
1522 /*****************************************************************************\
1523 * *
1524 * SDHCI core callbacks *
1525 * *
1526 \*****************************************************************************/
1527
1528 int sdhci_pci_enable_dma(struct sdhci_host *host)
1529 {
1530 struct sdhci_pci_slot *slot;
1531 struct pci_dev *pdev;
1532
1533 slot = sdhci_priv(host);
1534 pdev = slot->chip->pdev;
1535
1536 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1537 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1538 (host->flags & SDHCI_USE_SDMA)) {
1539 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1540 "doesn't fully claim to support it.\n");
1541 }
1542
1543 pci_set_master(pdev);
1544
1545 return 0;
1546 }
1547
1548 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host)
1549 {
1550 struct sdhci_pci_slot *slot = sdhci_priv(host);
1551 int rst_n_gpio = slot->rst_n_gpio;
1552
1553 if (!gpio_is_valid(rst_n_gpio))
1554 return;
1555 gpio_set_value_cansleep(rst_n_gpio, 0);
1556 /* For eMMC, minimum is 1us but give it 10us for good measure */
1557 udelay(10);
1558 gpio_set_value_cansleep(rst_n_gpio, 1);
1559 /* For eMMC, minimum is 200us but give it 300us for good measure */
1560 usleep_range(300, 1000);
1561 }
1562
1563 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1564 {
1565 struct sdhci_pci_slot *slot = sdhci_priv(host);
1566
1567 if (slot->hw_reset)
1568 slot->hw_reset(host);
1569 }
1570
1571 static const struct sdhci_ops sdhci_pci_ops = {
1572 .set_clock = sdhci_set_clock,
1573 .enable_dma = sdhci_pci_enable_dma,
1574 .set_bus_width = sdhci_set_bus_width,
1575 .reset = sdhci_reset,
1576 .set_uhs_signaling = sdhci_set_uhs_signaling,
1577 .hw_reset = sdhci_pci_hw_reset,
1578 };
1579
1580 /*****************************************************************************\
1581 * *
1582 * Suspend/resume *
1583 * *
1584 \*****************************************************************************/
1585
1586 #ifdef CONFIG_PM_SLEEP
1587 static int sdhci_pci_suspend(struct device *dev)
1588 {
1589 struct pci_dev *pdev = to_pci_dev(dev);
1590 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1591
1592 if (!chip)
1593 return 0;
1594
1595 if (chip->fixes && chip->fixes->suspend)
1596 return chip->fixes->suspend(chip);
1597
1598 return sdhci_pci_suspend_host(chip);
1599 }
1600
1601 static int sdhci_pci_resume(struct device *dev)
1602 {
1603 struct pci_dev *pdev = to_pci_dev(dev);
1604 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1605
1606 if (!chip)
1607 return 0;
1608
1609 if (chip->fixes && chip->fixes->resume)
1610 return chip->fixes->resume(chip);
1611
1612 return sdhci_pci_resume_host(chip);
1613 }
1614 #endif
1615
1616 #ifdef CONFIG_PM
1617 static int sdhci_pci_runtime_suspend(struct device *dev)
1618 {
1619 struct pci_dev *pdev = to_pci_dev(dev);
1620 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1621
1622 if (!chip)
1623 return 0;
1624
1625 if (chip->fixes && chip->fixes->runtime_suspend)
1626 return chip->fixes->runtime_suspend(chip);
1627
1628 return sdhci_pci_runtime_suspend_host(chip);
1629 }
1630
1631 static int sdhci_pci_runtime_resume(struct device *dev)
1632 {
1633 struct pci_dev *pdev = to_pci_dev(dev);
1634 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1635
1636 if (!chip)
1637 return 0;
1638
1639 if (chip->fixes && chip->fixes->runtime_resume)
1640 return chip->fixes->runtime_resume(chip);
1641
1642 return sdhci_pci_runtime_resume_host(chip);
1643 }
1644 #endif
1645
1646 static const struct dev_pm_ops sdhci_pci_pm_ops = {
1647 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
1648 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
1649 sdhci_pci_runtime_resume, NULL)
1650 };
1651
1652 /*****************************************************************************\
1653 * *
1654 * Device probing/removal *
1655 * *
1656 \*****************************************************************************/
1657
1658 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
1659 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
1660 int slotno)
1661 {
1662 struct sdhci_pci_slot *slot;
1663 struct sdhci_host *host;
1664 int ret, bar = first_bar + slotno;
1665 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
1666
1667 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
1668 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
1669 return ERR_PTR(-ENODEV);
1670 }
1671
1672 if (pci_resource_len(pdev, bar) < 0x100) {
1673 dev_err(&pdev->dev, "Invalid iomem size. You may "
1674 "experience problems.\n");
1675 }
1676
1677 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1678 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
1679 return ERR_PTR(-ENODEV);
1680 }
1681
1682 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
1683 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
1684 return ERR_PTR(-ENODEV);
1685 }
1686
1687 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
1688 if (IS_ERR(host)) {
1689 dev_err(&pdev->dev, "cannot allocate host\n");
1690 return ERR_CAST(host);
1691 }
1692
1693 slot = sdhci_priv(host);
1694
1695 slot->chip = chip;
1696 slot->host = host;
1697 slot->rst_n_gpio = -EINVAL;
1698 slot->cd_gpio = -EINVAL;
1699 slot->cd_idx = -1;
1700
1701 /* Retrieve platform data if there is any */
1702 if (*sdhci_pci_get_data)
1703 slot->data = sdhci_pci_get_data(pdev, slotno);
1704
1705 if (slot->data) {
1706 if (slot->data->setup) {
1707 ret = slot->data->setup(slot->data);
1708 if (ret) {
1709 dev_err(&pdev->dev, "platform setup failed\n");
1710 goto free;
1711 }
1712 }
1713 slot->rst_n_gpio = slot->data->rst_n_gpio;
1714 slot->cd_gpio = slot->data->cd_gpio;
1715 }
1716
1717 host->hw_name = "PCI";
1718 host->ops = chip->fixes && chip->fixes->ops ?
1719 chip->fixes->ops :
1720 &sdhci_pci_ops;
1721 host->quirks = chip->quirks;
1722 host->quirks2 = chip->quirks2;
1723
1724 host->irq = pdev->irq;
1725
1726 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
1727 if (ret) {
1728 dev_err(&pdev->dev, "cannot request region\n");
1729 goto cleanup;
1730 }
1731
1732 host->ioaddr = pcim_iomap_table(pdev)[bar];
1733
1734 if (chip->fixes && chip->fixes->probe_slot) {
1735 ret = chip->fixes->probe_slot(slot);
1736 if (ret)
1737 goto cleanup;
1738 }
1739
1740 if (gpio_is_valid(slot->rst_n_gpio)) {
1741 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) {
1742 gpio_direction_output(slot->rst_n_gpio, 1);
1743 slot->host->mmc->caps |= MMC_CAP_HW_RESET;
1744 slot->hw_reset = sdhci_pci_gpio_hw_reset;
1745 } else {
1746 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n");
1747 slot->rst_n_gpio = -EINVAL;
1748 }
1749 }
1750
1751 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
1752 host->mmc->slotno = slotno;
1753 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
1754
1755 if (device_can_wakeup(&pdev->dev))
1756 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
1757
1758 if (host->mmc->caps & MMC_CAP_CD_WAKE)
1759 device_init_wakeup(&pdev->dev, true);
1760
1761 if (slot->cd_idx >= 0) {
1762 ret = mmc_gpiod_request_cd(host->mmc, NULL, slot->cd_idx,
1763 slot->cd_override_level, 0, NULL);
1764 if (ret == -EPROBE_DEFER)
1765 goto remove;
1766
1767 if (ret) {
1768 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
1769 slot->cd_idx = -1;
1770 }
1771 }
1772
1773 if (chip->fixes && chip->fixes->add_host)
1774 ret = chip->fixes->add_host(slot);
1775 else
1776 ret = sdhci_add_host(host);
1777 if (ret)
1778 goto remove;
1779
1780 sdhci_pci_add_own_cd(slot);
1781
1782 /*
1783 * Check if the chip needs a separate GPIO for card detect to wake up
1784 * from runtime suspend. If it is not there, don't allow runtime PM.
1785 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure.
1786 */
1787 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm &&
1788 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0)
1789 chip->allow_runtime_pm = false;
1790
1791 return slot;
1792
1793 remove:
1794 if (chip->fixes && chip->fixes->remove_slot)
1795 chip->fixes->remove_slot(slot, 0);
1796
1797 cleanup:
1798 if (slot->data && slot->data->cleanup)
1799 slot->data->cleanup(slot->data);
1800
1801 free:
1802 sdhci_free_host(host);
1803
1804 return ERR_PTR(ret);
1805 }
1806
1807 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
1808 {
1809 int dead;
1810 u32 scratch;
1811
1812 sdhci_pci_remove_own_cd(slot);
1813
1814 dead = 0;
1815 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
1816 if (scratch == (u32)-1)
1817 dead = 1;
1818
1819 sdhci_remove_host(slot->host, dead);
1820
1821 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
1822 slot->chip->fixes->remove_slot(slot, dead);
1823
1824 if (slot->data && slot->data->cleanup)
1825 slot->data->cleanup(slot->data);
1826
1827 sdhci_free_host(slot->host);
1828 }
1829
1830 static void sdhci_pci_runtime_pm_allow(struct device *dev)
1831 {
1832 pm_suspend_ignore_children(dev, 1);
1833 pm_runtime_set_autosuspend_delay(dev, 50);
1834 pm_runtime_use_autosuspend(dev);
1835 pm_runtime_allow(dev);
1836 /* Stay active until mmc core scans for a card */
1837 pm_runtime_put_noidle(dev);
1838 }
1839
1840 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
1841 {
1842 pm_runtime_forbid(dev);
1843 pm_runtime_get_noresume(dev);
1844 }
1845
1846 static int sdhci_pci_probe(struct pci_dev *pdev,
1847 const struct pci_device_id *ent)
1848 {
1849 struct sdhci_pci_chip *chip;
1850 struct sdhci_pci_slot *slot;
1851
1852 u8 slots, first_bar;
1853 int ret, i;
1854
1855 BUG_ON(pdev == NULL);
1856 BUG_ON(ent == NULL);
1857
1858 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
1859 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
1860
1861 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
1862 if (ret)
1863 return ret;
1864
1865 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
1866 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
1867 if (slots == 0)
1868 return -ENODEV;
1869
1870 BUG_ON(slots > MAX_SLOTS);
1871
1872 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
1873 if (ret)
1874 return ret;
1875
1876 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
1877
1878 if (first_bar > 5) {
1879 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
1880 return -ENODEV;
1881 }
1882
1883 ret = pcim_enable_device(pdev);
1884 if (ret)
1885 return ret;
1886
1887 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
1888 if (!chip)
1889 return -ENOMEM;
1890
1891 chip->pdev = pdev;
1892 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
1893 if (chip->fixes) {
1894 chip->quirks = chip->fixes->quirks;
1895 chip->quirks2 = chip->fixes->quirks2;
1896 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
1897 }
1898 chip->num_slots = slots;
1899 chip->pm_retune = true;
1900 chip->rpm_retune = true;
1901
1902 pci_set_drvdata(pdev, chip);
1903
1904 if (chip->fixes && chip->fixes->probe) {
1905 ret = chip->fixes->probe(chip);
1906 if (ret)
1907 return ret;
1908 }
1909
1910 slots = chip->num_slots; /* Quirk may have changed this */
1911
1912 for (i = 0; i < slots; i++) {
1913 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
1914 if (IS_ERR(slot)) {
1915 for (i--; i >= 0; i--)
1916 sdhci_pci_remove_slot(chip->slots[i]);
1917 return PTR_ERR(slot);
1918 }
1919
1920 chip->slots[i] = slot;
1921 }
1922
1923 if (chip->allow_runtime_pm)
1924 sdhci_pci_runtime_pm_allow(&pdev->dev);
1925
1926 return 0;
1927 }
1928
1929 static void sdhci_pci_remove(struct pci_dev *pdev)
1930 {
1931 int i;
1932 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
1933
1934 if (chip->allow_runtime_pm)
1935 sdhci_pci_runtime_pm_forbid(&pdev->dev);
1936
1937 for (i = 0; i < chip->num_slots; i++)
1938 sdhci_pci_remove_slot(chip->slots[i]);
1939 }
1940
1941 static struct pci_driver sdhci_driver = {
1942 .name = "sdhci-pci",
1943 .id_table = pci_ids,
1944 .probe = sdhci_pci_probe,
1945 .remove = sdhci_pci_remove,
1946 .driver = {
1947 .pm = &sdhci_pci_pm_ops
1948 },
1949 };
1950
1951 module_pci_driver(sdhci_driver);
1952
1953 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
1954 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
1955 MODULE_LICENSE("GPL");
Linux with added FPC-III support