drivers/mmc/host/sdhci-pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef __SDHCI_PCI_H
   3 #define __SDHCI_PCI_H
   4
   5 /*
   6  * PCI device IDs, sub IDs
   7  */
   8
   9 #define PCI_DEVICE_ID_O2_SDS0           0x8420
  10 #define PCI_DEVICE_ID_O2_SDS1           0x8421
  11 #define PCI_DEVICE_ID_O2_FUJIN2         0x8520
  12 #define PCI_DEVICE_ID_O2_SEABIRD0       0x8620
  13 #define PCI_DEVICE_ID_O2_SEABIRD1       0x8621
  14
  15 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0   0x8809
  16 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1   0x880a
  17 #define PCI_DEVICE_ID_INTEL_BYT_EMMC    0x0f14
  18 #define PCI_DEVICE_ID_INTEL_BYT_SDIO    0x0f15
  19 #define PCI_DEVICE_ID_INTEL_BYT_SD      0x0f16
  20 #define PCI_DEVICE_ID_INTEL_BYT_EMMC2   0x0f50
  21 #define PCI_DEVICE_ID_INTEL_BSW_EMMC    0x2294
  22 #define PCI_DEVICE_ID_INTEL_BSW_SDIO    0x2295
  23 #define PCI_DEVICE_ID_INTEL_BSW_SD      0x2296
  24 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC   0x1190
  25 #define PCI_DEVICE_ID_INTEL_CLV_SDIO0   0x08f9
  26 #define PCI_DEVICE_ID_INTEL_CLV_SDIO1   0x08fa
  27 #define PCI_DEVICE_ID_INTEL_CLV_SDIO2   0x08fb
  28 #define PCI_DEVICE_ID_INTEL_CLV_EMMC0   0x08e5
  29 #define PCI_DEVICE_ID_INTEL_CLV_EMMC1   0x08e6
  30 #define PCI_DEVICE_ID_INTEL_QRK_SD      0x08A7
  31 #define PCI_DEVICE_ID_INTEL_SPT_EMMC    0x9d2b
  32 #define PCI_DEVICE_ID_INTEL_SPT_SDIO    0x9d2c
  33 #define PCI_DEVICE_ID_INTEL_SPT_SD      0x9d2d
  34 #define PCI_DEVICE_ID_INTEL_DNV_EMMC    0x19db
  35 #define PCI_DEVICE_ID_INTEL_CDF_EMMC    0x18db
  36 #define PCI_DEVICE_ID_INTEL_BXT_SD      0x0aca
  37 #define PCI_DEVICE_ID_INTEL_BXT_EMMC    0x0acc
  38 #define PCI_DEVICE_ID_INTEL_BXT_SDIO    0x0ad0
  39 #define PCI_DEVICE_ID_INTEL_BXTM_SD     0x1aca
  40 #define PCI_DEVICE_ID_INTEL_BXTM_EMMC   0x1acc
  41 #define PCI_DEVICE_ID_INTEL_BXTM_SDIO   0x1ad0
  42 #define PCI_DEVICE_ID_INTEL_APL_SD      0x5aca
  43 #define PCI_DEVICE_ID_INTEL_APL_EMMC    0x5acc
  44 #define PCI_DEVICE_ID_INTEL_APL_SDIO    0x5ad0
  45 #define PCI_DEVICE_ID_INTEL_GLK_SD      0x31ca
  46 #define PCI_DEVICE_ID_INTEL_GLK_EMMC    0x31cc
  47 #define PCI_DEVICE_ID_INTEL_GLK_SDIO    0x31d0
  48 #define PCI_DEVICE_ID_INTEL_CNP_EMMC    0x9dc4
  49 #define PCI_DEVICE_ID_INTEL_CNP_SD      0x9df5
  50 #define PCI_DEVICE_ID_INTEL_CNPH_SD     0xa375
  51
  52 #define PCI_DEVICE_ID_SYSKONNECT_8000   0x8000
  53 #define PCI_DEVICE_ID_VIA_95D0          0x95d0
  54 #define PCI_DEVICE_ID_REALTEK_5250      0x5250
  55
  56 #define PCI_SUBDEVICE_ID_NI_7884        0x7884
  57 #define PCI_SUBDEVICE_ID_NI_78E3        0x78e3
  58
  59 #define PCI_VENDOR_ID_ARASAN            0x16e6
  60 #define PCI_DEVICE_ID_ARASAN_PHY_EMMC   0x0670
  61
  62 /*
  63  * PCI device class and mask
  64  */
  65
  66 #define SYSTEM_SDHCI                    (PCI_CLASS_SYSTEM_SDHCI << 8)
  67 #define PCI_CLASS_MASK                  0xFFFF00
  68
  69 /*
  70  * Macros for PCI device-description
  71  */
  72
  73 #define _PCI_VEND(vend) PCI_VENDOR_ID_##vend
  74 #define _PCI_DEV(vend, dev) PCI_DEVICE_ID_##vend##_##dev
  75 #define _PCI_SUBDEV(subvend, subdev) PCI_SUBDEVICE_ID_##subvend##_##subdev
  76
  77 #define SDHCI_PCI_DEVICE(vend, dev, cfg) { \
  78         .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
  79         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  80         .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  81 }
  82
  83 #define SDHCI_PCI_SUBDEVICE(vend, dev, subvend, subdev, cfg) { \
  84         .vendor = _PCI_VEND(vend), .device = _PCI_DEV(vend, dev), \
  85         .subvendor = _PCI_VEND(subvend), \
  86         .subdevice = _PCI_SUBDEV(subvend, subdev), \
  87         .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  88 }
  89
  90 #define SDHCI_PCI_DEVICE_CLASS(vend, cl, cl_msk, cfg) { \
  91         .vendor = _PCI_VEND(vend), .device = PCI_ANY_ID, \
  92         .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, \
  93         .class = (cl), .class_mask = (cl_msk), \
  94         .driver_data = (kernel_ulong_t)&(sdhci_##cfg) \
  95 }
  96
  97 /*
  98  * PCI registers
  99  */
 100
 101 #define PCI_SDHCI_IFPIO                 0x00
 102 #define PCI_SDHCI_IFDMA                 0x01
 103 #define PCI_SDHCI_IFVENDOR              0x02
 104
 105 #define PCI_SLOT_INFO                   0x40    /* 8 bits */
 106 #define  PCI_SLOT_INFO_SLOTS(x)         ((x >> 4) & 7)
 107 #define  PCI_SLOT_INFO_FIRST_BAR_MASK   0x07
 108
 109 #define MAX_SLOTS                       8
 110
 111 struct sdhci_pci_chip;
 112 struct sdhci_pci_slot;
 113
 114 struct sdhci_pci_fixes {
 115         unsigned int            quirks;
 116         unsigned int            quirks2;
 117         bool                    allow_runtime_pm;
 118         bool                    own_cd_for_runtime_pm;
 119
 120         int                     (*probe) (struct sdhci_pci_chip *);
 121
 122         int                     (*probe_slot) (struct sdhci_pci_slot *);
 123         int                     (*add_host) (struct sdhci_pci_slot *);
 124         void                    (*remove_slot) (struct sdhci_pci_slot *, int);
 125
 126 #ifdef CONFIG_PM_SLEEP
 127         int                     (*suspend) (struct sdhci_pci_chip *);
 128         int                     (*resume) (struct sdhci_pci_chip *);
 129 #endif
 130 #ifdef CONFIG_PM
 131         int                     (*runtime_suspend) (struct sdhci_pci_chip *);
 132         int                     (*runtime_resume) (struct sdhci_pci_chip *);
 133 #endif
 134
 135         const struct sdhci_ops  *ops;
 136         size_t                  priv_size;
 137 };
 138
 139 struct sdhci_pci_slot {
 140         struct sdhci_pci_chip   *chip;
 141         struct sdhci_host       *host;
 142         struct sdhci_pci_data   *data;
 143
 144         int                     rst_n_gpio;
 145         int                     cd_gpio;
 146         int                     cd_irq;
 147
 148         int                     cd_idx;
 149         bool                    cd_override_level;
 150
 151         void (*hw_reset)(struct sdhci_host *host);
 152         unsigned long           private[0] ____cacheline_aligned;
 153 };
 154
 155 struct sdhci_pci_chip {
 156         struct pci_dev          *pdev;
 157
 158         unsigned int            quirks;
 159         unsigned int            quirks2;
 160         bool                    allow_runtime_pm;
 161         bool                    pm_retune;
 162         bool                    rpm_retune;
 163         const struct sdhci_pci_fixes *fixes;
 164
 165         int                     num_slots;      /* Slots on controller */
 166         struct sdhci_pci_slot   *slots[MAX_SLOTS]; /* Pointers to host slots */
 167 };
 168
 169 static inline void *sdhci_pci_priv(struct sdhci_pci_slot *slot)
 170 {
 171         return (void *)slot->private;
 172 }
 173
 174 #ifdef CONFIG_PM_SLEEP
 175 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip);
 176 #endif
 177 int sdhci_pci_enable_dma(struct sdhci_host *host);
 178 int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot);
 179 int sdhci_pci_o2_probe(struct sdhci_pci_chip *chip);
 180 #ifdef CONFIG_PM_SLEEP
 181 int sdhci_pci_o2_resume(struct sdhci_pci_chip *chip);
 182 #endif
 183
 184 extern const struct sdhci_pci_fixes sdhci_arasan;
 185
 186 #endif /* __SDHCI_PCI_H */