2 * Toshiba PCI Secure Digital Host Controller Interface driver
4 * Copyright (C) 2014 Ondrej Zary
5 * Copyright (C) 2007 Richard Betts, All Rights Reserved.
7 * Based on asic3_mmc.c, copyright (c) 2005 SDG Systems, LLC and,
8 * sdhci.c, copyright (C) 2005-2006 Pierre Ossman
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/delay.h>
17 #include <linux/device.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/scatterlist.h>
21 #include <linux/interrupt.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/mmc.h>
30 #define DRIVER_NAME "toshsd"
32 static const struct pci_device_id pci_ids
[] = {
33 { PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA
, 0x0805) },
34 { /* end: all zeroes */ },
37 MODULE_DEVICE_TABLE(pci
, pci_ids
);
39 static void toshsd_init(struct toshsd_host
*host
)
42 pci_write_config_byte(host
->pdev
, SD_PCICFG_CLKSTOP
,
43 SD_PCICFG_CLKSTOP_ENABLE_ALL
);
44 pci_write_config_byte(host
->pdev
, SD_PCICFG_CARDDETECT
, 2);
47 iowrite16(0, host
->ioaddr
+ SD_SOFTWARERESET
); /* assert */
49 iowrite16(1, host
->ioaddr
+ SD_SOFTWARERESET
); /* deassert */
52 /* Clear card registers */
53 iowrite16(0, host
->ioaddr
+ SD_CARDCLOCKCTRL
);
54 iowrite32(0, host
->ioaddr
+ SD_CARDSTATUS
);
55 iowrite32(0, host
->ioaddr
+ SD_ERRORSTATUS0
);
56 iowrite16(0, host
->ioaddr
+ SD_STOPINTERNAL
);
59 iowrite16(0x100, host
->ioaddr
+ SDIO_BASE
+ SDIO_CLOCKNWAITCTRL
);
62 pci_write_config_byte(host
->pdev
, SD_PCICFG_SDLED_ENABLE1
,
63 SD_PCICFG_LED_ENABLE1_START
);
64 pci_write_config_byte(host
->pdev
, SD_PCICFG_SDLED_ENABLE2
,
65 SD_PCICFG_LED_ENABLE2_START
);
67 /* set interrupt masks */
68 iowrite32(~(u32
)(SD_CARD_RESP_END
| SD_CARD_RW_END
69 | SD_CARD_CARD_REMOVED_0
| SD_CARD_CARD_INSERTED_0
70 | SD_BUF_READ_ENABLE
| SD_BUF_WRITE_ENABLE
71 | SD_BUF_CMD_TIMEOUT
),
72 host
->ioaddr
+ SD_INTMASKCARD
);
74 iowrite16(0x1000, host
->ioaddr
+ SD_TRANSACTIONCTRL
);
77 /* Set MMC clock / power.
78 * Note: This controller uses a simple divider scheme therefore it cannot run
79 * SD/MMC cards at full speed (24/20MHz). HCLK (=33MHz PCI clock?) is too high
80 * and the next slowest is 16MHz (div=2).
82 static void __toshsd_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
84 struct toshsd_host
*host
= mmc_priv(mmc
);
90 while (ios
->clock
< HCLK
/ div
)
95 if (div
== 1) { /* disable the divider */
96 pci_write_config_byte(host
->pdev
, SD_PCICFG_CLKMODE
,
97 SD_PCICFG_CLKMODE_DIV_DISABLE
);
98 clk
|= SD_CARDCLK_DIV_DISABLE
;
100 pci_write_config_byte(host
->pdev
, SD_PCICFG_CLKMODE
, 0);
102 clk
|= SD_CARDCLK_ENABLE_CLOCK
;
103 iowrite16(clk
, host
->ioaddr
+ SD_CARDCLOCKCTRL
);
107 iowrite16(0, host
->ioaddr
+ SD_CARDCLOCKCTRL
);
109 switch (ios
->power_mode
) {
111 pci_write_config_byte(host
->pdev
, SD_PCICFG_POWER1
,
118 pci_write_config_byte(host
->pdev
, SD_PCICFG_POWER1
,
120 pci_write_config_byte(host
->pdev
, SD_PCICFG_POWER2
,
121 SD_PCICFG_PWR2_AUTO
);
126 switch (ios
->bus_width
) {
127 case MMC_BUS_WIDTH_1
:
128 iowrite16(SD_CARDOPT_REQUIRED
| SD_CARDOPT_DATA_RESP_TIMEOUT(14)
129 | SD_CARDOPT_C2_MODULE_ABSENT
130 | SD_CARDOPT_DATA_XFR_WIDTH_1
,
131 host
->ioaddr
+ SD_CARDOPTIONSETUP
);
133 case MMC_BUS_WIDTH_4
:
134 iowrite16(SD_CARDOPT_REQUIRED
| SD_CARDOPT_DATA_RESP_TIMEOUT(14)
135 | SD_CARDOPT_C2_MODULE_ABSENT
136 | SD_CARDOPT_DATA_XFR_WIDTH_4
,
137 host
->ioaddr
+ SD_CARDOPTIONSETUP
);
142 static void toshsd_set_led(struct toshsd_host
*host
, unsigned char state
)
144 iowrite16(state
, host
->ioaddr
+ SDIO_BASE
+ SDIO_LEDCTRL
);
147 static void toshsd_finish_request(struct toshsd_host
*host
)
149 struct mmc_request
*mrq
= host
->mrq
;
151 /* Write something to end the command */
156 toshsd_set_led(host
, 0);
157 mmc_request_done(host
->mmc
, mrq
);
160 static irqreturn_t
toshsd_thread_irq(int irq
, void *dev_id
)
162 struct toshsd_host
*host
= dev_id
;
163 struct mmc_data
*data
= host
->data
;
164 struct sg_mapping_iter
*sg_miter
= &host
->sg_miter
;
170 dev_warn(&host
->pdev
->dev
, "Spurious Data IRQ\n");
172 host
->cmd
->error
= -EIO
;
173 toshsd_finish_request(host
);
177 spin_lock_irqsave(&host
->lock
, flags
);
179 if (!sg_miter_next(sg_miter
))
182 buf
= sg_miter
->addr
;
184 /* Ensure we dont read more than one block. The chip will interrupt us
185 * When the next block is available.
187 count
= sg_miter
->length
;
188 if (count
> data
->blksz
)
191 dev_dbg(&host
->pdev
->dev
, "count: %08x, flags %08x\n", count
,
194 /* Transfer the data */
195 if (data
->flags
& MMC_DATA_READ
)
196 ioread32_rep(host
->ioaddr
+ SD_DATAPORT
, buf
, count
>> 2);
198 iowrite32_rep(host
->ioaddr
+ SD_DATAPORT
, buf
, count
>> 2);
200 sg_miter
->consumed
= count
;
201 sg_miter_stop(sg_miter
);
204 spin_unlock_irqrestore(&host
->lock
, flags
);
209 static void toshsd_cmd_irq(struct toshsd_host
*host
)
211 struct mmc_command
*cmd
= host
->cmd
;
216 dev_warn(&host
->pdev
->dev
, "Spurious CMD irq\n");
219 buf
= (u8
*)cmd
->resp
;
222 if (cmd
->flags
& MMC_RSP_PRESENT
&& cmd
->flags
& MMC_RSP_136
) {
225 data
= ioread16(host
->ioaddr
+ SD_RESPONSE0
);
226 buf
[13] = data
& 0xff;
228 data
= ioread16(host
->ioaddr
+ SD_RESPONSE1
);
229 buf
[15] = data
& 0xff;
231 data
= ioread16(host
->ioaddr
+ SD_RESPONSE2
);
232 buf
[9] = data
& 0xff;
234 data
= ioread16(host
->ioaddr
+ SD_RESPONSE3
);
235 buf
[11] = data
& 0xff;
237 data
= ioread16(host
->ioaddr
+ SD_RESPONSE4
);
238 buf
[5] = data
& 0xff;
240 data
= ioread16(host
->ioaddr
+ SD_RESPONSE5
);
241 buf
[7] = data
& 0xff;
243 data
= ioread16(host
->ioaddr
+ SD_RESPONSE6
);
244 buf
[1] = data
& 0xff;
246 data
= ioread16(host
->ioaddr
+ SD_RESPONSE7
);
247 buf
[3] = data
& 0xff;
248 } else if (cmd
->flags
& MMC_RSP_PRESENT
) {
249 /* R1, R1B, R3, R6, R7 */
250 data
= ioread16(host
->ioaddr
+ SD_RESPONSE0
);
251 buf
[0] = data
& 0xff;
253 data
= ioread16(host
->ioaddr
+ SD_RESPONSE1
);
254 buf
[2] = data
& 0xff;
258 dev_dbg(&host
->pdev
->dev
, "Command IRQ complete %d %d %x\n",
259 cmd
->opcode
, cmd
->error
, cmd
->flags
);
261 /* If there is data to handle we will
262 * finish the request in the mmc_data_end_irq handler.*/
266 toshsd_finish_request(host
);
269 static void toshsd_data_end_irq(struct toshsd_host
*host
)
271 struct mmc_data
*data
= host
->data
;
276 dev_warn(&host
->pdev
->dev
, "Spurious data end IRQ\n");
280 if (data
->error
== 0)
281 data
->bytes_xfered
= data
->blocks
* data
->blksz
;
283 data
->bytes_xfered
= 0;
285 dev_dbg(&host
->pdev
->dev
, "Completed data request xfr=%d\n",
288 iowrite16(0, host
->ioaddr
+ SD_STOPINTERNAL
);
290 toshsd_finish_request(host
);
293 static irqreturn_t
toshsd_irq(int irq
, void *dev_id
)
295 struct toshsd_host
*host
= dev_id
;
296 u32 int_reg
, int_mask
, int_status
, detail
;
297 int error
= 0, ret
= IRQ_HANDLED
;
299 spin_lock(&host
->lock
);
300 int_status
= ioread32(host
->ioaddr
+ SD_CARDSTATUS
);
301 int_mask
= ioread32(host
->ioaddr
+ SD_INTMASKCARD
);
302 int_reg
= int_status
& ~int_mask
& ~IRQ_DONT_CARE_BITS
;
304 dev_dbg(&host
->pdev
->dev
, "IRQ status:%x mask:%x\n",
305 int_status
, int_mask
);
307 /* nothing to do: it's not our IRQ */
313 if (int_reg
& SD_BUF_CMD_TIMEOUT
) {
315 dev_dbg(&host
->pdev
->dev
, "Timeout\n");
316 } else if (int_reg
& SD_BUF_CRC_ERR
) {
318 dev_err(&host
->pdev
->dev
, "BadCRC\n");
319 } else if (int_reg
& (SD_BUF_ILLEGAL_ACCESS
320 | SD_BUF_CMD_INDEX_ERR
321 | SD_BUF_STOP_BIT_END_ERR
324 | SD_BUF_DATA_TIMEOUT
)) {
325 dev_err(&host
->pdev
->dev
, "Buffer status error: { %s%s%s%s%s%s}\n",
326 int_reg
& SD_BUF_ILLEGAL_ACCESS
? "ILLEGAL_ACC " : "",
327 int_reg
& SD_BUF_CMD_INDEX_ERR
? "CMD_INDEX " : "",
328 int_reg
& SD_BUF_STOP_BIT_END_ERR
? "STOPBIT_END " : "",
329 int_reg
& SD_BUF_OVERFLOW
? "OVERFLOW " : "",
330 int_reg
& SD_BUF_UNDERFLOW
? "UNDERFLOW " : "",
331 int_reg
& SD_BUF_DATA_TIMEOUT
? "DATA_TIMEOUT " : "");
333 detail
= ioread32(host
->ioaddr
+ SD_ERRORSTATUS0
);
334 dev_err(&host
->pdev
->dev
, "detail error status { %s%s%s%s%s%s%s%s%s%s%s%s%s}\n",
335 detail
& SD_ERR0_RESP_CMD_ERR
? "RESP_CMD " : "",
336 detail
& SD_ERR0_RESP_NON_CMD12_END_BIT_ERR
? "RESP_END_BIT " : "",
337 detail
& SD_ERR0_RESP_CMD12_END_BIT_ERR
? "RESP_END_BIT " : "",
338 detail
& SD_ERR0_READ_DATA_END_BIT_ERR
? "READ_DATA_END_BIT " : "",
339 detail
& SD_ERR0_WRITE_CRC_STATUS_END_BIT_ERR
? "WRITE_CMD_END_BIT " : "",
340 detail
& SD_ERR0_RESP_NON_CMD12_CRC_ERR
? "RESP_CRC " : "",
341 detail
& SD_ERR0_RESP_CMD12_CRC_ERR
? "RESP_CRC " : "",
342 detail
& SD_ERR0_READ_DATA_CRC_ERR
? "READ_DATA_CRC " : "",
343 detail
& SD_ERR0_WRITE_CMD_CRC_ERR
? "WRITE_CMD_CRC " : "",
344 detail
& SD_ERR1_NO_CMD_RESP
? "NO_CMD_RESP " : "",
345 detail
& SD_ERR1_TIMEOUT_READ_DATA
? "READ_DATA_TIMEOUT " : "",
346 detail
& SD_ERR1_TIMEOUT_CRS_STATUS
? "CRS_STATUS_TIMEOUT " : "",
347 detail
& SD_ERR1_TIMEOUT_CRC_BUSY
? "CRC_BUSY_TIMEOUT " : "");
353 host
->cmd
->error
= error
;
355 if (error
== -ETIMEDOUT
) {
356 iowrite32(int_status
&
357 ~(SD_BUF_CMD_TIMEOUT
| SD_CARD_RESP_END
),
358 host
->ioaddr
+ SD_CARDSTATUS
);
361 __toshsd_set_ios(host
->mmc
, &host
->mmc
->ios
);
366 /* Card insert/remove. The mmc controlling code is stateless. */
367 if (int_reg
& (SD_CARD_CARD_INSERTED_0
| SD_CARD_CARD_REMOVED_0
)) {
368 iowrite32(int_status
&
369 ~(SD_CARD_CARD_REMOVED_0
| SD_CARD_CARD_INSERTED_0
),
370 host
->ioaddr
+ SD_CARDSTATUS
);
372 if (int_reg
& SD_CARD_CARD_INSERTED_0
)
375 mmc_detect_change(host
->mmc
, 1);
379 if (int_reg
& (SD_BUF_READ_ENABLE
| SD_BUF_WRITE_ENABLE
)) {
380 iowrite32(int_status
&
381 ~(SD_BUF_WRITE_ENABLE
| SD_BUF_READ_ENABLE
),
382 host
->ioaddr
+ SD_CARDSTATUS
);
384 ret
= IRQ_WAKE_THREAD
;
388 /* Command completion */
389 if (int_reg
& SD_CARD_RESP_END
) {
390 iowrite32(int_status
& ~(SD_CARD_RESP_END
),
391 host
->ioaddr
+ SD_CARDSTATUS
);
392 toshsd_cmd_irq(host
);
395 /* Data transfer completion */
396 if (int_reg
& SD_CARD_RW_END
) {
397 iowrite32(int_status
& ~(SD_CARD_RW_END
),
398 host
->ioaddr
+ SD_CARDSTATUS
);
399 toshsd_data_end_irq(host
);
402 spin_unlock(&host
->lock
);
406 static void toshsd_start_cmd(struct toshsd_host
*host
, struct mmc_command
*cmd
)
408 struct mmc_data
*data
= host
->data
;
411 dev_dbg(&host
->pdev
->dev
, "Command opcode: %d\n", cmd
->opcode
);
413 if (cmd
->opcode
== MMC_STOP_TRANSMISSION
) {
414 iowrite16(SD_STOPINT_ISSUE_CMD12
,
415 host
->ioaddr
+ SD_STOPINTERNAL
);
417 cmd
->resp
[0] = cmd
->opcode
;
422 toshsd_finish_request(host
);
426 switch (mmc_resp_type(cmd
)) {
428 c
|= SD_CMD_RESP_TYPE_NONE
;
432 c
|= SD_CMD_RESP_TYPE_EXT_R1
;
435 c
|= SD_CMD_RESP_TYPE_EXT_R1B
;
438 c
|= SD_CMD_RESP_TYPE_EXT_R2
;
441 c
|= SD_CMD_RESP_TYPE_EXT_R3
;
445 dev_err(&host
->pdev
->dev
, "Unknown response type %d\n",
452 if (cmd
->opcode
== MMC_APP_CMD
)
453 c
|= SD_CMD_TYPE_ACMD
;
455 if (cmd
->opcode
== MMC_GO_IDLE_STATE
)
456 c
|= (3 << 8); /* removed from ipaq-asic3.h for some reason */
459 c
|= SD_CMD_DATA_PRESENT
;
461 if (data
->blocks
> 1) {
462 iowrite16(SD_STOPINT_AUTO_ISSUE_CMD12
,
463 host
->ioaddr
+ SD_STOPINTERNAL
);
464 c
|= SD_CMD_MULTI_BLOCK
;
467 if (data
->flags
& MMC_DATA_READ
)
468 c
|= SD_CMD_TRANSFER_READ
;
470 /* MMC_DATA_WRITE does not require a bit to be set */
473 /* Send the command */
474 iowrite32(cmd
->arg
, host
->ioaddr
+ SD_ARG0
);
475 iowrite16(c
, host
->ioaddr
+ SD_CMD
);
478 static void toshsd_start_data(struct toshsd_host
*host
, struct mmc_data
*data
)
480 unsigned int flags
= SG_MITER_ATOMIC
;
482 dev_dbg(&host
->pdev
->dev
, "setup data transfer: blocksize %08x nr_blocks %d, offset: %08x\n",
483 data
->blksz
, data
->blocks
, data
->sg
->offset
);
487 if (data
->flags
& MMC_DATA_READ
)
488 flags
|= SG_MITER_TO_SG
;
490 flags
|= SG_MITER_FROM_SG
;
492 sg_miter_start(&host
->sg_miter
, data
->sg
, data
->sg_len
, flags
);
494 /* Set transfer length and blocksize */
495 iowrite16(data
->blocks
, host
->ioaddr
+ SD_BLOCKCOUNT
);
496 iowrite16(data
->blksz
, host
->ioaddr
+ SD_CARDXFERDATALEN
);
499 /* Process requests from the MMC layer */
500 static void toshsd_request(struct mmc_host
*mmc
, struct mmc_request
*mrq
)
502 struct toshsd_host
*host
= mmc_priv(mmc
);
505 /* abort if card not present */
506 if (!(ioread16(host
->ioaddr
+ SD_CARDSTATUS
) & SD_CARD_PRESENT_0
)) {
507 mrq
->cmd
->error
= -ENOMEDIUM
;
508 mmc_request_done(mmc
, mrq
);
512 spin_lock_irqsave(&host
->lock
, flags
);
514 WARN_ON(host
->mrq
!= NULL
);
519 toshsd_start_data(host
, mrq
->data
);
521 toshsd_set_led(host
, 1);
523 toshsd_start_cmd(host
, mrq
->cmd
);
525 spin_unlock_irqrestore(&host
->lock
, flags
);
528 static void toshsd_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
530 struct toshsd_host
*host
= mmc_priv(mmc
);
533 spin_lock_irqsave(&host
->lock
, flags
);
534 __toshsd_set_ios(mmc
, ios
);
535 spin_unlock_irqrestore(&host
->lock
, flags
);
538 static int toshsd_get_ro(struct mmc_host
*mmc
)
540 struct toshsd_host
*host
= mmc_priv(mmc
);
543 return !(ioread16(host
->ioaddr
+ SD_CARDSTATUS
) & SD_CARD_WRITE_PROTECT
);
546 static int toshsd_get_cd(struct mmc_host
*mmc
)
548 struct toshsd_host
*host
= mmc_priv(mmc
);
550 return !!(ioread16(host
->ioaddr
+ SD_CARDSTATUS
) & SD_CARD_PRESENT_0
);
553 static const struct mmc_host_ops toshsd_ops
= {
554 .request
= toshsd_request
,
555 .set_ios
= toshsd_set_ios
,
556 .get_ro
= toshsd_get_ro
,
557 .get_cd
= toshsd_get_cd
,
561 static void toshsd_powerdown(struct toshsd_host
*host
)
563 /* mask all interrupts */
564 iowrite32(0xffffffff, host
->ioaddr
+ SD_INTMASKCARD
);
565 /* disable card clock */
566 iowrite16(0x000, host
->ioaddr
+ SDIO_BASE
+ SDIO_CLOCKNWAITCTRL
);
567 iowrite16(0, host
->ioaddr
+ SD_CARDCLOCKCTRL
);
568 /* power down card */
569 pci_write_config_byte(host
->pdev
, SD_PCICFG_POWER1
, SD_PCICFG_PWR1_OFF
);
571 pci_write_config_byte(host
->pdev
, SD_PCICFG_CLKSTOP
, 0);
574 #ifdef CONFIG_PM_SLEEP
575 static int toshsd_pm_suspend(struct device
*dev
)
577 struct pci_dev
*pdev
= to_pci_dev(dev
);
578 struct toshsd_host
*host
= pci_get_drvdata(pdev
);
580 toshsd_powerdown(host
);
582 pci_save_state(pdev
);
583 pci_enable_wake(pdev
, PCI_D3hot
, 0);
584 pci_disable_device(pdev
);
585 pci_set_power_state(pdev
, PCI_D3hot
);
590 static int toshsd_pm_resume(struct device
*dev
)
592 struct pci_dev
*pdev
= to_pci_dev(dev
);
593 struct toshsd_host
*host
= pci_get_drvdata(pdev
);
596 pci_set_power_state(pdev
, PCI_D0
);
597 pci_restore_state(pdev
);
598 ret
= pci_enable_device(pdev
);
606 #endif /* CONFIG_PM_SLEEP */
608 static int toshsd_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
611 struct toshsd_host
*host
;
612 struct mmc_host
*mmc
;
613 resource_size_t base
;
615 ret
= pci_enable_device(pdev
);
619 mmc
= mmc_alloc_host(sizeof(struct toshsd_host
), &pdev
->dev
);
625 host
= mmc_priv(mmc
);
629 pci_set_drvdata(pdev
, host
);
631 ret
= pci_request_regions(pdev
, DRIVER_NAME
);
635 host
->ioaddr
= pci_iomap(pdev
, 0, 0);
641 /* Set MMC host parameters */
642 mmc
->ops
= &toshsd_ops
;
643 mmc
->caps
= MMC_CAP_4_BIT_DATA
;
644 mmc
->ocr_avail
= MMC_VDD_32_33
;
646 mmc
->f_min
= HCLK
/ 512;
649 spin_lock_init(&host
->lock
);
653 ret
= request_threaded_irq(pdev
->irq
, toshsd_irq
, toshsd_thread_irq
,
654 IRQF_SHARED
, DRIVER_NAME
, host
);
660 base
= pci_resource_start(pdev
, 0);
661 dev_dbg(&pdev
->dev
, "MMIO %pa, IRQ %d\n", &base
, pdev
->irq
);
663 pm_suspend_ignore_children(&pdev
->dev
, 1);
668 pci_iounmap(pdev
, host
->ioaddr
);
670 pci_release_regions(pdev
);
673 pci_set_drvdata(pdev
, NULL
);
675 pci_disable_device(pdev
);
679 static void toshsd_remove(struct pci_dev
*pdev
)
681 struct toshsd_host
*host
= pci_get_drvdata(pdev
);
683 mmc_remove_host(host
->mmc
);
684 toshsd_powerdown(host
);
685 free_irq(pdev
->irq
, host
);
686 pci_iounmap(pdev
, host
->ioaddr
);
687 pci_release_regions(pdev
);
688 mmc_free_host(host
->mmc
);
689 pci_set_drvdata(pdev
, NULL
);
690 pci_disable_device(pdev
);
693 static const struct dev_pm_ops toshsd_pm_ops
= {
694 SET_SYSTEM_SLEEP_PM_OPS(toshsd_pm_suspend
, toshsd_pm_resume
)
697 static struct pci_driver toshsd_driver
= {
700 .probe
= toshsd_probe
,
701 .remove
= toshsd_remove
,
702 .driver
.pm
= &toshsd_pm_ops
,
705 module_pci_driver(toshsd_driver
);
707 MODULE_AUTHOR("Ondrej Zary, Richard Betts");
708 MODULE_DESCRIPTION("Toshiba PCI Secure Digital Host Controller Interface driver");
709 MODULE_LICENSE("GPL");